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Tue, 10 Dec 2024 06:55:33 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BA6tXxI004041 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 10 Dec 2024 06:55:33 GMT Received: from robotics-lnxbld017.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 9 Dec 2024 22:55:26 -0800 From: Fange Zhang Date: Tue, 10 Dec 2024 14:53:57 +0800 Subject: [PATCH v4 6/9] drm/msm/dsi: Add dsi phy support for SM6150 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241210-add-display-support-for-qcs615-platform-v4-6-2d875a67602d@quicinc.com> References: <20241210-add-display-support-for-qcs615-platform-v4-0-2d875a67602d@quicinc.com> In-Reply-To: <20241210-add-display-support-for-qcs615-platform-v4-0-2d875a67602d@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , "Bjorn Andersson" , Konrad Dybcio , Fange Zhang , Liu Li , Xiangxu Yin CC: , , , , X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733813687; l=3272; i=quic_fangez@quicinc.com; s=20241014; h=from:subject:message-id; bh=O8+ldMo7RBtiNgUHcF32YKbaoaqudqu+xuNbIbo120E=; b=FTeYH03RpmeRyNkVNB+ZvotzV0WOhnjr9JajAm+cYnDcinVRUrhMuaH7RhNfJrQRypKdIzRjr HASmreTkXGBDrcY/qLqB1Mj8zpezL/xOvWDBY46iRhFet9+u6Pnbblj X-Developer-Key: i=quic_fangez@quicinc.com; a=ed25519; pk=tJv8Cz0npA34ynt53o5GaQfBC0ySFhyb2FGj+V2Use4= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: C5Ha-RjoQ_5KQSBoPYtAKZfz5oV_IvYn X-Proofpoint-GUID: C5Ha-RjoQ_5KQSBoPYtAKZfz5oV_IvYn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 mlxscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412100051 From: Li Liu Add phy configuration for SM6150 Reviewed-by: Dmitry Baryshkov Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 21 +++++++++++++++++++++ 3 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index dd58bc0a49eb5ca96370f7832d9251609ac0c552..c0bcc68289633fd7506ce4f1f96= 3655d862e8f08 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -567,6 +567,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_14nm_8953_cfgs }, { .compatible =3D "qcom,sm6125-dsi-phy-14nm", .data =3D &dsi_phy_14nm_2290_cfgs }, + { .compatible =3D "qcom,sm6150-dsi-phy-14nm", + .data =3D &dsi_phy_14nm_6150_cfgs }, #endif #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY { .compatible =3D "qcom,dsi-phy-10nm", diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index 4953459edd636363614ecad85654614fc95cfa1d..8985818bb2e0934e9084a420c90= e2269c2e1c414 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -46,6 +46,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfg= s; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_6150_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/m= sm/dsi/phy/dsi_phy_14nm.c index 1723f0e4faa4e4fd612d66f9976e80e045eafcc8..2c3cbe0f2870e7d68b9563957de= 8621f7cd36b78 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -1032,6 +1032,10 @@ static const struct regulator_bulk_data dsi_phy_14nm= _73p4mA_regulators[] =3D { { .supply =3D "vcca", .init_load_uA =3D 73400 }, }; =20 +static const struct regulator_bulk_data dsi_phy_14nm_36mA_regulators[] =3D= { + { .supply =3D "vdda", .init_load_uA =3D 36000 }, +}; + const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs =3D { .has_phy_lane =3D true, .regulator_data =3D dsi_phy_14nm_17mA_regulators, @@ -1097,3 +1101,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = =3D { .io_start =3D { 0x5e94400 }, .num_dsi_phy =3D 1, }; + +const struct msm_dsi_phy_cfg dsi_phy_14nm_6150_cfgs =3D { + .has_phy_lane =3D true, + .regulator_data =3D dsi_phy_14nm_36mA_regulators, + .num_regulators =3D ARRAY_SIZE(dsi_phy_14nm_36mA_regulators), + .ops =3D { + .enable =3D dsi_14nm_phy_enable, + .disable =3D dsi_14nm_phy_disable, + .pll_init =3D dsi_pll_14nm_init, + .save_pll_state =3D dsi_14nm_pll_save_state, + .restore_pll_state =3D dsi_14nm_pll_restore_state, + }, + .min_pll_rate =3D VCO_MIN_RATE, + .max_pll_rate =3D VCO_MAX_RATE, + .io_start =3D { 0xae94400 }, + .num_dsi_phy =3D 1, +}; --=20 2.34.1