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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f2d08564sm94543645e9.12.2024.12.10.02.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2024 02:46:44 -0800 (PST) From: Guillaume Stols Date: Tue, 10 Dec 2024 10:46:41 +0000 Subject: [PATCH v2 1/9] iio: adc: ad7606: Fix hardcoded offset in the ADC channels Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241210-ad7606_add_iio_backend_software_mode-v2-1-6619c3e50d81@baylibre.com> References: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> In-Reply-To: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Nuno Sa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, dlechner@baylibre.com, jstephan@baylibre.com, aardelean@baylibre.com, adureghello@baylibre.com, Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733827603; l=7243; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=uS8y4KUjGGFp3SCGu9ptn+1rXRsn3b8FMwtrcYMWjdE=; b=hkwg1GMUOnEH41vU+VyvTShCazCQ+ZNhx/qkEmZgI9x0hhmR0SzOugmDBLZ+0FhJWddgTdi96 EvY0m0OxcoHDhUQskoHc6Yt/sYWaFYgwDzJuCl8b2yTX2TwI82d5ZHR X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= When introducing num_adc_channels, I overlooked some new functions created in a meanwhile that had also the hardcoded offset. This commit adds the new logic to these functions. Fixes: 7a671afeb592 ("iio: adc: ad7606: Introduce num_adc_channels") Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 48 ++++++++++++++++++++++++++++----------------= ---- drivers/iio/adc/ad7606.h | 2 +- 2 files changed, 29 insertions(+), 21 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index e35d55d03d86..d8e3c7a43678 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -175,17 +175,17 @@ static const struct iio_chan_spec ad7616_channels[] = =3D { AD7606_CHANNEL(15, 16), }; =20 -static int ad7606c_18bit_chan_scale_setup(struct ad7606_state *st, +static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch); -static int ad7606c_16bit_chan_scale_setup(struct ad7606_state *st, +static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch); -static int ad7606_16bit_chan_scale_setup(struct ad7606_state *st, +static int ad7606_16bit_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch); -static int ad7607_chan_scale_setup(struct ad7606_state *st, +static int ad7607_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch); -static int ad7608_chan_scale_setup(struct ad7606_state *st, +static int ad7608_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch); -static int ad7609_chan_scale_setup(struct ad7606_state *st, +static int ad7609_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch); =20 const struct ad7606_chip_info ad7605_4_info =3D { @@ -323,9 +323,10 @@ int ad7606_reset(struct ad7606_state *st) } EXPORT_SYMBOL_NS_GPL(ad7606_reset, "IIO_AD7606"); =20 -static int ad7606_16bit_chan_scale_setup(struct ad7606_state *st, +static int ad7606_16bit_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch) { + struct ad7606_state *st =3D iio_priv(indio_dev); struct ad7606_chan_scale *cs =3D &st->chan_scales[ch]; =20 if (!st->sw_mode_en) { @@ -345,10 +346,12 @@ static int ad7606_16bit_chan_scale_setup(struct ad760= 6_state *st, return 0; } =20 -static int ad7606_get_chan_config(struct ad7606_state *st, int ch, +static int ad7606_get_chan_config(struct iio_dev *indio_dev, int ch, bool *bipolar, bool *differential) { - unsigned int num_channels =3D st->chip_info->num_channels - 1; + struct ad7606_state *st =3D iio_priv(indio_dev); + unsigned int num_channels =3D st->chip_info->num_adc_channels; + unsigned int offset =3D indio_dev->num_channels - st->chip_info->num_adc_= channels; struct device *dev =3D st->dev; int ret; =20 @@ -364,7 +367,7 @@ static int ad7606_get_chan_config(struct ad7606_state *= st, int ch, continue; =20 /* channel number (here) is from 1 to num_channels */ - if (reg =3D=3D 0 || reg > num_channels) { + if (reg < offset || reg > num_channels) { dev_warn(dev, "Invalid channel number (ignoring): %d\n", reg); continue; @@ -399,9 +402,10 @@ static int ad7606_get_chan_config(struct ad7606_state = *st, int ch, return 0; } =20 -static int ad7606c_18bit_chan_scale_setup(struct ad7606_state *st, +static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch) { + struct ad7606_state *st =3D iio_priv(indio_dev); struct ad7606_chan_scale *cs =3D &st->chan_scales[ch]; bool bipolar, differential; int ret; @@ -413,7 +417,7 @@ static int ad7606c_18bit_chan_scale_setup(struct ad7606= _state *st, return 0; } =20 - ret =3D ad7606_get_chan_config(st, ch, &bipolar, &differential); + ret =3D ad7606_get_chan_config(indio_dev, ch, &bipolar, &differential); if (ret) return ret; =20 @@ -455,9 +459,10 @@ static int ad7606c_18bit_chan_scale_setup(struct ad760= 6_state *st, return 0; } =20 -static int ad7606c_16bit_chan_scale_setup(struct ad7606_state *st, +static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch) { + struct ad7606_state *st =3D iio_priv(indio_dev); struct ad7606_chan_scale *cs =3D &st->chan_scales[ch]; bool bipolar, differential; int ret; @@ -469,7 +474,7 @@ static int ad7606c_16bit_chan_scale_setup(struct ad7606= _state *st, return 0; } =20 - ret =3D ad7606_get_chan_config(st, ch, &bipolar, &differential); + ret =3D ad7606_get_chan_config(indio_dev, ch, &bipolar, &differential); if (ret) return ret; =20 @@ -512,9 +517,10 @@ static int ad7606c_16bit_chan_scale_setup(struct ad760= 6_state *st, return 0; } =20 -static int ad7607_chan_scale_setup(struct ad7606_state *st, +static int ad7607_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch) { + struct ad7606_state *st =3D iio_priv(indio_dev); struct ad7606_chan_scale *cs =3D &st->chan_scales[ch]; =20 cs->range =3D 0; @@ -523,9 +529,10 @@ static int ad7607_chan_scale_setup(struct ad7606_state= *st, return 0; } =20 -static int ad7608_chan_scale_setup(struct ad7606_state *st, +static int ad7608_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch) { + struct ad7606_state *st =3D iio_priv(indio_dev); struct ad7606_chan_scale *cs =3D &st->chan_scales[ch]; =20 cs->range =3D 0; @@ -534,9 +541,10 @@ static int ad7608_chan_scale_setup(struct ad7606_state= *st, return 0; } =20 -static int ad7609_chan_scale_setup(struct ad7606_state *st, +static int ad7609_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch) { + struct ad7606_state *st =3D iio_priv(indio_dev); struct ad7606_chan_scale *cs =3D &st->chan_scales[ch]; =20 cs->range =3D 0; @@ -1146,8 +1154,8 @@ static int ad7606_sw_mode_setup(struct iio_dev *indio= _dev) =20 static int ad7606_chan_scales_setup(struct iio_dev *indio_dev) { - unsigned int num_channels =3D indio_dev->num_channels - 1; struct ad7606_state *st =3D iio_priv(indio_dev); + unsigned int offset =3D indio_dev->num_channels - st->chip_info->num_adc_= channels; struct iio_chan_spec *chans; size_t size; int ch, ret; @@ -1161,8 +1169,8 @@ static int ad7606_chan_scales_setup(struct iio_dev *i= ndio_dev) memcpy(chans, indio_dev->channels, size); indio_dev->channels =3D chans; =20 - for (ch =3D 0; ch < num_channels; ch++) { - ret =3D st->chip_info->scale_setup_cb(st, &chans[ch + 1], ch); + for (ch =3D 0; ch < st->chip_info->num_adc_channels; ch++) { + ret =3D st->chip_info->scale_setup_cb(indio_dev, &chans[ch + offset], ch= ); if (ret) return ret; } diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 998814a92b82..8778ffe515b3 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -69,7 +69,7 @@ =20 struct ad7606_state; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f2d08564sm94543645e9.12.2024.12.10.02.46.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2024 02:46:45 -0800 (PST) From: Guillaume Stols Date: Tue, 10 Dec 2024 10:46:42 +0000 Subject: [PATCH v2 2/9] dt-bindings: iio: dac: adi-axi-adc: Add ad7606 variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241210-ad7606_add_iio_backend_software_mode-v2-2-6619c3e50d81@baylibre.com> References: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> In-Reply-To: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Nuno Sa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, dlechner@baylibre.com, jstephan@baylibre.com, aardelean@baylibre.com, adureghello@baylibre.com, Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733827603; l=3192; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=gjf0nQQoBWAGsVMcSFONNcDZNY/bgC7yz8ja/yiFY88=; b=U5uvH2PqBtYNE0NXZMnRmVR9BCGsUX1HsccQXBG+CS5RmDUX7t0FcSTM53m5/ppr2Tf/5cXZQ lyjeU6ik+XzAoMrbiP2qT/cNVFbV1lDDTGdghEznHJUVpMwzA5LW9SI X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= A new compatible is added to reflect the specialized version of the HDL. We use the parallel interface to write the ADC's registers, and accessing this interface requires to use ADI_AXI_REG_CONFIG_RD,ADI_AXI_REG_CONFIG_WR and ADI_AXI_REG_CONFIG_CTRL in a custom fashion. Signed-off-by: Guillaume Stols --- .../devicetree/bindings/iio/adc/adi,axi-adc.yaml | 53 ++++++++++++++++++= ++++ 1 file changed, 53 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml b/D= ocumentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml index e1f450b80db2..6c3fc44422cc 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml @@ -17,13 +17,22 @@ description: | interface for the actual ADC, while this IP core will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. + In some cases, the AXI ADC interface is used to perform specialized + operation to a particular ADC, e.g access the physical bus through + specific registers to write ADC registers. + In this case, we use a different compatible whch indicates the target + chip(s)'s name. + The following IP is currently supported: + -axi_ad7606X: Backend for all the chips from the ad7606 family. =20 https://wiki.analog.com/resources/fpga/docs/axi_adc_ip + http://analogdevicesinc.github.io/hdl/library/axi_ad7606x/index.html =20 properties: compatible: enum: - adi,axi-adc-10.0.a + - adi,axi-ad7606x =20 reg: maxItems: 1 @@ -53,6 +62,24 @@ required: - reg - clocks =20 +allOf: + - if: + properties: + compatible: + contains: + const: adi,axi-ad7606x + then: + patternProperties: + "^adc@[0-9a-f]+$": + type: object + properties: + reg: + maxItems: 1 + additionalProperties: true + required: + - compatible + - reg + additionalProperties: false =20 examples: @@ -65,4 +92,30 @@ examples: clocks =3D <&axi_clk>; #io-backend-cells =3D <0>; }; + - | + #include + axi-adc@44a00000 { + compatible =3D "adi,axi-ad7606x"; + reg =3D <0x44a00000 0x10000>; + dmas =3D <&rx_dma 0>; + dma-names =3D "rx"; + clocks =3D <&ext_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + adi_adc@0 { + compatible =3D "adi,ad7606b"; + reg =3D <0>; + pwms =3D <&axi_pwm_gen 0 0>; + pwm-names =3D "cnvst_n"; + avcc-supply =3D <&adc_vref>; + reset-gpios =3D <&gpio0 91 GPIO_ACTIVE_HIGH>; + standby-gpios =3D <&gpio0 90 GPIO_ACTIVE_LOW>; + adi,range-gpios =3D <&gpio0 89 GPIO_ACTIVE_HIGH>; + adi,oversampling-ratio-gpios =3D <&gpio0 88 GPIO_ACTIVE_HIGH + &gpio0 87 GPIO_ACTIVE_HIGH + &gpio0 86 GPIO_ACTIVE_HIGH>; + io-backends =3D <&iio_backend>; + }; + }; ... --=20 2.34.1 From nobody Sun Dec 14 13:58:34 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B88DA2080D2 for ; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f2d08564sm94543645e9.12.2024.12.10.02.46.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2024 02:46:46 -0800 (PST) From: Guillaume Stols Date: Tue, 10 Dec 2024 10:46:43 +0000 Subject: [PATCH v2 3/9] iio:adc: ad7606: Move the software mode configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241210-ad7606_add_iio_backend_software_mode-v2-3-6619c3e50d81@baylibre.com> References: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> In-Reply-To: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Nuno Sa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, dlechner@baylibre.com, jstephan@baylibre.com, aardelean@baylibre.com, adureghello@baylibre.com, Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733827603; l=1867; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=8CKBytTxvAK1VfjipALTFzGnskWpU3gyFxuC+1B1lQ4=; b=yQCFouVxoag5BQErP2fvmfprvbbvFuPiyTt5eNTmh5jTnWgywNDP9uN6Y1Rkc45ikBfJXHv5S 92OXAH2SVm3DJMLqCFp6sSyf2wWiwrRA11wT6SFKbY/GhXkRROOWO/x X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= This is a preparation for the intoduction of the sofware functions in the iio backend version of the driver. The software mode configuration must be executed once the channels are configured, and the number of channels is known. This is not the case before iio-backend's configuration is called, and iio backend version of the driver does not have a timestamp channel. Also the sw_mode_config callback is configured during the iio-backend configuration. For clarity purpose, I moved the entire block instead of just the concerned function calls. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index d8e3c7a43678..dde372ce7569 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -1246,17 +1246,6 @@ int ad7606_probe(struct device *dev, int irq, void _= _iomem *base_address, return -ERESTARTSYS; } =20 - st->write_scale =3D ad7606_write_scale_hw; - st->write_os =3D ad7606_write_os_hw; - - ret =3D ad7606_sw_mode_setup(indio_dev); - if (ret) - return ret; - - ret =3D ad7606_chan_scales_setup(indio_dev); - if (ret) - return ret; - /* If convst pin is not defined, setup PWM. */ if (!st->gpio_convst) { st->cnvst_pwm =3D devm_pwm_get(dev, NULL); @@ -1334,6 +1323,17 @@ int ad7606_probe(struct device *dev, int irq, void _= _iomem *base_address, return ret; } =20 + st->write_scale =3D ad7606_write_scale_hw; + st->write_os =3D ad7606_write_os_hw; + + ret =3D ad7606_sw_mode_setup(indio_dev); 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f2d08564sm94543645e9.12.2024.12.10.02.46.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2024 02:46:47 -0800 (PST) From: Guillaume Stols Date: Tue, 10 Dec 2024 10:46:44 +0000 Subject: [PATCH v2 4/9] iio: adc: ad7606: Move software functions into common file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241210-ad7606_add_iio_backend_software_mode-v2-4-6619c3e50d81@baylibre.com> References: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> In-Reply-To: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Nuno Sa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, dlechner@baylibre.com, jstephan@baylibre.com, aardelean@baylibre.com, adureghello@baylibre.com, Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733827603; l=16918; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=1M1DJAuVZtHPyo/hc5BlyYOmaLWfCXAlD10XfwAfT98=; b=UO5vI6dGg2k12CkmxBOcQUlJFgfgWrEjxxpES63oCLWhuMhHgfzxyAZ+1mHkls264UPMJCKYc 1Jihts09bxQC4QRn0UUeBOoWPfW9q4miZlXYMUbzg2RFbRdHlDDm3MN X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Since the register are always the same, whatever bus is used, moving the software functions into the main file avoids the code to be duplicated in both SPI and parallel version of the driver. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 137 +++++++++++++++++++++++++++++++++++++++= +--- drivers/iio/adc/ad7606.h | 37 ++++++++++-- drivers/iio/adc/ad7606_spi.c | 135 +--------------------------------------= --- 3 files changed, 162 insertions(+), 147 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index dde372ce7569..2f13b9cd2ed2 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -85,6 +85,10 @@ static const unsigned int ad7606_oversampling_avail[7] = =3D { 1, 2, 4, 8, 16, 32, 64, }; =20 +static const unsigned int ad7606b_oversampling_avail[9] =3D { + 1, 2, 4, 8, 16, 32, 64, 128, 256 +}; + static const unsigned int ad7616_oversampling_avail[8] =3D { 1, 2, 4, 8, 16, 32, 64, 128, }; @@ -187,6 +191,8 @@ static int ad7608_chan_scale_setup(struct iio_dev *indi= o_dev, struct iio_chan_spec *chan, int ch); static int ad7609_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch); +static int ad7616_sw_mode_setup(struct iio_dev *indio_dev); +static int ad7606b_sw_mode_setup(struct iio_dev *indio_dev); =20 const struct ad7606_chip_info ad7605_4_info =3D { .channels =3D ad7605_channels, @@ -239,6 +245,7 @@ const struct ad7606_chip_info ad7606b_info =3D { .oversampling_avail =3D ad7606_oversampling_avail, .oversampling_num =3D ARRAY_SIZE(ad7606_oversampling_avail), .scale_setup_cb =3D ad7606_16bit_chan_scale_setup, + .sw_setup_cb =3D ad7606b_sw_mode_setup, }; EXPORT_SYMBOL_NS_GPL(ad7606b_info, "IIO_AD7606"); =20 @@ -250,6 +257,7 @@ const struct ad7606_chip_info ad7606c_16_info =3D { .oversampling_avail =3D ad7606_oversampling_avail, .oversampling_num =3D ARRAY_SIZE(ad7606_oversampling_avail), .scale_setup_cb =3D ad7606c_16bit_chan_scale_setup, + .sw_setup_cb =3D ad7606b_sw_mode_setup, }; EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, "IIO_AD7606"); =20 @@ -294,6 +302,7 @@ const struct ad7606_chip_info ad7606c_18_info =3D { .oversampling_avail =3D ad7606_oversampling_avail, .oversampling_num =3D ARRAY_SIZE(ad7606_oversampling_avail), .scale_setup_cb =3D ad7606c_18bit_chan_scale_setup, + .sw_setup_cb =3D ad7606b_sw_mode_setup, }; EXPORT_SYMBOL_NS_GPL(ad7606c_18_info, "IIO_AD7606"); =20 @@ -307,6 +316,7 @@ const struct ad7606_chip_info ad7616_info =3D { .oversampling_num =3D ARRAY_SIZE(ad7616_oversampling_avail), .os_req_reset =3D true, .scale_setup_cb =3D ad7606_16bit_chan_scale_setup, + .sw_setup_cb =3D ad7616_sw_mode_setup, }; EXPORT_SYMBOL_NS_GPL(ad7616_info, "IIO_AD7606"); =20 @@ -1138,16 +1148,122 @@ static const struct iio_trigger_ops ad7606_trigger= _ops =3D { .validate_device =3D iio_trigger_validate_own_device, }; =20 -static int ad7606_sw_mode_setup(struct iio_dev *indio_dev) +static int ad7606_write_mask(struct ad7606_state *st, + unsigned int addr, + unsigned long mask, + unsigned int val) +{ + int readval; + + readval =3D st->bops->reg_read(st, addr); + if (readval < 0) + return readval; + + readval &=3D ~mask; + readval |=3D val; + + return st->bops->reg_write(st, addr, readval); +} + +static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int va= l) { struct ad7606_state *st =3D iio_priv(indio_dev); + unsigned int ch_addr, mode, ch_index; =20 - st->sw_mode_en =3D st->bops->sw_mode_config && - device_property_present(st->dev, "adi,sw-mode"); - if (!st->sw_mode_en) - return 0; + /* + * Ad7616 has 16 channels divided in group A and group B. + * The range of channels from A are stored in registers with address 4 + * while channels from B are stored in register with address 6. + * The last bit from channels determines if it is from group A or B + * because the order of channels in iio is 0A, 0B, 1A, 1B... + */ + ch_index =3D ch >> 1; + + ch_addr =3D AD7616_RANGE_CH_ADDR(ch_index); + + if ((ch & 0x1) =3D=3D 0) /* channel A */ + ch_addr +=3D AD7616_RANGE_CH_A_ADDR_OFF; + else /* channel B */ + ch_addr +=3D AD7616_RANGE_CH_B_ADDR_OFF; + + /* 0b01 for 2.5v, 0b10 for 5v and 0b11 for 10v */ + mode =3D AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11)); =20 - indio_dev->info =3D &ad7606_info_sw_mode; + return ad7606_write_mask(st, ch_addr, AD7616_RANGE_CH_MSK(ch_index), + mode); +} + +static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + + return ad7606_write_mask(st, AD7616_CONFIGURATION_REGISTER, + AD7616_OS_MASK, val << 2); +} + +static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int va= l) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + + return ad7606_write_mask(st, + AD7606_RANGE_CH_ADDR(ch), + AD7606_RANGE_CH_MSK(ch), + AD7606_RANGE_CH_MODE(ch, val)); +} + +static int ad7606_write_os_sw(struct iio_dev *indio_dev, int val) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + + return st->bops->reg_write(st, AD7606_OS_MODE, val); +} + +static int ad7616_sw_mode_setup(struct iio_dev *indio_dev) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + int ret; + + /* + * Scale can be configured individually for each channel + * in software mode. + */ + + st->write_scale =3D ad7616_write_scale_sw; + st->write_os =3D &ad7616_write_os_sw; + + ret =3D st->bops->sw_mode_config(indio_dev); + if (ret) + return ret; + + /* Activate Burst mode and SEQEN MODE */ + return ad7606_write_mask(st, + AD7616_CONFIGURATION_REGISTER, + AD7616_BURST_MODE | AD7616_SEQEN_MODE, + AD7616_BURST_MODE | AD7616_SEQEN_MODE); +} + +static int ad7606b_sw_mode_setup(struct iio_dev *indio_dev) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + DECLARE_BITMAP(os, 3); + + bitmap_fill(os, 3); + /* + * Software mode is enabled when all three oversampling + * pins are set to high. If oversampling gpios are defined + * in the device tree, then they need to be set to high, + * otherwise, they must be hardwired to VDD + */ + if (st->gpio_os) { + gpiod_set_array_value(st->gpio_os->ndescs, + st->gpio_os->desc, st->gpio_os->info, os); + } + /* OS of 128 and 256 are available only in software mode */ + st->oversampling_avail =3D ad7606b_oversampling_avail; + st->num_os_ratios =3D ARRAY_SIZE(ad7606b_oversampling_avail); + + st->write_scale =3D ad7606_write_scale_sw; + st->write_os =3D &ad7606_write_os_sw; =20 return st->bops->sw_mode_config(indio_dev); } @@ -1326,9 +1442,12 @@ int ad7606_probe(struct device *dev, int irq, void _= _iomem *base_address, st->write_scale =3D ad7606_write_scale_hw; st->write_os =3D ad7606_write_os_hw; =20 - ret =3D ad7606_sw_mode_setup(indio_dev); - if (ret) - return ret; + st->sw_mode_en =3D st->chip_info->sw_setup_cb && + device_property_present(st->dev, "adi,sw-mode"); + if (st->sw_mode_en) { + indio_dev->info =3D &ad7606_info_sw_mode; + st->chip_info->sw_setup_cb(indio_dev); + } =20 ret =3D ad7606_chan_scales_setup(indio_dev); if (ret) diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 8778ffe515b3..7a044b499cfe 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -10,6 +10,36 @@ =20 #define AD760X_MAX_CHANNELS 16 =20 +#define AD7616_CONFIGURATION_REGISTER 0x02 +#define AD7616_OS_MASK GENMASK(4, 2) +#define AD7616_BURST_MODE BIT(6) +#define AD7616_SEQEN_MODE BIT(5) +#define AD7616_RANGE_CH_A_ADDR_OFF 0x04 +#define AD7616_RANGE_CH_B_ADDR_OFF 0x06 +/* + * Range of channels from a group are stored in 2 registers. + * 0, 1, 2, 3 in a register followed by 4, 5, 6, 7 in second register. + * For channels from second group(8-15) the order is the same, only with + * an offset of 2 for register address. + */ +#define AD7616_RANGE_CH_ADDR(ch) ((ch) >> 2) +/* The range of the channel is stored in 2 bits */ +#define AD7616_RANGE_CH_MSK(ch) (0b11 << (((ch) & 0b11) * 2)) +#define AD7616_RANGE_CH_MODE(ch, mode) ((mode) << ((((ch) & 0b11)) * 2)) + +#define AD7606_CONFIGURATION_REGISTER 0x02 +#define AD7606_SINGLE_DOUT 0x00 + +/* + * Range for AD7606B channels are stored in registers starting with addres= s 0x3. + * Each register stores range for 2 channels(4 bits per channel). + */ +#define AD7606_RANGE_CH_MSK(ch) (GENMASK(3, 0) << (4 * ((ch) & 0x1))) +#define AD7606_RANGE_CH_MODE(ch, mode) \ + ((GENMASK(3, 0) & (mode)) << (4 * ((ch) & 0x1))) +#define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) +#define AD7606_OS_MODE 0x08 + #define AD760X_CHANNEL(num, mask_sep, mask_type, mask_all, bits) { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ @@ -71,6 +101,7 @@ struct ad7606_state; =20 typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch); +typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio_dev); =20 /** * struct ad7606_chip_info - chip specific information @@ -80,6 +111,7 @@ typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *i= ndio_dev, * @num_channels: number of channels * @num_adc_channels the number of channels the ADC actually inputs. * @scale_setup_cb: callback to setup the scales for each channel + * @sw_setup_cb: callback to setup the software mode if available. * @oversampling_avail pointer to the array which stores the available * oversampling ratios. * @oversampling_num number of elements stored in oversampling_avail array @@ -94,6 +126,7 @@ struct ad7606_chip_info { unsigned int num_adc_channels; unsigned int num_channels; ad7606_scale_setup_cb_t scale_setup_cb; + ad7606_sw_setup_cb_t sw_setup_cb; const unsigned int *oversampling_avail; unsigned int oversampling_num; bool os_req_reset; @@ -206,10 +239,6 @@ struct ad7606_bus_ops { int (*reg_write)(struct ad7606_state *st, unsigned int addr, unsigned int val); - int (*write_mask)(struct ad7606_state *st, - unsigned int addr, - unsigned long mask, - unsigned int val); int (*update_scan_mode)(struct iio_dev *indio_dev, const unsigned long *s= can_mask); u16 (*rd_wr_cmd)(int addr, char isWriteOp); }; diff --git a/drivers/iio/adc/ad7606_spi.c b/drivers/iio/adc/ad7606_spi.c index e2c147525706..e08563dd1108 100644 --- a/drivers/iio/adc/ad7606_spi.c +++ b/drivers/iio/adc/ad7606_spi.c @@ -15,36 +15,6 @@ =20 #define MAX_SPI_FREQ_HZ 23500000 /* VDRIVE above 4.75 V */ =20 -#define AD7616_CONFIGURATION_REGISTER 0x02 -#define AD7616_OS_MASK GENMASK(4, 2) -#define AD7616_BURST_MODE BIT(6) -#define AD7616_SEQEN_MODE BIT(5) -#define AD7616_RANGE_CH_A_ADDR_OFF 0x04 -#define AD7616_RANGE_CH_B_ADDR_OFF 0x06 -/* - * Range of channels from a group are stored in 2 registers. - * 0, 1, 2, 3 in a register followed by 4, 5, 6, 7 in second register. - * For channels from second group(8-15) the order is the same, only with - * an offset of 2 for register address. - */ -#define AD7616_RANGE_CH_ADDR(ch) ((ch) >> 2) -/* The range of the channel is stored in 2 bits */ -#define AD7616_RANGE_CH_MSK(ch) (0b11 << (((ch) & 0b11) * 2)) -#define AD7616_RANGE_CH_MODE(ch, mode) ((mode) << ((((ch) & 0b11)) * 2)) - -#define AD7606_CONFIGURATION_REGISTER 0x02 -#define AD7606_SINGLE_DOUT 0x00 - -/* - * Range for AD7606B channels are stored in registers starting with addres= s 0x3. - * Each register stores range for 2 channels(4 bits per channel). - */ -#define AD7606_RANGE_CH_MSK(ch) (GENMASK(3, 0) << (4 * ((ch) & 0x1))) -#define AD7606_RANGE_CH_MODE(ch, mode) \ - ((GENMASK(3, 0) & mode) << (4 * ((ch) & 0x1))) -#define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) -#define AD7606_OS_MODE 0x08 - static const struct iio_chan_spec ad7616_sw_channels[] =3D { IIO_CHAN_SOFT_TIMESTAMP(16), AD7616_CHANNEL(0), @@ -89,10 +59,6 @@ static const struct iio_chan_spec ad7606c_18_sw_channels= [] =3D { AD7606_SW_CHANNEL(7, 18), }; =20 -static const unsigned int ad7606B_oversampling_avail[9] =3D { - 1, 2, 4, 8, 16, 32, 64, 128, 256 -}; - static u16 ad7616_spi_rd_wr_cmd(int addr, char isWriteOp) { /* @@ -194,76 +160,6 @@ static int ad7606_spi_reg_write(struct ad7606_state *s= t, return spi_write(spi, &st->d16[0], sizeof(st->d16[0])); } =20 -static int ad7606_spi_write_mask(struct ad7606_state *st, - unsigned int addr, - unsigned long mask, - unsigned int val) -{ - int readval; - - readval =3D st->bops->reg_read(st, addr); - if (readval < 0) - return readval; - - readval &=3D ~mask; - readval |=3D val; - - return st->bops->reg_write(st, addr, readval); -} - -static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int va= l) -{ - struct ad7606_state *st =3D iio_priv(indio_dev); - unsigned int ch_addr, mode, ch_index; - - - /* - * Ad7616 has 16 channels divided in group A and group B. - * The range of channels from A are stored in registers with address 4 - * while channels from B are stored in register with address 6. - * The last bit from channels determines if it is from group A or B - * because the order of channels in iio is 0A, 0B, 1A, 1B... - */ - ch_index =3D ch >> 1; - - ch_addr =3D AD7616_RANGE_CH_ADDR(ch_index); - - if ((ch & 0x1) =3D=3D 0) /* channel A */ - ch_addr +=3D AD7616_RANGE_CH_A_ADDR_OFF; - else /* channel B */ - ch_addr +=3D AD7616_RANGE_CH_B_ADDR_OFF; - - /* 0b01 for 2.5v, 0b10 for 5v and 0b11 for 10v */ - mode =3D AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11)); - return st->bops->write_mask(st, ch_addr, AD7616_RANGE_CH_MSK(ch_index), - mode); -} - -static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val) -{ - struct ad7606_state *st =3D iio_priv(indio_dev); - - return st->bops->write_mask(st, AD7616_CONFIGURATION_REGISTER, - AD7616_OS_MASK, val << 2); -} - -static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int va= l) -{ - struct ad7606_state *st =3D iio_priv(indio_dev); - - return ad7606_spi_write_mask(st, - AD7606_RANGE_CH_ADDR(ch), - AD7606_RANGE_CH_MSK(ch), - AD7606_RANGE_CH_MODE(ch, val)); -} - -static int ad7606_write_os_sw(struct iio_dev *indio_dev, int val) -{ - struct ad7606_state *st =3D iio_priv(indio_dev); - - return ad7606_spi_reg_write(st, AD7606_OS_MODE, val); -} - static int ad7616_sw_mode_config(struct iio_dev *indio_dev) { struct ad7606_state *st =3D iio_priv(indio_dev); @@ -274,38 +170,12 @@ static int ad7616_sw_mode_config(struct iio_dev *indi= o_dev) */ indio_dev->channels =3D ad7616_sw_channels; =20 - st->write_scale =3D ad7616_write_scale_sw; - st->write_os =3D &ad7616_write_os_sw; - - /* Activate Burst mode and SEQEN MODE */ - return st->bops->write_mask(st, - AD7616_CONFIGURATION_REGISTER, - AD7616_BURST_MODE | AD7616_SEQEN_MODE, - AD7616_BURST_MODE | AD7616_SEQEN_MODE); + return 0; } =20 static int ad7606B_sw_mode_config(struct iio_dev *indio_dev) { struct ad7606_state *st =3D iio_priv(indio_dev); - DECLARE_BITMAP(os, 3); - - bitmap_fill(os, 3); - /* - * Software mode is enabled when all three oversampling - * pins are set to high. If oversampling gpios are defined - * in the device tree, then they need to be set to high, - * otherwise, they must be hardwired to VDD - */ - if (st->gpio_os) { - gpiod_set_array_value(st->gpio_os->ndescs, - st->gpio_os->desc, st->gpio_os->info, os); - } - /* OS of 128 and 256 are available only in software mode */ - st->oversampling_avail =3D ad7606B_oversampling_avail; - st->num_os_ratios =3D ARRAY_SIZE(ad7606B_oversampling_avail); - - st->write_scale =3D ad7606_write_scale_sw; - st->write_os =3D &ad7606_write_os_sw; =20 /* Configure device spi to output on a single channel */ st->bops->reg_write(st, @@ -350,7 +220,6 @@ static const struct ad7606_bus_ops ad7616_spi_bops =3D { .read_block =3D ad7606_spi_read_block, .reg_read =3D ad7606_spi_reg_read, .reg_write =3D ad7606_spi_reg_write, - .write_mask =3D ad7606_spi_write_mask, .rd_wr_cmd =3D ad7616_spi_rd_wr_cmd, .sw_mode_config =3D ad7616_sw_mode_config, }; @@ -359,7 +228,6 @@ static const struct ad7606_bus_ops ad7606b_spi_bops =3D= { .read_block =3D ad7606_spi_read_block, .reg_read =3D ad7606_spi_reg_read, .reg_write =3D ad7606_spi_reg_write, - .write_mask =3D ad7606_spi_write_mask, .rd_wr_cmd =3D ad7606B_spi_rd_wr_cmd, .sw_mode_config =3D ad7606B_sw_mode_config, }; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f2d08564sm94543645e9.12.2024.12.10.02.46.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2024 02:46:48 -0800 (PST) From: Guillaume Stols Date: Tue, 10 Dec 2024 10:46:45 +0000 Subject: [PATCH v2 5/9] iio: adc: adi-axi-adc: Add platform children support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241210-ad7606_add_iio_backend_software_mode-v2-5-6619c3e50d81@baylibre.com> References: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> In-Reply-To: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Nuno Sa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, dlechner@baylibre.com, jstephan@baylibre.com, aardelean@baylibre.com, adureghello@baylibre.com, Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733827603; l=4154; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=K0BvGK4oOeIidGmW8aWUPR+jB9kYewVqKo7IDNPdqLw=; b=QvXIoMpjAs3QFvOmcJLXDrJoy19P239MzZoKZ/6dDHf31sx/QoIun+q5eaFSt37jjNUhpp2Dy 519K9hJbc84CW3gLgWTOogPrX6iDvyaddjtg8ZKryCiLGGHD44LDzf9 X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= This is a preparation for the next commit adding support for register read and write functions on AD7606. Since sometimes a bus will be used, it has been agreed during ad3552's driver implementation that the device's driver bus is the backend, whose device node will be a child node. To provide the special callbacks for setting the register, axi-adc needs to pass them to the child device's driver through platform data. Signed-off-by: Guillaume Stols --- drivers/iio/adc/adi-axi-adc.c | 75 +++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 72 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index c7357601f0f8..7ff636643e56 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -80,7 +80,18 @@ ADI_AXI_REG_CHAN_CTRL_FMT_EN | \ ADI_AXI_REG_CHAN_CTRL_ENABLE) =20 +struct axi_adc_info { + unsigned int version; + const struct iio_backend_info *backend_info; + bool bus_controller; + const void *pdata; + unsigned int pdata_sz; +}; + struct adi_axi_adc_state { + /* Target ADC platform device */ + struct platform_device *adc_pdev; + const struct axi_adc_info *info; struct regmap *regmap; struct device *dev; /* lock to protect multiple accesses to the device registers */ @@ -325,6 +336,40 @@ static const struct regmap_config axi_adc_regmap_confi= g =3D { .reg_stride =3D 4, }; =20 +static void axi_adc_child_remove(void *data) +{ + struct adi_axi_adc_state *st =3D data; + + platform_device_unregister(st->adc_pdev); +} + +static int axi_adc_create_platform_device(struct adi_axi_adc_state *st, + struct fwnode_handle *child) +{ + struct platform_device_info pi =3D { + .parent =3D st->dev, + .name =3D fwnode_get_name(child), + .id =3D PLATFORM_DEVID_AUTO, + .fwnode =3D child, + .data =3D st->info->pdata, + .size_data =3D st->info->pdata_sz, + }; + struct platform_device *pdev; + int ret; + + pdev =3D platform_device_register_full(&pi); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + st->adc_pdev =3D pdev; + + ret =3D devm_add_action_or_reset(st->dev, axi_adc_child_remove, st); + if (ret) + return ret; + + return 0; +} + static const struct iio_backend_ops adi_axi_adc_ops =3D { .enable =3D axi_adc_enable, .disable =3D axi_adc_disable, @@ -370,7 +415,9 @@ static int adi_axi_adc_probe(struct platform_device *pd= ev) return dev_err_probe(&pdev->dev, PTR_ERR(st->regmap), "failed to init register map\n"); =20 - expected_ver =3D device_get_match_data(&pdev->dev); + st->info =3D device_get_match_data(&pdev->dev); + + expected_ver =3D &st->info->version; if (!expected_ver) return -ENODEV; =20 @@ -408,6 +455,25 @@ static int adi_axi_adc_probe(struct platform_device *p= dev) return dev_err_probe(&pdev->dev, ret, "failed to register iio backend\n"); =20 + if (st->info->bus_controller) { + device_for_each_child_node_scoped(&pdev->dev, child) { + int val; + + /* Processing only reg 0 node */ + ret =3D fwnode_property_read_u32(child, "reg", &val); + if (ret || val !=3D 0) + continue; + ret =3D fwnode_property_read_u32(child, "io-backends", + &val); + if (ret) + continue; + + ret =3D axi_adc_create_platform_device(st, child); + if (ret) + continue; + } + } + dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n", ADI_AXI_PCORE_VER_MAJOR(ver), ADI_AXI_PCORE_VER_MINOR(ver), @@ -416,11 +482,14 @@ static int adi_axi_adc_probe(struct platform_device *= pdev) return 0; } =20 -static unsigned int adi_axi_adc_10_0_a_info =3D ADI_AXI_PCORE_VER(10, 0, '= a'); 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f2d08564sm94543645e9.12.2024.12.10.02.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2024 02:46:48 -0800 (PST) From: Guillaume Stols Date: Tue, 10 Dec 2024 10:46:46 +0000 Subject: [PATCH v2 6/9] iio: adc: adi-axi-adc: Add support for AD7606 register writing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241210-ad7606_add_iio_backend_software_mode-v2-6-6619c3e50d81@baylibre.com> References: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> In-Reply-To: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Nuno Sa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, dlechner@baylibre.com, jstephan@baylibre.com, aardelean@baylibre.com, adureghello@baylibre.com, Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733827603; l=5558; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=dl8B5isqs0cpK6+0Gxa9yBzmXpvsMpKpjWXkbfyzLUU=; b=4n0W5kzyku2wLD8xi8+1pDXXO992R7e2WDCfxngNm+yKusBtmHCG2Iresog+mp2k4gSMf89bx 5Hcml4eWaXKCUFe0/E5ZVBSKZGw/lgKmneYUXOGlRScm1oq0r3ITF3C X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Since we must access the bus parallel bus using a custom procedure, let's add a specialized compatible, and define specialized callbacks for writing the registers using the parallel interface. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606_bi.h | 16 +++++++ drivers/iio/adc/adi-axi-adc.c | 100 ++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 116 insertions(+) diff --git a/drivers/iio/adc/ad7606_bi.h b/drivers/iio/adc/ad7606_bi.h new file mode 100644 index 000000000000..9ade23ec61dd --- /dev/null +++ b/drivers/iio/adc/ad7606_bi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2010-2024 Analog Devices Inc. + * Copyright (c) 2024 Baylibre, SAS + */ +#ifndef __LINUX_PLATFORM_DATA_AD7606_H__ +#define __LINUX_PLATFORM_DATA_AD7606_H__ + +#include + +struct ad7606_platform_data { + int (*bus_reg_read)(struct iio_backend *back, u32 reg, u32 *val); + int (*bus_reg_write)(struct iio_backend *back, u32 reg, u32 val); +}; + +#endif /* __LINUX_PLATFORM_DATA_AD7606_H__ */ diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index 7ff636643e56..b8bcf89417b0 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -27,6 +27,7 @@ #include #include =20 +#include "ad7606_bi.h" /* * Register definitions: * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map @@ -73,6 +74,12 @@ #define ADI_AXI_ADC_REG_DELAY(l) (0x0800 + (l) * 0x4) #define AXI_ADC_DELAY_CTRL_MASK GENMASK(4, 0) =20 +#define ADI_AXI_REG_CONFIG_WR 0x0080 +#define ADI_AXI_REG_CONFIG_RD 0x0084 +#define ADI_AXI_REG_CONFIG_CTRL 0x008c +#define ADI_AXI_REG_CONFIG_CTRL_READ 0x03 +#define ADI_AXI_REG_CONFIG_CTRL_WRITE 0x01 + #define ADI_AXI_ADC_MAX_IO_NUM_LANES 15 =20 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \ @@ -80,6 +87,11 @@ ADI_AXI_REG_CHAN_CTRL_FMT_EN | \ ADI_AXI_REG_CHAN_CTRL_ENABLE) =20 +/* AD7606's specific */ +#define AD7606_REG_READ_BIT 0x8000 +#define AD7606_REG_ADDRESS_MASK 0xff00 +#define AD7606_REG_VALUE_MASK 0x00ff + struct axi_adc_info { unsigned int version; const struct iio_backend_info *backend_info; @@ -313,6 +325,80 @@ static struct iio_buffer *axi_adc_request_buffer(struc= t iio_backend *back, return iio_dmaengine_buffer_setup(st->dev, indio_dev, dma_name); } =20 +static int axi_adc_raw_write(struct iio_backend *back, void *buf, unsigned= int len) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + u32 data; + u32 *bdata =3D buf; + + data =3D *bdata; + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_WR, data); + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, + ADI_AXI_REG_CONFIG_CTRL_WRITE); + usleep_range(50, 100); + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00); + usleep_range(50, 100); + + return 0; +} + +static int axi_adc_raw_read(struct iio_backend *back, void *buf, unsigned = int len) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + u32 *bdata =3D buf; + + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, + ADI_AXI_REG_CONFIG_CTRL_READ); + usleep_range(50, 100); + regmap_read(st->regmap, ADI_AXI_REG_CONFIG_RD, bdata); + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00); + usleep_range(50, 100); + + return 0; +} + +static int ad7606_bi_reg_read(struct iio_backend *back, u32 reg, u32 *val) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + u32 buf; + + guard(mutex)(&st->lock); + + /* + * The address is written on the highest weight byte, and the MSB set at 1 + * indicates a read operation. + */ + buf =3D FIELD_PREP(AD7606_REG_ADDRESS_MASK, reg) | AD7606_REG_READ_BIT; + axi_adc_raw_write(back, &buf, sizeof(buf)); + axi_adc_raw_read(back, val, 4); + + /* Write 0x0 on the bus to get back to ADC mode */ + buf =3D 0; + axi_adc_raw_write(back, &buf, sizeof(buf)); + return 0; +} + +static int ad7606_bi_reg_write(struct iio_backend *back, u32 reg, u32 val) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + u32 buf; + + guard(mutex)(&st->lock); + + /* Read any register to switch to register mode */ + buf =3D 0xaf00; + axi_adc_raw_write(back, &buf, sizeof(buf)); + + buf =3D FIELD_PREP(AD7606_REG_ADDRESS_MASK, reg) | FIELD_PREP(AD7606_REG_= VALUE_MASK, val); + axi_adc_raw_write(back, &buf, sizeof(buf)); + + /* Write 0x0 on the bus to get back to ADC mode */ + buf =3D 0; + axi_adc_raw_write(back, &buf, sizeof(buf)); + + return 0; +} + static void axi_adc_free_buffer(struct iio_backend *back, struct iio_buffer *buffer) { @@ -487,9 +573,23 @@ static const struct axi_adc_info adc_generic =3D { .backend_info =3D &adi_axi_adc_generic, }; =20 +static const struct ad7606_platform_data ad7606_pdata =3D { + .bus_reg_read =3D ad7606_bi_reg_read, + .bus_reg_write =3D ad7606_bi_reg_write, +}; + +static const struct axi_adc_info adc_ad7606 =3D { + .version =3D ADI_AXI_PCORE_VER(10, 0, 'a'), + .backend_info =3D &adi_axi_adc_generic, + .bus_controller =3D true, + .pdata =3D &ad7606_pdata, + .pdata_sz =3D sizeof(ad7606_pdata), +}; + /* Match table for of_platform binding */ static const struct of_device_id adi_axi_adc_of_match[] =3D { { .compatible =3D "adi,axi-adc-10.0.a", .data =3D &adc_generic }, + { .compatible =3D "adi,axi-ad7606x", .data =3D &adc_ad7606 }, { /* end of list */ } }; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f2d08564sm94543645e9.12.2024.12.10.02.46.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2024 02:46:49 -0800 (PST) From: Guillaume Stols Date: Tue, 10 Dec 2024 10:46:47 +0000 Subject: [PATCH v2 7/9] iio: adc: ad7606: change r/w_register signature Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241210-ad7606_add_iio_backend_software_mode-v2-7-6619c3e50d81@baylibre.com> References: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> In-Reply-To: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Nuno Sa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, dlechner@baylibre.com, jstephan@baylibre.com, aardelean@baylibre.com, adureghello@baylibre.com, Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733827603; l=6288; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=PAZUr7a+ezpER6BWIGM0HmPI8Y0j/PqczoFzw8Wo+qI=; b=kGl0VZMMI642Noohf4u4Y7XOae6Zv5MSFH9dcnaX5h9+6gDm+tHjOm2bAAP8SwyXR0wa1nCt3 Q2U3oJSTfsaC9ovJtp2720O1kI/dkHNn13DHvyckc/HhRdO3Xj2Mr81 X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= The register read/write with IIO backend will require to claim the direct mode, and doing so requires passing the corresponding iio_dev structure. So we need to modify the function signature to pass the iio_dev structure. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 25 +++++++++++-------------- drivers/iio/adc/ad7606.h | 8 ++++---- drivers/iio/adc/ad7606_spi.c | 10 +++++----- 3 files changed, 20 insertions(+), 23 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 2f13b9cd2ed2..bf1f84367c72 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -574,13 +574,13 @@ static int ad7606_reg_access(struct iio_dev *indio_de= v, guard(mutex)(&st->lock); =20 if (readval) { - ret =3D st->bops->reg_read(st, reg); + ret =3D st->bops->reg_read(indio_dev, reg); if (ret < 0) return ret; *readval =3D ret; return 0; } else { - return st->bops->reg_write(st, reg, writeval); + return st->bops->reg_write(indio_dev, reg, writeval); } } =20 @@ -1148,26 +1148,26 @@ static const struct iio_trigger_ops ad7606_trigger_= ops =3D { .validate_device =3D iio_trigger_validate_own_device, }; =20 -static int ad7606_write_mask(struct ad7606_state *st, +static int ad7606_write_mask(struct iio_dev *indio_dev, unsigned int addr, unsigned long mask, unsigned int val) { + struct ad7606_state *st =3D iio_priv(indio_dev); int readval; =20 - readval =3D st->bops->reg_read(st, addr); + readval =3D st->bops->reg_read(indio_dev, addr); if (readval < 0) return readval; =20 readval &=3D ~mask; readval |=3D val; =20 - return st->bops->reg_write(st, addr, readval); + return st->bops->reg_write(indio_dev, addr, readval); } =20 static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int va= l) { - struct ad7606_state *st =3D iio_priv(indio_dev); unsigned int ch_addr, mode, ch_index; =20 /* @@ -1189,23 +1189,20 @@ static int ad7616_write_scale_sw(struct iio_dev *in= dio_dev, int ch, int val) /* 0b01 for 2.5v, 0b10 for 5v and 0b11 for 10v */ mode =3D AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11)); =20 - return ad7606_write_mask(st, ch_addr, AD7616_RANGE_CH_MSK(ch_index), + return ad7606_write_mask(indio_dev, ch_addr, AD7616_RANGE_CH_MSK(ch_index= ), mode); } =20 static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val) { - struct ad7606_state *st =3D iio_priv(indio_dev); =20 - return ad7606_write_mask(st, AD7616_CONFIGURATION_REGISTER, + return ad7606_write_mask(indio_dev, AD7616_CONFIGURATION_REGISTER, AD7616_OS_MASK, val << 2); } =20 static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int va= l) { - struct ad7606_state *st =3D iio_priv(indio_dev); - - return ad7606_write_mask(st, + return ad7606_write_mask(indio_dev, AD7606_RANGE_CH_ADDR(ch), AD7606_RANGE_CH_MSK(ch), AD7606_RANGE_CH_MODE(ch, val)); @@ -1215,7 +1212,7 @@ static int ad7606_write_os_sw(struct iio_dev *indio_d= ev, int val) { struct ad7606_state *st =3D iio_priv(indio_dev); =20 - return st->bops->reg_write(st, AD7606_OS_MODE, val); + return st->bops->reg_write(indio_dev, AD7606_OS_MODE, val); } =20 static int ad7616_sw_mode_setup(struct iio_dev *indio_dev) @@ -1236,7 +1233,7 @@ static int ad7616_sw_mode_setup(struct iio_dev *indio= _dev) return ret; =20 /* Activate Burst mode and SEQEN MODE */ - return ad7606_write_mask(st, + return ad7606_write_mask(indio_dev, AD7616_CONFIGURATION_REGISTER, AD7616_BURST_MODE | AD7616_SEQEN_MODE, AD7616_BURST_MODE | AD7616_SEQEN_MODE); diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 7a044b499cfe..eca7ea99e24d 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -235,10 +235,10 @@ struct ad7606_bus_ops { int (*iio_backend_config)(struct device *dev, struct iio_dev *indio_dev); int (*read_block)(struct device *dev, int num, void *data); int (*sw_mode_config)(struct iio_dev *indio_dev); - int (*reg_read)(struct ad7606_state *st, unsigned int addr); - int (*reg_write)(struct ad7606_state *st, - unsigned int addr, - unsigned int val); + int (*reg_read)(struct iio_dev *indio_dev, unsigned int addr); + int (*reg_write)(struct iio_dev *indio_dev, + unsigned int addr, + unsigned int val); int (*update_scan_mode)(struct iio_dev *indio_dev, const unsigned long *s= can_mask); u16 (*rd_wr_cmd)(int addr, char isWriteOp); }; diff --git a/drivers/iio/adc/ad7606_spi.c b/drivers/iio/adc/ad7606_spi.c index e08563dd1108..15bfa7a427d9 100644 --- a/drivers/iio/adc/ad7606_spi.c +++ b/drivers/iio/adc/ad7606_spi.c @@ -124,8 +124,9 @@ static int ad7606_spi_read_block18to32(struct device *d= ev, return spi_sync_transfer(spi, &xfer, 1); } =20 -static int ad7606_spi_reg_read(struct ad7606_state *st, unsigned int addr) +static int ad7606_spi_reg_read(struct iio_dev *indio_dev, unsigned int add= r) { + struct ad7606_state *st =3D iio_priv(indio_dev); struct spi_device *spi =3D to_spi_device(st->dev); struct spi_transfer t[] =3D { { @@ -148,10 +149,11 @@ static int ad7606_spi_reg_read(struct ad7606_state *s= t, unsigned int addr) return be16_to_cpu(st->d16[1]); } =20 -static int ad7606_spi_reg_write(struct ad7606_state *st, +static int ad7606_spi_reg_write(struct iio_dev *indio_dev, unsigned int addr, unsigned int val) { + struct ad7606_state *st =3D iio_priv(indio_dev); struct spi_device *spi =3D to_spi_device(st->dev); =20 st->d16[0] =3D cpu_to_be16((st->bops->rd_wr_cmd(addr, 1) << 8) | @@ -162,8 +164,6 @@ static int ad7606_spi_reg_write(struct ad7606_state *st, =20 static int ad7616_sw_mode_config(struct iio_dev *indio_dev) { - struct ad7606_state *st =3D iio_priv(indio_dev); - /* * Scale can be configured individually for each channel * in software mode. @@ -178,7 +178,7 @@ static int ad7606B_sw_mode_config(struct iio_dev *indio= _dev) struct ad7606_state *st =3D iio_priv(indio_dev); =20 /* Configure device spi to output on a single channel */ - st->bops->reg_write(st, + st->bops->reg_write(indio_dev, AD7606_CONFIGURATION_REGISTER, AD7606_SINGLE_DOUT); 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f2d08564sm94543645e9.12.2024.12.10.02.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2024 02:46:50 -0800 (PST) From: Guillaume Stols Date: Tue, 10 Dec 2024 10:46:48 +0000 Subject: [PATCH v2 8/9] iio: adc: ad7606: Change channel macros parameters Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241210-ad7606_add_iio_backend_software_mode-v2-8-6619c3e50d81@baylibre.com> References: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> In-Reply-To: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Nuno Sa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, dlechner@baylibre.com, jstephan@baylibre.com, aardelean@baylibre.com, adureghello@baylibre.com, Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733827603; l=3162; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=q8L+/X8mQMclZDxDMNMoohPiMsPmm9wiBCl25kpj+IE=; b=S0PrQp4CIcaxFv3AH+5EAQczxw7xbqwMk5SsilNV/T3/SOiEvKEaXgaZBKeehaiSvRB0PB77n B6xClCSvw8FBS84JkOGiRXfg6iHJ/KyRZVVE7mrwobh3jw1bjQdzQg0 X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Add the possibility to pass the *_available parameters to the main macro. This is a preparation to add the new channels for software mode and hardware mode in iio backend mode more easily. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.h | 51 ++++++++++++++++++++++++--------------------= ---- 1 file changed, 25 insertions(+), 26 deletions(-) diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index eca7ea99e24d..ada8065fba4e 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -40,37 +40,19 @@ #define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) #define AD7606_OS_MODE 0x08 =20 -#define AD760X_CHANNEL(num, mask_sep, mask_type, mask_all, bits) { \ +#define AD760X_CHANNEL(num, mask_sep, mask_type, mask_all, \ + mask_sep_avail, mask_all_avail, bits) { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ .channel =3D num, \ .address =3D num, \ .info_mask_separate =3D mask_sep, \ + .info_mask_separate_available =3D \ + mask_sep_avail, \ .info_mask_shared_by_type =3D mask_type, \ .info_mask_shared_by_all =3D mask_all, \ - .scan_index =3D num, \ - .scan_type =3D { \ - .sign =3D 's', \ - .realbits =3D (bits), \ - .storagebits =3D (bits) > 16 ? 32 : 16, \ - .endianness =3D IIO_CPU, \ - }, \ -} - -#define AD7606_SW_CHANNEL(num, bits) { \ - .type =3D IIO_VOLTAGE, \ - .indexed =3D 1, \ - .channel =3D num, \ - .address =3D num, \ - .info_mask_separate =3D \ - BIT(IIO_CHAN_INFO_RAW) | \ - BIT(IIO_CHAN_INFO_SCALE), \ - .info_mask_separate_available =3D \ - BIT(IIO_CHAN_INFO_SCALE), \ - .info_mask_shared_by_all =3D \ - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_shared_by_all_available =3D \ - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + mask_all_avail, \ .scan_index =3D num, \ .scan_type =3D { \ .sign =3D 's', \ @@ -80,14 +62,30 @@ }, \ } =20 +#define AD7606_SW_CHANNEL(num, bits) \ + AD760X_CHANNEL(num, \ + /* mask separate */ \ + BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + /* mask type */ \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + /* mask all */ \ + 0, \ + /* mask separate available */ \ + BIT(IIO_CHAN_INFO_SCALE), \ + /* mask all available */ \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + bits) + #define AD7605_CHANNEL(num) \ AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW), \ - BIT(IIO_CHAN_INFO_SCALE), 0, 16) + BIT(IIO_CHAN_INFO_SCALE), 0, 0, 0, 16) =20 #define AD7606_CHANNEL(num, bits) \ AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW), \ BIT(IIO_CHAN_INFO_SCALE), \ - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), bits) + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + 0, 0, bits) =20 #define AD7616_CHANNEL(num) AD7606_SW_CHANNEL(num, 16) =20 @@ -95,7 +93,8 @@ AD760X_CHANNEL(num, 0, \ BIT(IIO_CHAN_INFO_SCALE), \ BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 16) + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + 0, 0, 16) =20 struct ad7606_state; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f2d08564sm94543645e9.12.2024.12.10.02.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2024 02:46:51 -0800 (PST) From: Guillaume Stols Date: Tue, 10 Dec 2024 10:46:49 +0000 Subject: [PATCH v2 9/9] iio: adc: ad7606: Add support for writing registers when using backend Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241210-ad7606_add_iio_backend_software_mode-v2-9-6619c3e50d81@baylibre.com> References: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> In-Reply-To: <20241210-ad7606_add_iio_backend_software_mode-v2-0-6619c3e50d81@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Nuno Sa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, dlechner@baylibre.com, jstephan@baylibre.com, aardelean@baylibre.com, adureghello@baylibre.com, Guillaume Stols X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733827603; l=3756; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=0DaB6GUhAdZIbGZ7qGgEv5Jwt3U+pqBjdF0vztCbme8=; b=gEIvVwbhrXDeyaZABlBonAmGn84SE5hpsvXKnT+vORvDnqx0Z6zNTjnCRiYqsAota1JS8e1Bi q+HCIlVvtLMAW5JB1GpDt6qaVTT8+Tmrc9HLf0S4wuIiw06n/Qrp+ff X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Adds the logic for effectively enabling the software mode for the iio-backend, i.e enabling the software mode channel configuration and implementing the register writing functions. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.h | 15 ++++++++++++ drivers/iio/adc/ad7606_par.c | 56 ++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 71 insertions(+) diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index ada8065fba4e..9da39c2d5d53 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -96,6 +96,21 @@ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 0, 0, 16) =20 +#define AD7606_BI_SW_CHANNEL(num) \ + AD760X_CHANNEL(num, \ + /* mask separate */ \ + BIT(IIO_CHAN_INFO_SCALE), \ + /* mask type */ \ + 0, \ + /* mask all */ \ + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + /* mask separate available */ \ + BIT(IIO_CHAN_INFO_SCALE), \ + /* mask all available */ \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + 16) + struct ad7606_state; =20 typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev, diff --git a/drivers/iio/adc/ad7606_par.c b/drivers/iio/adc/ad7606_par.c index 64733b607aa8..c159cd4f7802 100644 --- a/drivers/iio/adc/ad7606_par.c +++ b/drivers/iio/adc/ad7606_par.c @@ -13,12 +13,14 @@ #include #include #include +#include #include =20 #include #include =20 #include "ad7606.h" +#include "ad7606_bi.h" =20 static const struct iio_chan_spec ad7606b_bi_channels[] =3D { AD7606_BI_CHANNEL(0), @@ -31,6 +33,17 @@ static const struct iio_chan_spec ad7606b_bi_channels[] = =3D { AD7606_BI_CHANNEL(7), }; =20 +static const struct iio_chan_spec ad7606b_bi_sw_channels[] =3D { + AD7606_BI_SW_CHANNEL(0), + AD7606_BI_SW_CHANNEL(1), + AD7606_BI_SW_CHANNEL(2), + AD7606_BI_SW_CHANNEL(3), + AD7606_BI_SW_CHANNEL(4), + AD7606_BI_SW_CHANNEL(5), + AD7606_BI_SW_CHANNEL(6), + AD7606_BI_SW_CHANNEL(7), +}; + static int ad7606_bi_update_scan_mode(struct iio_dev *indio_dev, const uns= igned long *scan_mask) { struct ad7606_state *st =3D iio_priv(indio_dev); @@ -86,9 +99,52 @@ static int ad7606_bi_setup_iio_backend(struct device *de= v, struct iio_dev *indio return 0; } =20 +static int ad7606_bi_reg_read(struct iio_dev *indio_dev, unsigned int addr) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + int val, ret; + struct ad7606_platform_data *pdata =3D st->dev->platform_data; + + iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { + ret =3D pdata->bus_reg_read(st->back, + addr, + &val); + } + if (ret < 0) + return ret; + + return val; +} + +static int ad7606_bi_reg_write(struct iio_dev *indio_dev, + unsigned int addr, + unsigned int val) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + struct ad7606_platform_data *pdata =3D st->dev->platform_data; + int ret; + + iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { + ret =3D pdata->bus_reg_write(st->back, + addr, + val); + } + return ret; +} + +static int ad7606_bi_sw_mode_config(struct iio_dev *indio_dev) +{ + indio_dev->channels =3D ad7606b_bi_sw_channels; + + return 0; +} + static const struct ad7606_bus_ops ad7606_bi_bops =3D { .iio_backend_config =3D ad7606_bi_setup_iio_backend, .update_scan_mode =3D ad7606_bi_update_scan_mode, + .reg_read =3D ad7606_bi_reg_read, + .reg_write =3D ad7606_bi_reg_write, + .sw_mode_config =3D ad7606_bi_sw_mode_config, }; =20 static int ad7606_par16_read_block(struct device *dev, --=20 2.34.1