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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH v3 01/15] cpufreq/amd-pstate: Store the boost numerator as highest perf again Date: Mon, 9 Dec 2024 12:52:34 -0600 Message-ID: <20241209185248.16301-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241209185248.16301-1-mario.limonciello@amd.com> References: <20241209185248.16301-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A348:EE_|SA3PR12MB8811:EE_ X-MS-Office365-Filtering-Correlation-Id: 49d8cd2f-e185-4c10-ae0d-08dd1882ba86 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?v/GfTwlUE9cHn9i1PC1zYAMqmLrox4KYq2w8/YbnkuEqDh0Lh8BbfifxPY8M?= =?us-ascii?Q?xODjsP2Xkc2z6U7YoWCt7gNes1ey0x82GqQWHnBIgBIxEQjVXz/nl/s59d+s?= =?us-ascii?Q?gTw8RUeCugf+DpST/S0LMXXEiadR61wJxKQu+35MrpiPn3aKsvqGg5YPQOYX?= =?us-ascii?Q?AAA67gIO8tyj3qdlplaC7ReGUJPE54VSwEz9WC7maXJBukKoKRiwRTF/dEkX?= =?us-ascii?Q?bgv8C15rfl23CJFQDk3SvtCHqfU3KG04BzBViZaTq70b/dtrt0aCiEccWQDk?= =?us-ascii?Q?fjTQ0svtIOKjAb45VwyUOFmU6I9qxafjKkEbGXazMN9BcNJxsvL/MAaM7Qs2?= =?us-ascii?Q?rXMyO3jOGnxxJeib5LrXbswLd/QjcemSGB1Q1q/AquMfZuXK/y8fbfetn3OP?= =?us-ascii?Q?XDijK9+DZ1KU8r2ZtGyFn8H3Tvk4NhjvrrSK1AAodGNaeRLKZ7quhuijVGV2?= =?us-ascii?Q?V/MAiMUApVLt3FU1olP/IRtN8wIAugp0fN2wikzN5ohyGyDangYD9wt+4KyG?= =?us-ascii?Q?CS7qqWRSp1cezpsK9nHZpZi2rwP15l8shUQ29mkVU9rvWTuTFZB0slWMB0Au?= =?us-ascii?Q?FoY17nWP5GqSYLljjBf8/QktmPwAa7WtnizxFo/iHKHBa6Faf4p3bqPohM8B?= =?us-ascii?Q?klHWmqyJasJmJ94Z8NnOdEG0pVgjlXCVHUIrBNUYcYYZ7GgnMD5oDwV8ZmqQ?= =?us-ascii?Q?ZE+ZuhxrRy0Hjn8S/4tmCUi0ml5k/Yn43zj5HqfbVOramZJ0M0WrM1KlUi3j?= =?us-ascii?Q?WxjSKqTlwRaP89eB8wMu4nIDlqRrafPkqzk8BMbuweshpnA54uG7V3RSHEbx?= =?us-ascii?Q?YHSxC4O8aLWNJBNXxYZjiGE9KiDNe4qOX9DsgjRFGh1s5+9eAOh3uQ2Plrrv?= =?us-ascii?Q?7AfqqofdqNbKtuqlCx28ZooekY/7/8Ig5krf6ddkgDW9L0F5Z1xNTRR9oztc?= =?us-ascii?Q?eFmm+nh/SkyzdZ7nF45Jg26X5FH0jKhj+C6AEnWO1fnSv/XjvxrKZkYkqjpR?= =?us-ascii?Q?JYze4BNFt6wobc9JP8/9q9Mf/LyWa7QPPTQPcSOEu77CaB0ddyEbXup4Bzoy?= =?us-ascii?Q?A9IbAeA4rcOD6mzLzLW/tjgf38UaeHhfFrZJDlrylUHxrdSkuYDPFane5FNn?= =?us-ascii?Q?JG3j5XWskhH6Goqv7RX2gi8sdFI+a4QA8FGCOjE4VZuN8QGVZwR7rpcIJvcv?= =?us-ascii?Q?w1Ejbcp6LYpaP3ALYd3xwSL6aitkqW9DOm/kegTEDjWO2L6sEaTa8nV5Pk09?= =?us-ascii?Q?ln5nkbq//9tBu1ETgwLePiU6pCZFOIHWNVIaHqAaXU81Zpr69ai0vma6flkt?= =?us-ascii?Q?QpIzPo7Ant580AZq7evKFt6oNt1ZNH4zOaFN/y9mlx50tL7h04EyF3itkBGN?= =?us-ascii?Q?JOyIoC5u8diRlRS8OQBb3C0DZtcs1oTbF0iBL6Ttnp/8G2OHcUoxwkCciAt7?= =?us-ascii?Q?C1uUH+RtYeOTudWfguXdPG+erWFpirNZ?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2024 18:53:10.9744 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49d8cd2f-e185-4c10-ae0d-08dd1882ba86 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A348.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8811 Content-Type: text/plain; charset="utf-8" commit ad4caad58d91d ("cpufreq: amd-pstate: Merge amd_pstate_highest_perf_set() into amd_get_boost_ratio_numerator()") changed the semantics for highest perf and commit 18d9b52271213 ("cpufreq/amd-pstate: Use nominal perf for limits when boost is disabled") worked around those semantic changes. This however is a confusing result and furthermore makes it awkward to change frequency limits and boost due to the scaling differences. Restore the boost numerator to highest perf again. Suggested-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy Fixes: ad4caad58d91 ("cpufreq: amd-pstate: Merge amd_pstate_highest_perf_se= t() into amd_get_boost_ratio_numerator()") Signed-off-by: Mario Limonciello --- Documentation/admin-guide/pm/amd-pstate.rst | 4 +--- drivers/cpufreq/amd-pstate.c | 25 ++++++++++++--------- 2 files changed, 16 insertions(+), 13 deletions(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/ad= min-guide/pm/amd-pstate.rst index 210a808b74ec2..412423c54f258 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -251,9 +251,7 @@ performance supported in `AMD CPPC Performance Capabili= ty `_). In some ASICs, the highest CPPC performance is not the one in the ``_CPC`` table, so we need to expose it to sysfs. If boost is not active, but still supported, this maximum frequency will be larger than the one in -``cpuinfo``. On systems that support preferred core, the driver will have -different values for some cores than others and this will reflect the valu= es -advertised by the platform at bootup. +``cpuinfo``. This attribute is read-only. =20 ``amd_pstate_lowest_nonlinear_freq`` diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 66fb7aee95d24..c51026fe636a9 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -397,15 +397,19 @@ static inline int amd_pstate_cppc_enable(bool enable) =20 static int msr_init_perf(struct amd_cpudata *cpudata) { - u64 cap1; + u64 cap1, numerator; =20 int ret =3D rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &cap1); if (ret) return ret; =20 - WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); - WRITE_ONCE(cpudata->max_limit_perf, AMD_CPPC_HIGHEST_PERF(cap1)); + ret =3D amd_get_boost_ratio_numerator(cpudata->cpu, &numerator); + if (ret) + return ret; + + WRITE_ONCE(cpudata->highest_perf, numerator); + WRITE_ONCE(cpudata->max_limit_perf, numerator); WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1)); @@ -417,13 +421,18 @@ static int msr_init_perf(struct amd_cpudata *cpudata) static int shmem_init_perf(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; + u64 numerator; =20 int ret =3D cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; =20 - WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf); - WRITE_ONCE(cpudata->max_limit_perf, cppc_perf.highest_perf); + ret =3D amd_get_boost_ratio_numerator(cpudata->cpu, &numerator); + if (ret) + return ret; + + WRITE_ONCE(cpudata->highest_perf, numerator); + WRITE_ONCE(cpudata->max_limit_perf, numerator); WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); WRITE_ONCE(cpudata->lowest_nonlinear_perf, cppc_perf.lowest_nonlinear_perf); @@ -912,7 +921,6 @@ static int amd_pstate_init_freq(struct amd_cpudata *cpu= data) { int ret; u32 min_freq, max_freq; - u64 numerator; u32 nominal_perf, nominal_freq; u32 lowest_nonlinear_perf, lowest_nonlinear_freq; u32 boost_ratio, lowest_nonlinear_ratio; @@ -934,10 +942,7 @@ static int amd_pstate_init_freq(struct amd_cpudata *cp= udata) =20 nominal_perf =3D READ_ONCE(cpudata->nominal_perf); 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This however is not necessary when the highest perf value is the boost numerator. Suggested-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy Fixes: 18d9b5227121 ("cpufreq/amd-pstate: Use nominal perf for limits when = boost is disabled") Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index c51026fe636a9..5e0edb65de32a 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -593,16 +593,13 @@ static int amd_pstate_verify(struct cpufreq_policy_da= ta *policy_data) =20 static int amd_pstate_update_min_max_limit(struct cpufreq_policy *policy) { - u32 max_limit_perf, min_limit_perf, lowest_perf, max_perf; + u32 max_limit_perf, min_limit_perf, lowest_perf, max_perf, max_freq; struct amd_cpudata *cpudata =3D policy->driver_data; =20 - if (cpudata->boost_supported && !policy->boost_enabled) - max_perf =3D READ_ONCE(cpudata->nominal_perf); - else - max_perf =3D READ_ONCE(cpudata->highest_perf); - - max_limit_perf =3D div_u64(policy->max * max_perf, policy->cpuinfo.max_fr= eq); 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The 'amd_pstate_epp_perf' trace event shows the values being written for all CPUs. Reviewed-by: Perry Yuan Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- v2: * Fix boost in some calls --- drivers/cpufreq/amd-pstate-trace.h | 45 ++++++++++++++++++++++++++++++ drivers/cpufreq/amd-pstate.c | 28 +++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/drivers/cpufreq/amd-pstate-trace.h b/drivers/cpufreq/amd-pstat= e-trace.h index 35f38ae67fb13..e2221a4b6901c 100644 --- a/drivers/cpufreq/amd-pstate-trace.h +++ b/drivers/cpufreq/amd-pstate-trace.h @@ -88,6 +88,51 @@ TRACE_EVENT(amd_pstate_perf, ) ); =20 +TRACE_EVENT(amd_pstate_epp_perf, + + TP_PROTO(unsigned int cpu_id, + unsigned int highest_perf, + unsigned int epp, + unsigned int min_perf, + unsigned int max_perf, + bool boost + ), + + TP_ARGS(cpu_id, + highest_perf, + epp, + min_perf, + max_perf, + boost), + + TP_STRUCT__entry( + __field(unsigned int, cpu_id) + __field(unsigned int, highest_perf) + __field(unsigned int, epp) + __field(unsigned int, min_perf) + __field(unsigned int, max_perf) + __field(bool, boost) + ), + + TP_fast_assign( + __entry->cpu_id =3D cpu_id; + __entry->highest_perf =3D highest_perf; + __entry->epp =3D epp; + __entry->min_perf =3D min_perf; + __entry->max_perf =3D max_perf; + __entry->boost =3D boost; + ), + + TP_printk("cpu%u: [%u<->%u]/%u, epp=3D%u, boost=3D%u", + (unsigned int)__entry->cpu_id, + (unsigned int)__entry->min_perf, + (unsigned int)__entry->max_perf, + (unsigned int)__entry->highest_perf, + (unsigned int)__entry->epp, + (bool)__entry->boost + ) +); + #endif /* _AMD_PSTATE_TRACE_H */ =20 /* This part must be outside protection */ diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 5e0edb65de32a..a59c897dd59c7 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -324,6 +324,14 @@ static int amd_pstate_set_energy_pref_index(struct amd= _cpudata *cpudata, return -EBUSY; } =20 + if (trace_amd_pstate_epp_perf_enabled()) { + trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, + epp, + AMD_CPPC_MIN_PERF(cpudata->cppc_req_cached), + AMD_CPPC_MAX_PERF(cpudata->cppc_req_cached), + cpudata->boost_state); + } + ret =3D amd_pstate_set_epp(cpudata, epp); =20 return ret; @@ -1598,6 +1606,13 @@ static int amd_pstate_epp_update_limit(struct cpufre= q_policy *policy) =20 WRITE_ONCE(cpudata->cppc_req_cached, value); =20 + if (trace_amd_pstate_epp_perf_enabled()) { + trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, epp, + cpudata->min_limit_perf, + cpudata->max_limit_perf, + policy->boost_enabled); + } + amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U, cpudata->max_limit_perf, false); =20 @@ -1641,6 +1656,13 @@ static void amd_pstate_epp_reenable(struct amd_cpuda= ta *cpudata) =20 max_perf =3D READ_ONCE(cpudata->highest_perf); =20 + if (trace_amd_pstate_epp_perf_enabled()) { + trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, + cpudata->epp_cached, + AMD_CPPC_MIN_PERF(cpudata->cppc_req_cached), + max_perf, cpudata->boost_state); + } + amd_pstate_update_perf(cpudata, 0, 0, max_perf, false); amd_pstate_set_epp(cpudata, cpudata->epp_cached); } @@ -1669,6 +1691,12 @@ static int amd_pstate_epp_cpu_offline(struct cpufreq= _policy *policy) =20 mutex_lock(&amd_pstate_limits_lock); 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Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 32 ++++++++++++-------------------- 1 file changed, 12 insertions(+), 20 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index a59c897dd59c7..6a96d3a24c77e 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -758,12 +758,12 @@ static int amd_pstate_set_boost(struct cpufreq_policy= *policy, int state) pr_err("Boost mode is not supported by this processor or SBIOS\n"); return -EOPNOTSUPP; } - mutex_lock(&amd_pstate_driver_lock); + guard(mutex)(&amd_pstate_driver_lock); + ret =3D amd_pstate_cpu_boost_update(policy, state); WRITE_ONCE(cpudata->boost_state, !ret ? state : false); policy->boost_enabled =3D !ret ? state : false; refresh_frequency_limits(policy); - mutex_unlock(&amd_pstate_driver_lock); =20 return ret; } @@ -854,7 +854,8 @@ static void amd_pstate_update_limits(unsigned int cpu) if (!amd_pstate_prefcore) return; =20 - mutex_lock(&amd_pstate_driver_lock); + guard(mutex)(&amd_pstate_driver_lock); + ret =3D amd_get_highest_perf(cpu, &cur_high); if (ret) goto free_cpufreq_put; @@ -874,7 +875,6 @@ static void amd_pstate_update_limits(unsigned int cpu) if (!highest_perf_changed) cpufreq_update_policy(cpu); =20 - mutex_unlock(&amd_pstate_driver_lock); } =20 /* @@ -1203,11 +1203,11 @@ static ssize_t store_energy_performance_preference( if (ret < 0) return -EINVAL; =20 - mutex_lock(&amd_pstate_limits_lock); + guard(mutex)(&amd_pstate_limits_lock); + ret =3D amd_pstate_set_energy_pref_index(cpudata, ret); - mutex_unlock(&amd_pstate_limits_lock); =20 - return ret ?: count; + return ret ? ret : count; } =20 static ssize_t show_energy_performance_preference( @@ -1371,13 +1371,10 @@ EXPORT_SYMBOL_GPL(amd_pstate_update_status); static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { - ssize_t ret; =20 - mutex_lock(&amd_pstate_driver_lock); - ret =3D amd_pstate_show_status(buf); - mutex_unlock(&amd_pstate_driver_lock); + guard(mutex)(&amd_pstate_driver_lock); =20 - return ret; + return amd_pstate_show_status(buf); } =20 static ssize_t status_store(struct device *a, struct device_attribute *b, @@ -1386,9 +1383,8 @@ static ssize_t status_store(struct device *a, struct = device_attribute *b, char *p =3D memchr(buf, '\n', count); int ret; =20 - mutex_lock(&amd_pstate_driver_lock); + guard(mutex)(&amd_pstate_driver_lock); ret =3D amd_pstate_update_status(buf, p ? p - buf : count); - mutex_unlock(&amd_pstate_driver_lock); =20 return ret < 0 ? ret : count; } @@ -1689,7 +1685,7 @@ static int amd_pstate_epp_cpu_offline(struct cpufreq_= policy *policy) =20 min_perf =3D READ_ONCE(cpudata->lowest_perf); =20 - mutex_lock(&amd_pstate_limits_lock); + guard(mutex)(&amd_pstate_limits_lock); =20 if (trace_amd_pstate_epp_perf_enabled()) { trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, @@ -1700,8 +1696,6 @@ static int amd_pstate_epp_cpu_offline(struct cpufreq_= policy *policy) amd_pstate_update_perf(cpudata, min_perf, 0, min_perf, false); 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Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 3 --- drivers/cpufreq/amd-pstate.h | 2 -- 2 files changed, 5 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6a96d3a24c77e..dd25e7e615984 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1478,7 +1478,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_pol= icy *policy) return -ENOMEM; =20 cpudata->cpu =3D policy->cpu; - cpudata->epp_policy =3D 0; =20 ret =3D amd_pstate_init_perf(cpudata); if (ret) @@ -1585,8 +1584,6 @@ static int amd_pstate_epp_update_limit(struct cpufreq= _policy *policy) value &=3D ~AMD_CPPC_DES_PERF(~0L); value |=3D AMD_CPPC_DES_PERF(0); =20 - cpudata->epp_policy =3D cpudata->policy; - /* Get BIOS pre-defined epp value */ epp =3D amd_pstate_get_epp(cpudata, value); if (epp < 0) { diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h index cd573bc6b6db8..7765c82f975c6 100644 --- a/drivers/cpufreq/amd-pstate.h +++ b/drivers/cpufreq/amd-pstate.h @@ -57,7 +57,6 @@ struct amd_aperf_mperf { * @hw_prefcore: check whether HW supports preferred core featue. * Only when hw_prefcore and early prefcore param are true, * AMD P-State driver supports preferred core featue. - * @epp_policy: Last saved policy used to set energy-performance preference * @epp_cached: Cached CPPC energy-performance preference value * @policy: Cpufreq policy value * @cppc_cap1_cached Cached MSR_AMD_CPPC_CAP1 register value @@ -94,7 +93,6 @@ struct amd_cpudata { bool hw_prefcore; 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Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- v2: * Add a missing case to traces * Use AMD_CPPC instead of AMD_PSTATE --- drivers/cpufreq/amd-pstate.c | 51 ++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index dd25e7e615984..0ed04316a8d80 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -22,6 +22,7 @@ =20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 +#include #include #include #include @@ -88,6 +89,11 @@ static bool cppc_enabled; static bool amd_pstate_prefcore =3D true; static struct quirk_entry *quirks; =20 +#define AMD_CPPC_MAX_PERF_MASK GENMASK(7, 0) +#define AMD_CPPC_MIN_PERF_MASK GENMASK(15, 8) +#define AMD_CPPC_DES_PERF_MASK GENMASK(23, 16) +#define AMD_CPPC_EPP_PERF_MASK GENMASK(31, 24) + /* * AMD Energy Preference Performance (EPP) * The EPP is used in the CCLK DPM controller to drive @@ -182,7 +188,6 @@ static DEFINE_MUTEX(amd_pstate_driver_lock); =20 static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) { - u64 epp; int ret; =20 if (!cppc_req_cached) { @@ -192,9 +197,8 @@ static s16 msr_get_epp(struct amd_cpudata *cpudata, u64= cppc_req_cached) return ret; } } - epp =3D (cppc_req_cached >> 24) & 0xFF; =20 - return (s16)epp; + return FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cppc_req_cached); } =20 DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp); @@ -269,12 +273,11 @@ static inline void amd_pstate_update_perf(struct amd_= cpudata *cpudata, =20 static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) { - int ret; - u64 value =3D READ_ONCE(cpudata->cppc_req_cached); + int ret; =20 - value &=3D ~GENMASK_ULL(31, 24); - value |=3D (u64)epp << 24; + value &=3D ~AMD_CPPC_EPP_PERF_MASK; + value |=3D FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); WRITE_ONCE(cpudata->cppc_req_cached, value); =20 ret =3D wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); @@ -327,8 +330,8 @@ static int amd_pstate_set_energy_pref_index(struct amd_= cpudata *cpudata, if (trace_amd_pstate_epp_perf_enabled()) { trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, epp, - AMD_CPPC_MIN_PERF(cpudata->cppc_req_cached), - AMD_CPPC_MAX_PERF(cpudata->cppc_req_cached), + FIELD_GET(AMD_CPPC_MIN_PERF_MASK, cpudata->cppc_req_cached), + FIELD_GET(AMD_CPPC_MAX_PERF_MASK, cpudata->cppc_req_cached), cpudata->boost_state); } =20 @@ -542,18 +545,15 @@ static void amd_pstate_update(struct amd_cpudata *cpu= data, u32 min_perf, des_perf =3D 0; } =20 - value &=3D ~AMD_CPPC_MIN_PERF(~0L); - value |=3D AMD_CPPC_MIN_PERF(min_perf); - - value &=3D ~AMD_CPPC_DES_PERF(~0L); - value |=3D AMD_CPPC_DES_PERF(des_perf); - /* limit the max perf when core performance boost feature is disabled */ if (!cpudata->boost_supported) max_perf =3D min_t(unsigned long, nominal_perf, max_perf); =20 - value &=3D ~AMD_CPPC_MAX_PERF(~0L); - value |=3D AMD_CPPC_MAX_PERF(max_perf); + value &=3D ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | + AMD_CPPC_DES_PERF_MASK); + value |=3D FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); + value |=3D FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf); + value |=3D FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); =20 if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) { trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq, @@ -1573,16 +1573,11 @@ static int amd_pstate_epp_update_limit(struct cpufr= eq_policy *policy) if (cpudata->policy =3D=3D CPUFREQ_POLICY_PERFORMANCE) min_perf =3D min(cpudata->nominal_perf, max_perf); =20 - /* Initial min/max values for CPPC Performance Controls Register */ - value &=3D ~AMD_CPPC_MIN_PERF(~0L); - value |=3D AMD_CPPC_MIN_PERF(min_perf); - - value &=3D ~AMD_CPPC_MAX_PERF(~0L); - value |=3D AMD_CPPC_MAX_PERF(max_perf); - - /* CPPC EPP feature require to set zero to the desire perf bit */ - value &=3D ~AMD_CPPC_DES_PERF(~0L); - value |=3D AMD_CPPC_DES_PERF(0); + value &=3D ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | + AMD_CPPC_DES_PERF_MASK); + value |=3D FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); + value |=3D FIELD_PREP(AMD_CPPC_DES_PERF_MASK, 0); + value |=3D FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); =20 /* Get BIOS pre-defined epp value */ epp =3D amd_pstate_get_epp(cpudata, value); @@ -1652,7 +1647,7 @@ static void amd_pstate_epp_reenable(struct amd_cpudat= a *cpudata) if (trace_amd_pstate_epp_perf_enabled()) { trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, cpudata->epp_cached, - AMD_CPPC_MIN_PERF(cpudata->cppc_req_cached), + FIELD_GET(AMD_CPPC_MIN_PERF_MASK, cpudata->cppc_req_cached), max_perf, cpudata->boost_state); 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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH v3 07/15] cpufreq/amd-pstate: Only update the cached value in msr_set_epp() on success Date: Mon, 9 Dec 2024 12:52:40 -0600 Message-ID: <20241209185248.16301-8-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241209185248.16301-1-mario.limonciello@amd.com> References: <20241209185248.16301-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A348:EE_|IA1PR12MB8465:EE_ X-MS-Office365-Filtering-Correlation-Id: 827873a5-6d8f-46ed-8059-08dd1882bcc0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?dVG0vewoa1qE1UznaH9cq5mjy5MrWPb2S8jpWaKe+QFApfDk/DHvB/xZzjtV?= =?us-ascii?Q?EZN203nTLBuLK+cCNmUhAEOpVfOVanuk73XpAQ+I4xQOwmZ4aPYGsldoXZ4q?= =?us-ascii?Q?TLQ+CAszMrZX6/LWGtrkhzmAygQ+DMMi62xA7sSR+YO115ZuqYfmopgPagc2?= =?us-ascii?Q?utXhqlU2JJ14JlqAUAaeLQjtHZFptBzQSODRWTvg1RjA4rOGc1Ojcns0+Iuz?= =?us-ascii?Q?veKDZQaIMzvgWIKiwFZL0RljUDQ3xJanKxXZL+5qMH6pdetFqwI6Fm3GnWmK?= =?us-ascii?Q?ISc4DJdCeSh4zlg3cTksk8HeMi3VEyU3Hwq5KzKJi9G73zStHqQ8dsvKFsEo?= =?us-ascii?Q?jx/YlV03QAsee8pZgR938KEEcNHfHrVl/irXJlY7ANlHmwM2P7A3NSFWE9WU?= =?us-ascii?Q?HYHgiXWsdqLmYf1Bq8sig4ZUJIrVQL3cF4LIAW9RJSrWAET2MajJb2CULfOK?= =?us-ascii?Q?JlM5fsONdMTPhsbBDVIa/Z41u7gu1JHioAU5+0A0iEGelu4GBO1/jbv6rzcV?= =?us-ascii?Q?viuAKUk6DwyExj7URmukLFitnmpp8y1gprV/x+FnFZDOUk9G1msx92SkZUZB?= =?us-ascii?Q?oC7N2eSOswrBBJ5233u/5n1wStGayR+fsIQHMas56CufQeSzd9atvy6xN+Ia?= =?us-ascii?Q?IWD0XcMlwFj2EddAIORA/GhJ8oKpng4keCbdjq7O6+ReSAviwRjRFib77usN?= =?us-ascii?Q?v9K0H8Qi7vKYpkEc2LfxDjK4L4/sNdK6L+Np9dhP5eK8epHn/FObrbcbrO9b?= =?us-ascii?Q?iX+Kuq3cwW9Vo3V8jcKHVxdTd4KmcBzn5CWMJnxgOhSA4XMbF6a9tJuTfxwx?= =?us-ascii?Q?s7KY1bUyWG4TfRAHcl86RMjvQGy+RWR07Xv8DS5YheRMcyLSEmOoevUdAMnu?= =?us-ascii?Q?B0sUzDsJ4NkQ++vS1N5UErPk7JWZNa9Ja0BT3I+gUNbvI57yYDW6htv/nzJL?= =?us-ascii?Q?6QTTur8GiN9kqraO+43SNhQ9CHbAbPm/pwI8YwEPztUWWhWQDG+A9WldMVwd?= =?us-ascii?Q?VXUrPysQcorDbL1XBOIq58eFQ7FqhsFRV/IiN9w1Re8sIiHbEMH3E0HvGNKy?= =?us-ascii?Q?z8SIZUGv5BkZRH1SXTsSZ0UqCvYDH4xsch5dxGYzsskNnZn4EZKYBRbG3o3O?= =?us-ascii?Q?twC6LrnXwEKN2IPFR79ACPuSxitkXKemdOPps/ihzrZIjrQsOR7eA+wirrk7?= =?us-ascii?Q?MHCUdFXSmK0cR08waI76lvA8586gTD40ViXBZEDYN9ipaVvR181Ea0jSkbxq?= =?us-ascii?Q?NK/FM9BKjrHeXZiTZgHH0NK6oWAYc/EdciVryxuheDrQC0UlJaB4qUQEjBxv?= =?us-ascii?Q?YWjGVMoKmyHriav9bofFiaWgn/xTa4J1OUm8ATMxe2MrzEx1QNWrR36Kwij2?= =?us-ascii?Q?bcqDXdkmeYGsus/uMRGj+YeUI2mcDyjJphW4GVii9mYIlGj1BrrIUr/mGsdz?= =?us-ascii?Q?dBe1xjXQOFiuBw64MsmZpg4TEgnl/iSj?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2024 18:53:14.7244 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 827873a5-6d8f-46ed-8059-08dd1882bcc0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A348.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8465 Content-Type: text/plain; charset="utf-8" If writing the MSR MSR_AMD_CPPC_REQ fails then the cached value in the amd_cpudata structure should not be updated. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 0ed04316a8d80..263acce2f4b0c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -278,11 +278,15 @@ static int msr_set_epp(struct amd_cpudata *cpudata, u= 32 epp) =20 value &=3D ~AMD_CPPC_EPP_PERF_MASK; value |=3D FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); - WRITE_ONCE(cpudata->cppc_req_cached, value); =20 ret =3D wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); - if (!ret) - cpudata->epp_cached =3D epp; + if (ret) { + pr_err("failed to set energy perf value (%d)\n", ret); + return ret; + } + + cpudata->epp_cached =3D epp; + WRITE_ONCE(cpudata->cppc_req_cached, value); =20 return ret; } --=20 2.43.0 From nobody Fri Dec 27 11:52:00 2024 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2045.outbound.protection.outlook.com [40.107.212.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B5AD1990BD; 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Mon, 9 Dec 2024 12:53:12 -0600 From: Mario Limonciello To: "Gautham R . Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH v3 08/15] cpufreq/amd-pstate: store all values in cpudata struct in khz Date: Mon, 9 Dec 2024 12:52:41 -0600 Message-ID: <20241209185248.16301-9-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241209185248.16301-1-mario.limonciello@amd.com> References: <20241209185248.16301-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A34B:EE_|IA1PR12MB7589:EE_ X-MS-Office365-Filtering-Correlation-Id: 71f1a9c7-290c-438a-1c50-08dd1882bcd9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?1UQzNHFCQS6osRtvTeg/kbCXFhUPfrfyI6ehqqJaXYPj0FzIB23mC9A56BEx?= =?us-ascii?Q?XBa8VyAnLj9JCaUv03oNqx4iPCTDZDyF9Z14FnEfMxtKpjdKN3LZyrQIIIxo?= =?us-ascii?Q?56pDe07DuZ+QHK21LA/FP8PAk6f5csryx9Vv62aUmByiwmT3ZYT51xiDzY81?= =?us-ascii?Q?3Gj09EY2HAehF2yLsNiypkDh6STmPK77wPXRB8mnIQWt/sXCQBnTNc9/t5YL?= =?us-ascii?Q?+HuqK88M/WslDYbDG1o4hqM8dGmPeD11N1SY28Bm2oNX/ZNet0BV2fm0XmDp?= =?us-ascii?Q?GZqQ/Ug4dcvqPrPNkGpCGXxH4gHnQ3O4NoMn3QxO7jrZLLpxiEl/ks5q6mxz?= =?us-ascii?Q?Jf7yvtDBxk+V7faBHb1Y20WWGO+aryCh4loE3/pNbYmvCNJdNVhBblnh7cXj?= =?us-ascii?Q?LgVp1q/Lp3fGc7wPMkAecPiB7gn2dzwvuPj6c7dwvExwAYVJ/fo4oTbNlMfJ?= =?us-ascii?Q?XtWnJozIo2tA0GKcxw9aJLo+Yfr/yXFxm1iVbix78x2JhQfmgyNCSKTEa3mK?= =?us-ascii?Q?j/HbMAHeeeas4mMU8xYMdnrFICWlawm24qhaK4c4mjeOhX6I01fvVDicu4ox?= =?us-ascii?Q?3VH37TJxt2LwJ/QMW3aCX0nyNSST9GeaCartE2PR2DbcrFAnvLKfTCxZRJkr?= =?us-ascii?Q?hLrRKNhm+dutfUNU0TdKq1/IZo48FR6OWdtPjpMJYf5ORaJeaY9Tj3qzrgX3?= =?us-ascii?Q?Ho3XMqDpXiljmv8lDzn+HCE7mr77yDOs33sHAdaIlVEFx8m1Et2u3iSV71GT?= =?us-ascii?Q?yLGjC/TMaLXHk7e8i4jrrS7jjTD+Hyk2KaT5jdGjnn87q5mMg6qpWd8AwVNI?= =?us-ascii?Q?oF8Ft2hxRyru1c74nKhqoV7tnlfQT30jebRhDtF1/CaizUZKX5NOcWxGRhJ2?= =?us-ascii?Q?s/3oo2Xv7BwUMWxmeB4z5rgwC+KeQjKmAZUndVi0LDIrbZheU9rYF+s/gYXV?= =?us-ascii?Q?k84A3E6C1BjIssY12xVhyW/sBS/Q90RSAY6mRzRskQfzy8O5fcs7dp0GeXR9?= =?us-ascii?Q?dw7q9HTfy/drWAHmWQ0PM9l6yf+wvttf025cebK6RLHGBkTjn4hVbg7WMGJ6?= =?us-ascii?Q?2/51sM9A0Y6CtXwqBGlzJLtq56cX099Smlq2PG6CSUmtqrtoKPFc0C7Pha8i?= =?us-ascii?Q?xAbRR0rUu6RzxqbcZZrRRwT+EotRm0o4yNv+ng1VAEY3YlktbIM9f1PAVDG6?= =?us-ascii?Q?exN8x1Mli7tF9ybzLK7HUgRZtOoC6TTp5bOW+jsAGeeEpciQNEDtpw4xx7yL?= =?us-ascii?Q?2GZAkdx3rKsJSJ8bzp7xfqzpVyHUsNkvPKKQEOw+EO9YD9rrPpmrY5WwD4Po?= =?us-ascii?Q?3f9bbSDWNfrnAoG0sdIGm/0iN5cvrFgdVeaPMqZX0J5NdE7D/XHRc7tz+ly8?= =?us-ascii?Q?+iYAg27BITuAJu2dDkLQd/aOtx4IYllkvrm7/DsJGV7uWph1uajHWkhuh4S3?= =?us-ascii?Q?HDFL32tWre9G9rcK+YQWooVQAX88jJ7z?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2024 18:53:14.8701 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71f1a9c7-290c-438a-1c50-08dd1882bcd9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7589 Content-Type: text/plain; charset="utf-8" Storing values in the cpudata structure in different units leads to confusion and hardcoded conversions elsewhere. After ratios are calculated store everything in khz for any future use. Adjust all relevant consumers for this change as well. Suggested-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- v2: * Adjust checks to use nominal_freq for consistency --- drivers/cpufreq/amd-pstate-ut.c | 12 +++++------- drivers/cpufreq/amd-pstate.c | 28 ++++++++++++++-------------- 2 files changed, 19 insertions(+), 21 deletions(-) diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-u= t.c index a261d7300951e..3a0a380c3590c 100644 --- a/drivers/cpufreq/amd-pstate-ut.c +++ b/drivers/cpufreq/amd-pstate-ut.c @@ -207,7 +207,6 @@ static void amd_pstate_ut_check_freq(u32 index) int cpu =3D 0; struct cpufreq_policy *policy =3D NULL; struct amd_cpudata *cpudata =3D NULL; - u32 nominal_freq_khz; =20 for_each_possible_cpu(cpu) { policy =3D cpufreq_cpu_get(cpu); @@ -215,14 +214,13 @@ static void amd_pstate_ut_check_freq(u32 index) break; cpudata =3D policy->driver_data; =20 - nominal_freq_khz =3D cpudata->nominal_freq*1000; - if (!((cpudata->max_freq >=3D nominal_freq_khz) && - (nominal_freq_khz > cpudata->lowest_nonlinear_freq) && + if (!((cpudata->max_freq >=3D cpudata->nominal_freq) && + (cpudata->nominal_freq > cpudata->lowest_nonlinear_freq) && (cpudata->lowest_nonlinear_freq > cpudata->min_freq) && (cpudata->min_freq > 0))) { amd_pstate_ut_cases[index].result =3D AMD_PSTATE_UT_RESULT_FAIL; pr_err("%s cpu%d max=3D%d >=3D nominal=3D%d > lowest_nonlinear=3D%d > m= in=3D%d > 0, the formula is incorrect!\n", - __func__, cpu, cpudata->max_freq, nominal_freq_khz, + __func__, cpu, cpudata->max_freq, cpudata->nominal_freq, cpudata->lowest_nonlinear_freq, cpudata->min_freq); goto skip_test; } @@ -236,13 +234,13 @@ static void amd_pstate_ut_check_freq(u32 index) =20 if (cpudata->boost_supported) { if ((policy->max =3D=3D cpudata->max_freq) || - (policy->max =3D=3D nominal_freq_khz)) + (policy->max =3D=3D cpudata->nominal_freq)) amd_pstate_ut_cases[index].result =3D AMD_PSTATE_UT_RESULT_PASS; else { amd_pstate_ut_cases[index].result =3D AMD_PSTATE_UT_RESULT_FAIL; pr_err("%s cpu%d policy_max=3D%d should be equal cpu_max=3D%d or cpu_n= ominal=3D%d !\n", __func__, cpu, policy->max, cpudata->max_freq, - nominal_freq_khz); + cpudata->nominal_freq); goto skip_test; } } else { diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 263acce2f4b0c..8a173359c2754 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -739,8 +739,8 @@ static int amd_pstate_cpu_boost_update(struct cpufreq_p= olicy *policy, bool on) =20 if (on) policy->cpuinfo.max_freq =3D max_freq; - else if (policy->cpuinfo.max_freq > nominal_freq * 1000) - policy->cpuinfo.max_freq =3D nominal_freq * 1000; + else if (policy->cpuinfo.max_freq > nominal_freq) + policy->cpuinfo.max_freq =3D nominal_freq; =20 policy->max =3D policy->cpuinfo.max_freq; =20 @@ -940,29 +940,29 @@ static int amd_pstate_init_freq(struct amd_cpudata *c= pudata) return ret; =20 if (quirks && quirks->lowest_freq) - min_freq =3D quirks->lowest_freq * 1000; + min_freq =3D quirks->lowest_freq; else - min_freq =3D cppc_perf.lowest_freq * 1000; + min_freq =3D cppc_perf.lowest_freq; =20 if (quirks && quirks->nominal_freq) - nominal_freq =3D quirks->nominal_freq ; + nominal_freq =3D quirks->nominal_freq; else nominal_freq =3D cppc_perf.nominal_freq; =20 nominal_perf =3D READ_ONCE(cpudata->nominal_perf); =20 boost_ratio =3D div_u64(cpudata->highest_perf << SCHED_CAPACITY_SHIFT, no= minal_perf); - max_freq =3D (nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT) * 1000; + max_freq =3D (nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT); =20 lowest_nonlinear_perf =3D READ_ONCE(cpudata->lowest_nonlinear_perf); lowest_nonlinear_ratio =3D div_u64(lowest_nonlinear_perf << SCHED_CAPACIT= Y_SHIFT, nominal_perf); - lowest_nonlinear_freq =3D (nominal_freq * lowest_nonlinear_ratio >> SCHED= _CAPACITY_SHIFT) * 1000; + lowest_nonlinear_freq =3D (nominal_freq * lowest_nonlinear_ratio >> SCHED= _CAPACITY_SHIFT); =20 - WRITE_ONCE(cpudata->min_freq, min_freq); - WRITE_ONCE(cpudata->lowest_nonlinear_freq, lowest_nonlinear_freq); - WRITE_ONCE(cpudata->nominal_freq, nominal_freq); - WRITE_ONCE(cpudata->max_freq, max_freq); + WRITE_ONCE(cpudata->min_freq, min_freq * 1000); + WRITE_ONCE(cpudata->lowest_nonlinear_freq, lowest_nonlinear_freq * 1000); + WRITE_ONCE(cpudata->nominal_freq, nominal_freq * 1000); + WRITE_ONCE(cpudata->max_freq, max_freq * 1000); =20 /** * Below values need to be initialized correctly, otherwise driver will f= ail to load @@ -972,13 +972,13 @@ static int amd_pstate_init_freq(struct amd_cpudata *c= pudata) */ if (min_freq <=3D 0 || max_freq <=3D 0 || nominal_freq <=3D 0 || min_freq= > max_freq) { pr_err("min_freq(%d) or max_freq(%d) or nominal_freq(%d) value is incorr= ect\n", - min_freq, max_freq, nominal_freq * 1000); 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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH v3 09/15] cpufreq/amd-pstate: Change amd_pstate_update_perf() to return an int Date: Mon, 9 Dec 2024 12:52:42 -0600 Message-ID: <20241209185248.16301-10-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241209185248.16301-1-mario.limonciello@amd.com> References: <20241209185248.16301-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A348:EE_|PH7PR12MB6834:EE_ X-MS-Office365-Filtering-Correlation-Id: 44178ff0-4bf6-4461-3fa7-08dd1882bd41 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ZoINt0oj0V324SUScG2jKFU05BfROoHBYwtMx4K9aibW2q/aZApVCxuu38tV?= =?us-ascii?Q?rpOQwXwg5x0GY3f+FjIUp/mmsGk8u5gY5DoingiQ4jYQOQLgZWGIjDlcEzeD?= =?us-ascii?Q?g05/8YIiN2ByQslLetjBFWfOlejSvB6n4NRgYkQY0fIArO4+wk09SyNRgriW?= =?us-ascii?Q?wPoqDx5UkatqGEgGRawf7MsaE7HbijY6g3LttIAC/jp/dh5tEbrqE86fytrg?= =?us-ascii?Q?ymrTBjd0J9rgpEQ9jqEfAz6JAL+5n97RRt4TeVD205JN5/uPHQoH80aXpo8x?= =?us-ascii?Q?+eJpS4/GPywCpS2gZ9QnYbrsdKHfE9WBcRozz92h3yM6lEwcME8BcSViDw16?= =?us-ascii?Q?I8F0MtPTuPDm3Nm4NRqUgB8RgX41xNUv9jiRuyk1QMDZQsVpas2HAbR5ot5j?= =?us-ascii?Q?BASOXRy0GZMPt9nd7iSAr9vb8XBTUXsldONM8zvFhnzG7I3eF40iFhMznss0?= =?us-ascii?Q?+ceKeRrTnz4Suk+jgjDq4EXdt3RfOT3xIS45Q9GMXh1w4okH52mdplm4H1YS?= =?us-ascii?Q?p3S6KXl2mb6MQoHUs4xwMP9vhEUxtRmQnBrqptsJy1M8vBfDhFv+Od4EEUEu?= =?us-ascii?Q?LBVEO4H6bon8NBTjViGyDMbdX67ImyKd+A1WvGxU53l08jTW5BGqFG6b+F+3?= =?us-ascii?Q?eQWywTGqg/Dz4wO3jhQBCxBjdO0iAx2j/w/xjVma2LkB/C29GW5JJwOXNoHZ?= =?us-ascii?Q?VfeUSLARKcr8Y3xVPchdzSi/JbIxyEkW2CA6RVo8kWYGUlQzCeKAeBaXKfnG?= =?us-ascii?Q?g1CpB1I3MeKFFdxsikgF0vyQ4L4r1ol2fPOzZ80acB226oOOfQymL0rTp//Y?= =?us-ascii?Q?E8iUMIZxLI7HzqVxcHDZyewZ4ozwiesh1ylTbImO4tsAi5DwR/xgVlANoHhL?= =?us-ascii?Q?wunvo/8yiVlRE7DnP6OE0GMVGvR+7GPdCFqVuqJRZFuiROcU8j8mgTndAKkU?= =?us-ascii?Q?zGaRtVnjecyn1wJcMl8KffIedPhnGb9RDFVTUR8OiEfAwRBbr5WOrB60tMEN?= =?us-ascii?Q?rsQABIyhbw1GnGJLm3EYTCn4nxNmaTlIktBTo+Iczkiv/Xmnmm/gikFNhzip?= =?us-ascii?Q?k6WDNZJ9wodAuBtpHwUQbwAFv7lZGw4btNhfqL4LaSL1ARorY4hW3X4dD7BK?= =?us-ascii?Q?Pt699o5YeWVv2MSQU3ggfEOPPO92fSEZ78+AbIN5XOv3/k2QTkasf3RubBkD?= =?us-ascii?Q?lI4IInLHJt0bxATYbvwWgk/kc/DbaKGn7aqdqn/9H9nFf+HbvXf/ixOhDzhF?= =?us-ascii?Q?dtPP04p77NBbdqt8SlVwlk4SiHprGTChNTOAHvJA2sbOvgKSal4PREYZip9U?= =?us-ascii?Q?kh5tHYRbzyt9WJ0T0phwmRYUb8UzgRfmu+XfdNEf8YBR0clwBrXvSFDNZADu?= =?us-ascii?Q?OP6fd4fjhxrI/JGmGNlFSi67nOJtYXeGOQegWwDA6RDaGVUwGInFQVFSYfEN?= =?us-ascii?Q?bB4UNiJuZIvTexh/JesIFx/A+rcKSkSn?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2024 18:53:15.5525 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 44178ff0-4bf6-4461-3fa7-08dd1882bd41 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A348.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6834 Content-Type: text/plain; charset="utf-8" As msr_update_perf() calls an MSR it's possible that it fails. Pass this return code up to the caller. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 8a173359c2754..3a3df67c096d5 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -251,24 +251,26 @@ static int amd_pstate_get_energy_pref_index(struct am= d_cpudata *cpudata) return index; } =20 -static void msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf, +static int msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch) { - if (fast_switch) + if (fast_switch) { wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached)); - else - wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, - READ_ONCE(cpudata->cppc_req_cached)); + return 0; + } + + return wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, + READ_ONCE(cpudata->cppc_req_cached)); } =20 DEFINE_STATIC_CALL(amd_pstate_update_perf, msr_update_perf); =20 -static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata, +static inline int amd_pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch) { - static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf, - max_perf, fast_switch); + return static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf, + max_perf, fast_switch); } =20 static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) @@ -480,7 +482,7 @@ static inline int amd_pstate_init_perf(struct amd_cpuda= ta *cpudata) return static_call(amd_pstate_init_perf)(cpudata); } =20 -static void shmem_update_perf(struct amd_cpudata *cpudata, +static int shmem_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch) { @@ -490,7 +492,7 @@ static void shmem_update_perf(struct amd_cpudata *cpuda= ta, perf_ctrls.min_perf =3D min_perf; perf_ctrls.desired_perf =3D des_perf; =20 - cppc_set_perf(cpudata->cpu, &perf_ctrls); + return cppc_set_perf(cpudata->cpu, &perf_ctrls); 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Move it to amd_pstate_update_min_max_limit() so other callers can benefit as well. With this move it's not necessary to have clamp_t calls anymore because the verify callback is called when setting limits. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- v2: * Drop lowest_perf variable --- drivers/cpufreq/amd-pstate.c | 28 +++++----------------------- 1 file changed, 5 insertions(+), 23 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 3a3df67c096d5..dc3c45b6f5103 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -537,10 +537,6 @@ static void amd_pstate_update(struct amd_cpudata *cpud= ata, u32 min_perf, u32 nominal_perf =3D READ_ONCE(cpudata->nominal_perf); u64 value =3D prev; =20 - min_perf =3D clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, - cpudata->max_limit_perf); - max_perf =3D clamp_t(unsigned long, max_perf, cpudata->min_limit_perf, - cpudata->max_limit_perf); des_perf =3D clamp_t(unsigned long, des_perf, min_perf, max_perf); =20 max_freq =3D READ_ONCE(cpudata->max_limit_freq); @@ -607,7 +603,7 @@ static int amd_pstate_verify(struct cpufreq_policy_data= *policy_data) =20 static int amd_pstate_update_min_max_limit(struct cpufreq_policy *policy) { - u32 max_limit_perf, min_limit_perf, lowest_perf, max_perf, max_freq; + u32 max_limit_perf, min_limit_perf, max_perf, max_freq; struct amd_cpudata *cpudata =3D policy->driver_data; =20 max_perf =3D READ_ONCE(cpudata->highest_perf); @@ -615,12 +611,8 @@ static int amd_pstate_update_min_max_limit(struct cpuf= req_policy *policy) max_limit_perf =3D div_u64(policy->max * max_perf, max_freq); min_limit_perf =3D div_u64(policy->min * max_perf, max_freq); =20 - lowest_perf =3D READ_ONCE(cpudata->lowest_perf); - if (min_limit_perf < lowest_perf) - min_limit_perf =3D lowest_perf; - - if (max_limit_perf < min_limit_perf) - max_limit_perf =3D min_limit_perf; + if (cpudata->policy =3D=3D CPUFREQ_POLICY_PERFORMANCE) + min_limit_perf =3D min(cpudata->nominal_perf, max_limit_perf); =20 WRITE_ONCE(cpudata->max_limit_perf, max_limit_perf); WRITE_ONCE(cpudata->min_limit_perf, min_limit_perf); @@ -1562,28 +1554,18 @@ static void amd_pstate_epp_cpu_exit(struct cpufreq_= policy *policy) static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata =3D policy->driver_data; - u32 max_perf, min_perf; u64 value; s16 epp; =20 - max_perf =3D READ_ONCE(cpudata->highest_perf); - min_perf =3D READ_ONCE(cpudata->lowest_perf); amd_pstate_update_min_max_limit(policy); =20 - max_perf =3D clamp_t(unsigned long, max_perf, cpudata->min_limit_perf, - cpudata->max_limit_perf); - min_perf =3D clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, - cpudata->max_limit_perf); value =3D READ_ONCE(cpudata->cppc_req_cached); =20 - if (cpudata->policy =3D=3D CPUFREQ_POLICY_PERFORMANCE) - min_perf =3D min(cpudata->nominal_perf, max_perf); - value &=3D ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | AMD_CPPC_DES_PERF_MASK); - value |=3D FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); + value |=3D FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, cpudata->max_limit_perf); value |=3D FIELD_PREP(AMD_CPPC_DES_PERF_MASK, 0); - value |=3D FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); + value |=3D FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, cpudata->min_limit_perf); =20 /* Get BIOS pre-defined epp value */ epp =3D amd_pstate_get_epp(cpudata, value); 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As all callers use cached value merge amd_pstate_get_energy_pref_index() into show_energy_performance_preference(). Check if the EPP value is changed before writing it to MSR or shared memory region. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- v2: * Drop extra mutex --- drivers/cpufreq/amd-pstate.c | 105 ++++++++++++++--------------------- 1 file changed, 43 insertions(+), 62 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index dc3c45b6f5103..d21acd961edcd 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -186,29 +186,28 @@ static inline int get_mode_idx_from_str(const char *s= tr, size_t size) static DEFINE_MUTEX(amd_pstate_limits_lock); static DEFINE_MUTEX(amd_pstate_driver_lock); =20 -static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) +static s16 msr_get_epp(struct amd_cpudata *cpudata) { + u64 value; int ret; =20 - if (!cppc_req_cached) { - ret =3D rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req_cached); - if (ret < 0) { - pr_debug("Could not retrieve energy perf value (%d)\n", ret); - return ret; - } + ret =3D rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); + if (ret < 0) { + pr_debug("Could not retrieve energy perf value (%d)\n", ret); + return ret; } =20 - return FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cppc_req_cached); + return FIELD_GET(AMD_CPPC_EPP_PERF_MASK, value); } =20 DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp); =20 -static inline s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc= _req_cached) +static inline s16 amd_pstate_get_epp(struct amd_cpudata *cpudata) { - return static_call(amd_pstate_get_epp)(cpudata, cppc_req_cached); + return static_call(amd_pstate_get_epp)(cpudata); } =20 -static s16 shmem_get_epp(struct amd_cpudata *cpudata, u64 dummy) +static s16 shmem_get_epp(struct amd_cpudata *cpudata) { u64 epp; int ret; @@ -222,35 +221,6 @@ static s16 shmem_get_epp(struct amd_cpudata *cpudata, = u64 dummy) return (s16)(epp & 0xff); } =20 -static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata) -{ - s16 epp; - int index =3D -EINVAL; - - epp =3D amd_pstate_get_epp(cpudata, 0); - if (epp < 0) - return epp; - - switch (epp) { - case AMD_CPPC_EPP_PERFORMANCE: - index =3D EPP_INDEX_PERFORMANCE; - break; - case AMD_CPPC_EPP_BALANCE_PERFORMANCE: - index =3D EPP_INDEX_BALANCE_PERFORMANCE; - break; - case AMD_CPPC_EPP_BALANCE_POWERSAVE: - index =3D EPP_INDEX_BALANCE_POWERSAVE; - break; - case AMD_CPPC_EPP_POWERSAVE: - index =3D EPP_INDEX_POWERSAVE; - break; - default: - break; - } - - return index; -} - static int msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch) { @@ -275,19 +245,23 @@ static inline int amd_pstate_update_perf(struct amd_c= pudata *cpudata, =20 static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) { - u64 value =3D READ_ONCE(cpudata->cppc_req_cached); + u64 value, prev; int ret; =20 + value =3D prev =3D READ_ONCE(cpudata->cppc_req_cached); value &=3D ~AMD_CPPC_EPP_PERF_MASK; value |=3D FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); =20 + if (value =3D=3D prev) + return 0; + ret =3D wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); if (ret) { pr_err("failed to set energy perf value (%d)\n", ret); return ret; } =20 - cpudata->epp_cached =3D epp; + WRITE_ONCE(cpudata->epp_cached, epp); WRITE_ONCE(cpudata->cppc_req_cached, value); =20 return ret; @@ -305,13 +279,16 @@ static int shmem_set_epp(struct amd_cpudata *cpudata,= u32 epp) int ret; struct cppc_perf_ctrls perf_ctrls; =20 + if (epp =3D=3D cpudata->epp_cached) + return 0; + perf_ctrls.energy_perf =3D epp; ret =3D cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); if (ret) { pr_debug("failed to set energy perf value (%d)\n", ret); return ret; } - cpudata->epp_cached =3D epp; + WRITE_ONCE(cpudata->epp_cached, epp); =20 return ret; } @@ -1214,9 +1191,22 @@ static ssize_t show_energy_performance_preference( struct amd_cpudata *cpudata =3D policy->driver_data; int preference; =20 - preference =3D amd_pstate_get_energy_pref_index(cpudata); - if (preference < 0) - return preference; + switch (cpudata->epp_cached) { + case AMD_CPPC_EPP_PERFORMANCE: + preference =3D EPP_INDEX_PERFORMANCE; + break; + case AMD_CPPC_EPP_BALANCE_PERFORMANCE: + preference =3D EPP_INDEX_BALANCE_PERFORMANCE; + break; + case AMD_CPPC_EPP_BALANCE_POWERSAVE: + preference =3D EPP_INDEX_BALANCE_POWERSAVE; + break; + case AMD_CPPC_EPP_POWERSAVE: + preference =3D EPP_INDEX_POWERSAVE; + break; + default: + return -EINVAL; + } =20 return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); } @@ -1501,7 +1491,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_pol= icy *policy) =20 policy->driver_data =3D cpudata; =20 - cpudata->epp_cached =3D cpudata->epp_default =3D amd_pstate_get_epp(cpuda= ta, 0); + cpudata->epp_cached =3D cpudata->epp_default =3D amd_pstate_get_epp(cpuda= ta); =20 policy->min =3D policy->cpuinfo.min_freq; policy->max =3D policy->cpuinfo.max_freq; @@ -1555,35 +1545,26 @@ static int amd_pstate_epp_update_limit(struct cpufr= eq_policy *policy) { struct amd_cpudata *cpudata =3D policy->driver_data; u64 value; - s16 epp; =20 amd_pstate_update_min_max_limit(policy); =20 value =3D READ_ONCE(cpudata->cppc_req_cached); =20 value &=3D ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | - AMD_CPPC_DES_PERF_MASK); + AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK); value |=3D FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, cpudata->max_limit_perf); value |=3D FIELD_PREP(AMD_CPPC_DES_PERF_MASK, 0); value |=3D FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, cpudata->min_limit_perf); =20 - /* Get BIOS pre-defined epp value */ - epp =3D amd_pstate_get_epp(cpudata, value); - if (epp < 0) { - /** - * This return value can only be negative for shared_memory - * systems where EPP register read/write not supported. - */ - return epp; - } - if (cpudata->policy =3D=3D CPUFREQ_POLICY_PERFORMANCE) - epp =3D 0; + WRITE_ONCE(cpudata->epp_cached, 0); + value |=3D FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, cpudata->epp_cached); =20 WRITE_ONCE(cpudata->cppc_req_cached, value); =20 if (trace_amd_pstate_epp_perf_enabled()) { - trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, epp, + trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, + cpudata->epp_cached, cpudata->min_limit_perf, cpudata->max_limit_perf, policy->boost_enabled); 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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH v3 12/15] cpufreq/amd-pstate: Always write EPP value when updating perf Date: Mon, 9 Dec 2024 12:52:45 -0600 Message-ID: <20241209185248.16301-13-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241209185248.16301-1-mario.limonciello@amd.com> References: <20241209185248.16301-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A348:EE_|DS0PR12MB7897:EE_ X-MS-Office365-Filtering-Correlation-Id: 4fc00e30-29dd-408e-143b-08dd1882bd97 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?mwsoRYbldHTNg0Vc9ru+r9zX6yxM34GSADILwPsdBH0peW7YGZP8zyZg9gqU?= =?us-ascii?Q?3Ca8UqHNPE8K800mSULd5wpMWPfedsWKnv8zR3Y0PSz5VsEc8LZ2pRWFIUz6?= =?us-ascii?Q?z+rGYWaSGuiD2r6BNOyl/7Q4PKRxh2kto7LGIUGGC/YprCJpCE6mA5zukdV3?= =?us-ascii?Q?cSUJ7t5BeoU4engsM2frTLbbmy486su1ufn0hGLArBJlT2qtArfIUQ+zOeUx?= =?us-ascii?Q?Pv/xIRXRZ9RHom/pDu+3Gi4hRfqV62gM+rRk5QSIDktPq3ZQuJ+hYbl0Nx+t?= =?us-ascii?Q?N2pO1EDlpEEZx3Rmz3aH+sulS2QCKkfrUMzNSKFgIAz4mclxXlj0OTm7HS3s?= =?us-ascii?Q?2yXSJNzoRdLzjie/BIw2C0hJBzBXYukNHcO3Q/lUVEOOLUufeOYc48tCGTRM?= =?us-ascii?Q?DyRYLTRLL3eqdtfmcnCaXtCFzg0gW1MeUfummcX7FnFfrrrZDyafMdGepszD?= =?us-ascii?Q?Q7La0gTTNNH3sFTBkvuyN8FQYliIHwkyiBErL0xj3F7F7A/UWt1urPoeTj06?= =?us-ascii?Q?chbEAEPD/pDl3A8kJ8plCRzh4foV97bY+yFTnF7ZvuOi/FqGJO+wX2hFWXTD?= =?us-ascii?Q?03GAd17bFHi0anjV6Z18ChthlN8CBemDXs7naL3qURnSGXFZryY0BW1b8v4s?= =?us-ascii?Q?YlpTVu2zvN2KQkhrcDh9qKWO3QIZ3/AgGo+MA3mpCpll8V4rlYLAHh+VYxzw?= =?us-ascii?Q?crsaGqqECasy+/4dITJSDYt/9uMbwtIfGNvkTZetvpwkLF4Iu3V04VEaLc8K?= =?us-ascii?Q?YXce1TI5E6jvFtiVkt+vlspmPIGXZnahwTijO0dfOviS/8bi/8W7edq8xLZP?= =?us-ascii?Q?JKjt9DjS5WN4paKHVeXap2uOqbecaC+2RuXdEXxMfdwxe/rLaqa36Lp7UsDE?= =?us-ascii?Q?1tN32JzVFbVWUw82A1578sKrficsJ1N81YtzrOYQrH1o6C11Hw7JxFh7jIHp?= =?us-ascii?Q?BDLdq2Ll9TxH3kGpP521qRnQJk8MAHt6eU5xH2pCHlNkM80rV2Ev2LEsSelQ?= =?us-ascii?Q?M2ZvwSyR/hwpMa8EHE6JjuuKoJMHU/vbSc2w2iFSF64BKhCeo/miZwh43eh0?= =?us-ascii?Q?sQiM3auzB1TF6fasqp43kzLZOln3W25xxhI27jInaXQ3YF+fQ9w4GNqWqF0K?= =?us-ascii?Q?tRL8b+0BLBfTtYRoVzJnhq+3SVFAgrQBxmJb4DvLb3vNYLkUl+HeS9UdwaU2?= =?us-ascii?Q?2FIc9Y5x2mWMNL2LnvVwOrNZkb7mSSjmq0iFzg9flppTmhcrF0/Bbeoq78hV?= =?us-ascii?Q?z5lhKTHclze6FGL2PKHWKIM7iGsmNQtB1rYdH0gHvjdKdVCMiZ73Qdfqmcd+?= =?us-ascii?Q?M223fIcPzXMP5NXK6vz0zxh+3zQJV2B5TpzF/IN4DNEn+a1HZRCvlyZRF3Y2?= =?us-ascii?Q?K29/uby4r/N5rpXhKyw45yTiT3t8EVRrLWENcSkhJLsumQd0PqY2B61NX0Wz?= =?us-ascii?Q?gdzBscndzfjUsJs2yuV4LYEP2GWL+Iis?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2024 18:53:16.1151 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4fc00e30-29dd-408e-143b-08dd1882bd97 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A348.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7897 Content-Type: text/plain; charset="utf-8" For MSR systems the EPP value is in the same register as perf targets and so divding them into two separate MSR writes is wasteful. In msr_update_perf(), update both EPP and perf values in one write to MSR_AMD_CPPC_REQ, and cache them if successful. To accomplish this plumb the EPP value into the update_perf call and modify all its callers to check the return value. As this unifies calls, ensure that the MSR write is necessary before flushing a write out. Also drop the comparison from the passive flow tracing. Signed-off-by: Mario Limonciello --- v3: * Squash "Always write EPP value when updating perf" and "Check if CPPC request has changed before writing to the MSR or shared m= emory" * Remove extra write to cached value * Add comment explaining why updating two cached variables --- drivers/cpufreq/amd-pstate-trace.h | 7 +- drivers/cpufreq/amd-pstate.c | 108 +++++++++++++++-------------- 2 files changed, 56 insertions(+), 59 deletions(-) diff --git a/drivers/cpufreq/amd-pstate-trace.h b/drivers/cpufreq/amd-pstat= e-trace.h index e2221a4b6901c..8d692415d9050 100644 --- a/drivers/cpufreq/amd-pstate-trace.h +++ b/drivers/cpufreq/amd-pstate-trace.h @@ -32,7 +32,6 @@ TRACE_EVENT(amd_pstate_perf, u64 aperf, u64 tsc, unsigned int cpu_id, - bool changed, bool fast_switch ), =20 @@ -44,7 +43,6 @@ TRACE_EVENT(amd_pstate_perf, aperf, tsc, cpu_id, - changed, fast_switch ), =20 @@ -57,7 +55,6 @@ TRACE_EVENT(amd_pstate_perf, __field(unsigned long long, aperf) __field(unsigned long long, tsc) __field(unsigned int, cpu_id) - __field(bool, changed) __field(bool, fast_switch) ), =20 @@ -70,11 +67,10 @@ TRACE_EVENT(amd_pstate_perf, __entry->aperf =3D aperf; __entry->tsc =3D tsc; __entry->cpu_id =3D cpu_id; - __entry->changed =3D changed; __entry->fast_switch =3D fast_switch; ), =20 - TP_printk("amd_min_perf=3D%lu amd_des_perf=3D%lu amd_max_perf=3D%lu freq= =3D%llu mperf=3D%llu aperf=3D%llu tsc=3D%llu cpu_id=3D%u changed=3D%s fast_= switch=3D%s", + TP_printk("amd_min_perf=3D%lu amd_des_perf=3D%lu amd_max_perf=3D%lu freq= =3D%llu mperf=3D%llu aperf=3D%llu tsc=3D%llu cpu_id=3D%u fast_switch=3D%s", (unsigned long)__entry->min_perf, (unsigned long)__entry->target_perf, (unsigned long)__entry->capacity, @@ -83,7 +79,6 @@ TRACE_EVENT(amd_pstate_perf, (unsigned long long)__entry->aperf, (unsigned long long)__entry->tsc, (unsigned int)__entry->cpu_id, - (__entry->changed) ? "true" : "false", (__entry->fast_switch) ? "true" : "false" ) ); diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index d21acd961edcd..fc0eb268c0335 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -222,25 +222,47 @@ static s16 shmem_get_epp(struct amd_cpudata *cpudata) } =20 static int msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf, - u32 des_perf, u32 max_perf, bool fast_switch) + u32 des_perf, u32 max_perf, u32 epp, bool fast_switch) { + u64 value, prev; + + value =3D prev =3D READ_ONCE(cpudata->cppc_req_cached); + + value &=3D ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | + AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK); + value |=3D FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); + value |=3D FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf); + value |=3D FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); + value |=3D FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); + + if (value =3D=3D prev) + return 0; + if (fast_switch) { - wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached)); + wrmsrl(MSR_AMD_CPPC_REQ, value); return 0; + } else { + int ret =3D wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + + if (ret) + return ret; } =20 - return wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, - READ_ONCE(cpudata->cppc_req_cached)); + WRITE_ONCE(cpudata->cppc_req_cached, value); + WRITE_ONCE(cpudata->epp_cached, epp); + + return 0; } =20 DEFINE_STATIC_CALL(amd_pstate_update_perf, msr_update_perf); =20 static inline int amd_pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, - u32 max_perf, bool fast_switch) + u32 max_perf, u32 epp, + bool fast_switch) { return static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf, - max_perf, fast_switch); + max_perf, epp, fast_switch); } =20 static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) @@ -261,6 +283,7 @@ static int msr_set_epp(struct amd_cpudata *cpudata, u32= epp) return ret; } =20 + /* update both so that msr_update_perf() can effectively check */ WRITE_ONCE(cpudata->epp_cached, epp); WRITE_ONCE(cpudata->cppc_req_cached, value); =20 @@ -459,12 +482,18 @@ static inline int amd_pstate_init_perf(struct amd_cpu= data *cpudata) return static_call(amd_pstate_init_perf)(cpudata); } =20 -static int shmem_update_perf(struct amd_cpudata *cpudata, - u32 min_perf, u32 des_perf, - u32 max_perf, bool fast_switch) +static int shmem_update_perf(struct amd_cpudata *cpudata, u32 min_perf, + u32 des_perf, u32 max_perf, u32 epp, bool fast_switch) { struct cppc_perf_ctrls perf_ctrls; =20 + if (cppc_state =3D=3D AMD_PSTATE_ACTIVE) { + int ret =3D shmem_set_epp(cpudata, epp); + + if (ret) + return ret; + } + perf_ctrls.max_perf =3D max_perf; perf_ctrls.min_perf =3D min_perf; perf_ctrls.desired_perf =3D des_perf; @@ -510,9 +539,7 @@ static void amd_pstate_update(struct amd_cpudata *cpuda= ta, u32 min_perf, { unsigned long max_freq; struct cpufreq_policy *policy =3D cpufreq_cpu_get(cpudata->cpu); - u64 prev =3D READ_ONCE(cpudata->cppc_req_cached); u32 nominal_perf =3D READ_ONCE(cpudata->nominal_perf); - u64 value =3D prev; =20 des_perf =3D clamp_t(unsigned long, des_perf, min_perf, max_perf); =20 @@ -528,27 +555,14 @@ static void amd_pstate_update(struct amd_cpudata *cpu= data, u32 min_perf, if (!cpudata->boost_supported) max_perf =3D min_t(unsigned long, nominal_perf, max_perf); =20 - value &=3D ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | - AMD_CPPC_DES_PERF_MASK); - value |=3D FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); - value |=3D FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf); - value |=3D FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); - if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) { trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq, cpudata->cur.mperf, cpudata->cur.aperf, cpudata->cur.tsc, - cpudata->cpu, (value !=3D prev), fast_switch); + cpudata->cpu, fast_switch); } =20 - if (value =3D=3D prev) - goto cpufreq_policy_put; + amd_pstate_update_perf(cpudata, min_perf, des_perf, max_perf, 0, fast_swi= tch); =20 - WRITE_ONCE(cpudata->cppc_req_cached, value); - - amd_pstate_update_perf(cpudata, min_perf, des_perf, - max_perf, fast_switch); - -cpufreq_policy_put: cpufreq_cpu_put(policy); } =20 @@ -1544,36 +1558,24 @@ static void amd_pstate_epp_cpu_exit(struct cpufreq_= policy *policy) static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata =3D policy->driver_data; - u64 value; + u32 epp; =20 amd_pstate_update_min_max_limit(policy); =20 - value =3D READ_ONCE(cpudata->cppc_req_cached); - - value &=3D ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | - AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK); - value |=3D FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, cpudata->max_limit_perf); - value |=3D FIELD_PREP(AMD_CPPC_DES_PERF_MASK, 0); - value |=3D FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, cpudata->min_limit_perf); - if (cpudata->policy =3D=3D CPUFREQ_POLICY_PERFORMANCE) - WRITE_ONCE(cpudata->epp_cached, 0); - value |=3D FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, cpudata->epp_cached); - - WRITE_ONCE(cpudata->cppc_req_cached, value); + epp =3D 0; + else + epp =3D READ_ONCE(cpudata->epp_cached); =20 if (trace_amd_pstate_epp_perf_enabled()) { - trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, - cpudata->epp_cached, + trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, epp, cpudata->min_limit_perf, cpudata->max_limit_perf, policy->boost_enabled); } =20 - amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U, - cpudata->max_limit_perf, false); - - return amd_pstate_set_epp(cpudata, READ_ONCE(cpudata->epp_cached)); + return amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U, + cpudata->max_limit_perf, epp, false); } =20 static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) @@ -1602,7 +1604,7 @@ static int amd_pstate_epp_set_policy(struct cpufreq_p= olicy *policy) return 0; } =20 -static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) +static int amd_pstate_epp_reenable(struct amd_cpudata *cpudata) { u64 max_perf; int ret; @@ -1620,17 +1622,19 @@ static void amd_pstate_epp_reenable(struct amd_cpud= ata *cpudata) max_perf, cpudata->boost_state); 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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello , Dhananjay Ugwekar Subject: [PATCH v3 13/15] cpufreq/amd-pstate: Drop ret variable from amd_pstate_set_energy_pref_index() Date: Mon, 9 Dec 2024 12:52:46 -0600 Message-ID: <20241209185248.16301-14-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241209185248.16301-1-mario.limonciello@amd.com> References: <20241209185248.16301-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A34B:EE_|LV8PR12MB9154:EE_ X-MS-Office365-Filtering-Correlation-Id: 38b1901e-c56d-489b-4c54-08dd1882bdcc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?LmndC4mS7RcH9hE60Ov9gQad1jJG56WYdOJUJbEMks2T5VpiphgpsCG5ZztT?= =?us-ascii?Q?hJ1Eau450NjYohbOmbSLzWMn8TEqpK/8ER5Y1AlzWvcxVCeVbZ4cHeinao+I?= =?us-ascii?Q?gOwKtTZFUOFzC5dM2A2QmJoJpETSluJ5wCEBLoNrrTE36kjpKSCVuJKQyVsp?= =?us-ascii?Q?xS/wCP3YYLNxfoviSRck1QYQqD3sOMfGMRW+mTFBapF8rN25u+WlkJb6HRF0?= =?us-ascii?Q?Jv+p1ExOE7vNuyFmWYmoQM2FRpI25DO07u9Nl9OPYF5wLARpTTeK7FIb94Jr?= =?us-ascii?Q?7amZhquaqwZcYQyoiHnM/T/qFscg630c2cjuCpKJByYX9bpoi9NVsgA3HKwI?= =?us-ascii?Q?Nqxqd9wFwXq9Bt/4+4YOq1B9cS91EJk+GOb2clN5dVIJH32UAbJdsIg0N5tE?= =?us-ascii?Q?ywQax+guLfFpqoZG0ri+XLrqE0KW80rTN2GKEhLLEhRkBKmo8Gpr9zOvL2ap?= =?us-ascii?Q?eAH6WtCPdXpN1W6O4Y3dpmLZyCrQv2PhluRgU/+OxSvd5pcA98613E2N8vJG?= =?us-ascii?Q?xwzHtvxITz8n6EF3Dx7056N5e4tqrNtxnPpMa0bkrXvWA1M0nhS5WEcYnmkO?= =?us-ascii?Q?myuneSKrJI92pu5u9C5Hg6FyaRkLTx+mwQEtT8+szi1UP1FGukCzUeqsSsOe?= =?us-ascii?Q?5+F3HBWoyRam07se3Hb38FTFnGEYd1CKsQkWSdfoetPwdr/VmigeMWi69wbh?= =?us-ascii?Q?SwPjyGY2Msa21sO9d3D7ULJjOWclMDV+E5DGQQTxqk2u7LAFKEEg41Ue3rsQ?= =?us-ascii?Q?+tZuR0zWYKAXx3c0fm0My/ZiFOZohuLnRjmT9NgWRoqzEfg89cyGeIoGutq6?= =?us-ascii?Q?jzTcMumhzgJSSXhJXESM2j8NRyoofP23Y4y7nQk9Tp56vi+YUUeS7eBFvHhO?= =?us-ascii?Q?nhcS3mI7T0YeqAJhqVsiOOSVFosi/1njOvhifWfluTNzXZN8FCIWPO6urDSA?= =?us-ascii?Q?q+VJaou9slFSQvJnl7p/2Z8kMS8ctjt3Jb0zTC9goB/klUVhaYaVvrA/MDAk?= =?us-ascii?Q?pQUdur1f1ybnq1bIoEw72XG5V4Fulo2h14v6duvflYajeUneRPoimFML0ck9?= =?us-ascii?Q?bamB3UCJFEspWXdJPWAG5Q4dwU2YIFA3yiPEFvUBHWojfcIwVIJUxPzguave?= =?us-ascii?Q?lDoZbYqZ4uLpT1sNErv6vQpAModP0B/FZvEimXtZjKfMBy7mvOZy22t6onRi?= =?us-ascii?Q?BQOlM7Pksqhqp8L0BhiSf3Sw8K60LlxSL44R08yKk+XY/KZ0dUWT5pSIjamE?= =?us-ascii?Q?r8Lj6xfPoM/9LIivyvf34Lh8wRtL16AJ5R9rBLAC2sLFvh+Sim5MHfNS6WJO?= =?us-ascii?Q?q6Bh5uzq56Ql7LiiVctFgiKB/1JKnwefWSpO9LFJSQxz1muNAA16RUjiRPp0?= =?us-ascii?Q?Tfz9EwEeuFY75lZHGHcbiF8Q3hWwc5jW4BmfefPDSmj2x3KOv7fLGyTtCt80?= =?us-ascii?Q?1olnTBPth/zM6SGvifErNtUC4a8fjnIk?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2024 18:53:16.4794 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 38b1901e-c56d-489b-4c54-08dd1882bdcc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9154 Content-Type: text/plain; charset="utf-8" The ret variable is not necessary. Reviewed-and-tested-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index fc0eb268c0335..ead3a47570139 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -319,13 +319,11 @@ static int shmem_set_epp(struct amd_cpudata *cpudata,= u32 epp) static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata, int pref_index) { - int epp =3D -EINVAL; - int ret; + int epp; =20 if (!pref_index) epp =3D cpudata->epp_default; - - if (epp =3D=3D -EINVAL) + else epp =3D epp_values[pref_index]; =20 if (epp > 0 && cpudata->policy =3D=3D CPUFREQ_POLICY_PERFORMANCE) { @@ -341,9 +339,7 @@ static int amd_pstate_set_energy_pref_index(struct amd_= cpudata *cpudata, cpudata->boost_state); } =20 - ret =3D amd_pstate_set_epp(cpudata, epp); - - return ret; + return amd_pstate_set_epp(cpudata, epp); } =20 static inline int msr_cppc_enable(bool enable) --=20 2.43.0 From nobody Fri Dec 27 11:52:00 2024 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2044.outbound.protection.outlook.com [40.107.220.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A51D9198A37; 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Mon, 9 Dec 2024 12:53:15 -0600 From: Mario Limonciello To: "Gautham R . Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello , "Artem S . Tashkinov" , Dhananjay Ugwekar Subject: [PATCH v3 14/15] cpufreq/amd-pstate: Set different default EPP policy for Epyc and Ryzen Date: Mon, 9 Dec 2024 12:52:47 -0600 Message-ID: <20241209185248.16301-15-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241209185248.16301-1-mario.limonciello@amd.com> References: <20241209185248.16301-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A348:EE_|SA1PR12MB7319:EE_ X-MS-Office365-Filtering-Correlation-Id: db0cc331-1415-4167-4b3d-08dd1882bdef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?pTJ2nVNIek+AAJwQG75SKVAPYR8XzADQ6+jskPm9exw5LW3npzng0D6W9TDN?= =?us-ascii?Q?FNIST2g8JQtjHpNOKSP86Okx4H5zIbbyjEUoMcE1QgQcUdAyTn8qjypfL+GS?= =?us-ascii?Q?xY28YB6jzjfZw+ES8S0ZTW3CiOBWtXDdiPAsKNphroScNdQAiHfKdFZFtGeq?= =?us-ascii?Q?wwnU/sCL92btxZx3BPmSvJPH3vtCXPqw7GUveLJ7SMsPBb40gnfDA6FBExhX?= =?us-ascii?Q?A60QEgS4w0jSh2ym8gZRX9dNj/xCdT+RtIdVtiQvL09/WlKntcIxFrXwCC5y?= =?us-ascii?Q?Uy0pKHX0Ozhyl/qumXejfIh86IM2RYMlVH6siwY7m6hpOM7KKGGRLDorkTIN?= =?us-ascii?Q?GvarropPVZXS02DsawbNzMMwfv451wxqlY1v8jkIVsQTBPLk9vzfSV5jssIn?= =?us-ascii?Q?1duBzy7wHcMpN7LOCo9NPSIXB9qwW2TZrWvCNEVCrXTSRYyM9afnUzT0lSEP?= =?us-ascii?Q?8/9CCrTzolwphIPPWmuh/K0H+EJVbv8JD/C2sjof9B7XVnt6/wotY0jq/1SK?= =?us-ascii?Q?XTQfSRWC422djIhsvw5TruEObDqlKvFJ3IyHJ5H9Jrd7LN3RJDyanmBxA8q8?= =?us-ascii?Q?yC4FS+O+JZNw6IeTR24RpDgM1SZQBbk8BzaZKSeLqyj/v1H73iw8pf3cz01d?= =?us-ascii?Q?EnCm/Y4Lfw5yCPIPVMG/rsNRumoXkx/zQIr6ZnUb5aGCTHSxWMAD8FdIaILw?= =?us-ascii?Q?NGbmRpckZAqEXCHh0zpzg0Tu1wj3JC/ku6VaLHx1Lgt85fwBjXaoP2P/kTe1?= =?us-ascii?Q?g/e1d1fLfqINdqArjP93SjulPSuqpFEFk5RuPVBIFB7Y52tJARz0fKIShkkv?= =?us-ascii?Q?1Kwiuak7HgmeCmmRCq8Usjc9Pqg8krNg1nYCvGwRCrr2RudPA0rxRcAkKE9t?= =?us-ascii?Q?qfWVEr/7wsk9GG9rWQNMBcimGtSXGKjNC/Hh5JCj8xu6srywUQcmKFV2+soh?= =?us-ascii?Q?bRovCdfwRK/TY5Tdz1aEdM4zdfwG76A2tl3wZp3YnD4EOmNpyvTKHu2DnlJ3?= =?us-ascii?Q?ZmGKgNOTV+GLNZQsjWDvaTJ1QVwx+oIg8NEeSfa1yyiMJ4PVMBzivEOmzYe1?= =?us-ascii?Q?GOUjtAczrV0CFNhVpuPrlKNtuJtkR+MzMVKbNw7YcWfspJ5JeEVPb40k1PtC?= =?us-ascii?Q?34wV2F48c5f6xy+bMeoGFIMwm3moy9mLgrqOjom+gDNcE2fLNGpSUhcZ6zow?= =?us-ascii?Q?3f7FyrIdOaHdoOi0yGWJ76/u+6OXOvAuQ14CsEBCYf3WWxttFE7R7tcjDCHj?= =?us-ascii?Q?jJPHbhZ40vV0Ox5XJKPFwePXPf8WKdcEX6Czad9ztOu/wb9m93xDU2UEoZDW?= =?us-ascii?Q?g9tZHZrVIZiDnFOtr196dyCPTZXFNZFT/qxHYJ9s6Cei0u2E9yPDJVRdsH9s?= =?us-ascii?Q?IUL+NKnT9jQAlWuVTorToUZaNU2BpH6HLUmQIG7e6mvIQpeXjlEdH1QXLEH+?= =?us-ascii?Q?K8DxeQ+a5RGxkAWQO0lx4zE3IH1FxEFI?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2024 18:53:16.6932 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db0cc331-1415-4167-4b3d-08dd1882bdef X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A348.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7319 Content-Type: text/plain; charset="utf-8" For Ryzen systems the EPP policy set by the BIOS is generally configured to performance as this is the default register value for the CPPC request MSR. If a user doesn't use additional software to configure EPP then the system will default biased towards performance and consume extra battery. Instead configure the default to "balanced_performance" for this case. Suggested-by: Artem S. Tashkinov Reviewed-by: Dhananjay Ugwekar Tested-by: Dhananjay Ugwekar Closes: https://bugzilla.kernel.org/show_bug.cgi?id=3D219526 Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index ead3a47570139..308d30a25f100 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1501,8 +1501,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_pol= icy *policy) =20 policy->driver_data =3D cpudata; =20 - cpudata->epp_cached =3D cpudata->epp_default =3D amd_pstate_get_epp(cpuda= ta); - policy->min =3D policy->cpuinfo.min_freq; policy->max =3D policy->cpuinfo.max_freq; =20 @@ -1513,10 +1511,13 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_p= olicy *policy) * the default cpufreq governor is neither powersave nor performance. */ if (amd_pstate_acpi_pm_profile_server() || - amd_pstate_acpi_pm_profile_undefined()) + amd_pstate_acpi_pm_profile_undefined()) { policy->policy =3D CPUFREQ_POLICY_PERFORMANCE; - else + cpudata->epp_default =3D amd_pstate_get_epp(cpudata); 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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH v3 15/15] cpufreq/amd-pstate: Drop boost_state variable Date: Mon, 9 Dec 2024 12:52:48 -0600 Message-ID: <20241209185248.16301-16-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241209185248.16301-1-mario.limonciello@amd.com> References: <20241209185248.16301-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A34B:EE_|LV3PR12MB9409:EE_ X-MS-Office365-Filtering-Correlation-Id: 14474434-b823-42cc-4962-08dd1882be0a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?eNmLjhPcD9nORovnbObWcTdExX5E92VZ4JEZQ9GOVFrqo7J2B4lq5QwwlWUm?= =?us-ascii?Q?LoazpDqeA2Dv5wwYvYB3wYCooRoTUJQZsxrf8iM+tkloNeMaduwMObu0hk2d?= =?us-ascii?Q?OZrkrVZzhDw72sAZLOk0eueF8spdJvFab+TiWZsIvrX32wVDP7iM/QKtSKdm?= =?us-ascii?Q?n0Zbe6KzGHw5xDPDIhvF43q/XpOcsQkXQ1nNZ7HEZe+cij70h0umHtNiDVNK?= =?us-ascii?Q?hJ734CI5udx88MFZYrvCrPuqZ+pr7vHQsEUI4vrDyzYIBsENxYKtoNwcn4UV?= =?us-ascii?Q?EMp5PQuNwhSjmEYGbHI75B1O6kjLQaX/V4r+LvX9kE6cZSVB5LblE7/WsXIW?= =?us-ascii?Q?4JaAQERkPHqOMAjKdtn3SKE9qDhH1uaYSVHlcIHmzod4u6JbzFGuQVviEBGK?= =?us-ascii?Q?T/73qOor9ba1cQPE6f7+avl9vYZL4yb9OA4Rb0WNajC/qxM0vaDCBQPln6d8?= =?us-ascii?Q?WRXuB6sz4zWSEMQBsQ8NVN/2slVPI7FCpYHm1MvPblg4E/do+edHZV8Zw68O?= =?us-ascii?Q?O/Xc866yaRU7shd7a1lkN/6YWhX51GK2GLXEtJad+MvvDKsvd3L7B58Gk7xp?= =?us-ascii?Q?vn4g0Iw4egaGGTcLUxGhKe+rfjpeKY6CDAkKXbFT5H/QHcB0bCOZEg072Fvj?= =?us-ascii?Q?4i6Igioy3CQKTTcDwqwnyJwwXk+NfTjynQLeXOQjFHDhzUig0C3ZSBlLTjVj?= =?us-ascii?Q?th54eCzW7tK+jSp7EB6nwtpG8vBvWF8tsLqhKTAJ6GxUxzvbtryBFAj4KzBP?= =?us-ascii?Q?oMzqJ1TsTxuumDQeyp0p/KS/VYSaVDIt1XBIaAliBU7vpMON02qkX2Nvx/pb?= =?us-ascii?Q?9b7RHWklfVy161xKsySax44eimw6WPbj8Si2NigkR92TCv7wEIYyXSUZbBra?= =?us-ascii?Q?yvAUW3jXLQrLfTEVgTjXXctCfgXTDxYAWR/ZoxU9iK/ruGVQwAQMDywdDrLm?= =?us-ascii?Q?6hH99Y0VpqascIQ1A4/91IZuxOBc9cvmItYup4yq1Cdrh9GWkfOzLoCIy1nO?= =?us-ascii?Q?anR9FWZFHpg7VA0q3k7wN3bX+eBFJ+6JWxGkNjBhXX5IyiN9mQRqCKxFhUce?= =?us-ascii?Q?iWqU90a/tC+b0rvK3U3fxItThZZPRZsDAA0cyN/IzO85IgFhOQPzZOfsEjRm?= =?us-ascii?Q?fy4jsGetGoA6Paf69MASGHQUdGKagZyOaKA5Zm9FzWiR05uN90vvzgYBAQgC?= =?us-ascii?Q?h0HFeLlBp02rnv4hv/++LZqUwvzMm+WywKwpa195wP27btw0gojdHZH3QPQJ?= =?us-ascii?Q?6crs99nGOx3g/UaeC509PxX1FIeIZ3mU4dnYEyoJ238LeZ2K2skI/JmTve7B?= =?us-ascii?Q?2AKhBnsP6Wr1a0DHx5rSyOBsNQPnysLRAo57i3ABRAj/mdVQ+dSALDa/2wyw?= =?us-ascii?Q?oJbM1jc28lo+ar3/qYROraoJ0u7r+oLxjLGur/M19CNxNXuHvAQ0UOJRFeeL?= =?us-ascii?Q?Q2Ej/oRF3WEddjt1NbDBiAHSMm4Juz8H?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2024 18:53:16.8857 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14474434-b823-42cc-4962-08dd1882be0a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9409 Content-Type: text/plain; charset="utf-8" Currently boost_state is cached for every processor in cpudata structure and driver boost state is set for every processor. Both of these aren't necessary as the driver only needs to set once and the policy stores whether boost is enabled. Move the driver boost setting to registration and adjust all references to cached value to pull from the policy instead. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 26 +++++++++++++------------- drivers/cpufreq/amd-pstate.h | 1 - 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 308d30a25f100..f31703dbb754b 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -316,9 +316,10 @@ static int shmem_set_epp(struct amd_cpudata *cpudata, = u32 epp) return ret; } =20 -static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata, - int pref_index) +static int amd_pstate_set_energy_pref_index(struct cpufreq_policy *policy, + int pref_index) { + struct amd_cpudata *cpudata =3D policy->driver_data; int epp; =20 if (!pref_index) @@ -336,7 +337,7 @@ static int amd_pstate_set_energy_pref_index(struct amd_= cpudata *cpudata, epp, FIELD_GET(AMD_CPPC_MIN_PERF_MASK, cpudata->cppc_req_cached), FIELD_GET(AMD_CPPC_MAX_PERF_MASK, cpudata->cppc_req_cached), - cpudata->boost_state); + policy->boost_enabled); } =20 return amd_pstate_set_epp(cpudata, epp); @@ -746,7 +747,6 @@ static int amd_pstate_set_boost(struct cpufreq_policy *= policy, int state) guard(mutex)(&amd_pstate_driver_lock); =20 ret =3D amd_pstate_cpu_boost_update(policy, state); - WRITE_ONCE(cpudata->boost_state, !ret ? state : false); policy->boost_enabled =3D !ret ? state : false; refresh_frequency_limits(policy); =20 @@ -768,9 +768,6 @@ static int amd_pstate_init_boost_support(struct amd_cpu= data *cpudata) goto exit_err; } =20 - /* at least one CPU supports CPB, even if others fail later on to set up = */ - current_pstate_driver->boost_enabled =3D true; - ret =3D rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); if (ret) { pr_err_once("failed to read initial CPU boost state!\n"); @@ -1176,7 +1173,6 @@ static ssize_t show_energy_performance_available_pref= erences( static ssize_t store_energy_performance_preference( struct cpufreq_policy *policy, const char *buf, size_t count) { - struct amd_cpudata *cpudata =3D policy->driver_data; char str_preference[21]; ssize_t ret; =20 @@ -1190,7 +1186,7 @@ static ssize_t store_energy_performance_preference( =20 guard(mutex)(&amd_pstate_limits_lock); =20 - ret =3D amd_pstate_set_energy_pref_index(cpudata, ret); + ret =3D amd_pstate_set_energy_pref_index(policy, ret); =20 return ret ? ret : count; } @@ -1265,6 +1261,9 @@ static int amd_pstate_register_driver(int mode) return ret; } =20 + /* at least one CPU supports CPB */ + current_pstate_driver->boost_enabled =3D cpu_feature_enabled(X86_FEATURE_= CPB); + ret =3D cpufreq_register_driver(current_pstate_driver); if (ret) { amd_pstate_driver_cleanup(); @@ -1604,8 +1603,9 @@ static int amd_pstate_epp_set_policy(struct cpufreq_p= olicy *policy) return 0; } =20 -static int amd_pstate_epp_reenable(struct amd_cpudata *cpudata) +static int amd_pstate_epp_reenable(struct cpufreq_policy *policy) { + struct amd_cpudata *cpudata =3D policy->driver_data; u64 max_perf; int ret; =20 @@ -1619,7 +1619,7 @@ static int amd_pstate_epp_reenable(struct amd_cpudata= *cpudata) trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, cpudata->epp_cached, FIELD_GET(AMD_CPPC_MIN_PERF_MASK, cpudata->cppc_req_cached), - max_perf, cpudata->boost_state); + max_perf, policy->boost_enabled); } =20 return amd_pstate_update_perf(cpudata, 0, 0, max_perf, cpudata->epp_cache= d, false); @@ -1632,7 +1632,7 @@ static int amd_pstate_epp_cpu_online(struct cpufreq_p= olicy *policy) =20 pr_debug("AMD CPU Core %d going online\n", cpudata->cpu); =20 - ret =3D amd_pstate_epp_reenable(cpudata); + ret =3D amd_pstate_epp_reenable(policy); if (ret) return ret; cpudata->suspended =3D false; @@ -1690,7 +1690,7 @@ static int amd_pstate_epp_resume(struct cpufreq_polic= y *policy) guard(mutex)(&amd_pstate_limits_lock); =20 /* enable amd pstate from suspend state*/ - amd_pstate_epp_reenable(cpudata); + amd_pstate_epp_reenable(policy); =20 cpudata->suspended =3D false; } diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h index 7765c82f975c6..9747e3be6ceee 100644 --- a/drivers/cpufreq/amd-pstate.h +++ b/drivers/cpufreq/amd-pstate.h @@ -98,7 +98,6 @@ struct amd_cpudata { u64 cppc_cap1_cached; bool suspended; s16 epp_default; - bool boost_state; }; =20 /* --=20 2.43.0