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([2406:7400:94:42cf:4dea:f154:880:3adc]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2164d103993sm21837865ad.193.2024.12.09.09.49.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2024 09:49:17 -0800 (PST) From: Amit Pundir To: Stephen Boyd , Bjorn Andersson , Taniya Das , Konrad Dybcio Cc: linux-arm-msm , linux-clk , lkml Subject: [RESEND] clk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPs Date: Mon, 9 Dec 2024 23:19:12 +0530 Message-ID: <20241209174912.2526928-1-amit.pundir@linaro.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Similar to the earlier fixes meant for sm8x50 and x1e platforms, we have to stop using the shared clk ops for sdm845 QUPs as well. As Stephen Boyd pointed out in earlier fixes, there wasn't a problem to mark QUP clks shared until we started parking shared RCGs at clk registration time in commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration"). Parking at init is actually harmful to the UART when earlycon is used. If the device is pumping out data while the frequency changes and we see garbage on the serial console until the driver can probe and actually set a proper frequency. This patch reverts the QUP clk sharing ops part of commit 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845"), so that the QUPs on sdm845 don't get parked during clk registration and break UART operations. Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") Signed-off-by: Amit Pundir --- drivers/clk/qcom/gcc-sdm845.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index dc3aa7014c3e..c6692808a822 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -454,7 +454,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s0_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src =3D { @@ -470,7 +470,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s1_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src =3D { @@ -486,7 +486,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s2_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src =3D { @@ -502,7 +502,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s3_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src =3D { @@ -518,7 +518,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s4_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src =3D { @@ -534,7 +534,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s5_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src =3D { @@ -550,7 +550,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s6_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src =3D { @@ -566,7 +566,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap0_s7_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src =3D { @@ -582,7 +582,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s0_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src =3D { @@ -598,7 +598,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s1_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src =3D { @@ -614,7 +614,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s2_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src =3D { @@ -630,7 +630,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s3_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src =3D { @@ -646,7 +646,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s4_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src =3D { @@ -662,7 +662,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s5_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src =3D { @@ -678,7 +678,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s6_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src =3D { @@ -694,7 +694,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_= init =3D { .name =3D "gcc_qupv3_wrap1_s7_clk_src", .parent_data =3D gcc_parent_data_0, .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_ops, }; =20 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src =3D { --=20 2.43.0