From nobody Wed Dec 17 16:09:34 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3EE2139D1E; Mon, 9 Dec 2024 16:20:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733761233; cv=none; b=oZszlFpHSMyUspqHKYOlIlBR7HRJ6I25UJvKm53NMsG/xnfYxgJ2XAO4si+uYOC9rlLxm/4mk0uOk0AWA/VJaQ4ccltB8TGhvILChC6m98QkJcQ6pEsVaAw+oW1kex/gfcezY5mZAmnUX5fjsfknP+Vkbq6m9fOL8qgomGZlwQY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733761233; c=relaxed/simple; bh=7JDHmM2iHo64SWED4IWrIDJsip4EkJ+oHnJJMF+n2to=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Xl+Yq8BaD2rJkp9wa63dFqKUnJ7qIpWzo4a0oR5b3U4ebp1qacbQIO7+v4XxX+BEfa2NaoCfuC7380O1W2PxS2vFhz/7IlEMwqwtTBaEupPFhLe9TIhWCNx2re9gqZ87Dm3rsPqrNZGS71h/DRoTbk4ym5kh4N0HqncHMgHHj/g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=utzEcJwO; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="utzEcJwO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1733761232; x=1765297232; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=7JDHmM2iHo64SWED4IWrIDJsip4EkJ+oHnJJMF+n2to=; b=utzEcJwOq5975O48xR+/JzjMq7ulvnx6zAJSUZTNTNHcV5KnbFJVrkkt ZIlByOGZsFh1aog7/F+/NmX4apNTYRQs2MJGhdgysYFfiqd8OeXDJ/hkc kjXMHDnr2zO2LhWNQ4RlyjUGiZFCM6IKNJJi9sp2zcwlciZ3MpYE0mAG7 d8bmB43Ai4VxYG3ICmUxeIv/tWhwLaqV6UPiA9XjxtzGVm2zMLmNUnKpx Kbw6kbgWFlqCtH4QyzaXWYx3XYLUXQlIz2pFeJSZhGTZDY6vq/j6Y/lBT LUEQ59DF7lZTc2YLCptQymZuYY+d5O5XBAEJoJplG2fVSFpkwrjLUlZnm w==; X-CSE-ConnectionGUID: JLL7S6y7ROGYO+q1cU6U3w== X-CSE-MsgGUID: rxfh/GnkTX+ZaSxX2IE+0g== X-IronPort-AV: E=Sophos;i="6.12,219,1728975600"; d="scan'208";a="35311726" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Dec 2024 09:20:31 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 9 Dec 2024 09:20:17 -0700 Received: from HYD-DK-UNGSW20.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 9 Dec 2024 09:20:13 -0700 From: Tarun Alle To: , , , , , , , , , , Subject: [PATCH net-next 1/2] net: phy: phy-c45: Auto-negotiaion changes for T1 phy in phy library Date: Mon, 9 Dec 2024 21:44:26 +0530 Message-ID: <20241209161427.3580256-2-Tarun.Alle@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241209161427.3580256-1-Tarun.Alle@microchip.com> References: <20241209161427.3580256-1-Tarun.Alle@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Below auto-negotiation library changes required for T1 phys: - Lower byte advertisement register need to read after higher byte as per 802.3-2022 : Section 45.2.7.22. - Link status need to be get from control T1 registers for T1 phys. Signed-off-by: Tarun Alle --- drivers/net/phy/phy-c45.c | 36 ++++++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c index 0dac08e85304..85d8a9b9c3f6 100644 --- a/drivers/net/phy/phy-c45.c +++ b/drivers/net/phy/phy-c45.c @@ -234,15 +234,11 @@ static int genphy_c45_baset1_an_config_aneg(struct ph= y_device *phydev) return -EOPNOTSUPP; } =20 - adv_l |=3D linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); - - ret =3D phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, - adv_l_mask, adv_l); - if (ret < 0) - return ret; - if (ret > 0) - changed =3D 1; - + /* Ref. 802.3-2022 : Section 45.2.7.22 + * The Base Page value is transferred to mr_adv_ability when register + * 7.514 is written. + * Therefore, registers 7.515 and 7.516 should be written before 7.514. + */ adv_m |=3D linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); =20 ret =3D phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, @@ -252,6 +248,23 @@ static int genphy_c45_baset1_an_config_aneg(struct phy= _device *phydev) if (ret > 0) changed =3D 1; =20 + adv_l |=3D linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); + + if (changed) { + ret =3D phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, + adv_l); + if (ret < 0) + return ret; + } else { + ret =3D phy_modify_mmd_changed(phydev, MDIO_MMD_AN, + MDIO_AN_T1_ADV_L, + adv_l_mask, adv_l); + if (ret < 0) + return ret; + if (ret > 0) + changed =3D 1; + } + return changed; } =20 @@ -418,11 +431,14 @@ EXPORT_SYMBOL_GPL(genphy_c45_aneg_done); int genphy_c45_read_link(struct phy_device *phydev) { u32 mmd_mask =3D MDIO_DEVS_PMAPMD; + u16 reg =3D MDIO_CTRL1; int val, devad; bool link =3D true; =20 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { - val =3D phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); + if (genphy_c45_baset1_able(phydev)) + reg =3D MDIO_AN_T1_CTRL; + val =3D phy_read_mmd(phydev, MDIO_MMD_AN, reg); if (val < 0) return val; =20 --=20 2.34.1 From nobody Wed Dec 17 16:09:34 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6497513D638; 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X-CSE-ConnectionGUID: JLL7S6y7ROGYO+q1cU6U3w== X-CSE-MsgGUID: wDpFiZV9RvSP4oWuRd5a1A== X-IronPort-AV: E=Sophos;i="6.12,219,1728975600"; d="scan'208";a="35311727" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Dec 2024 09:20:31 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 9 Dec 2024 09:20:25 -0700 Received: from HYD-DK-UNGSW20.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 9 Dec 2024 09:20:22 -0700 From: Tarun Alle To: , , , , , , , , , , Subject: [PATCH net-next 2/2] net: phy: microchip_t1: Autonegotiaion support for LAN887x T1 phy Date: Mon, 9 Dec 2024 21:44:27 +0530 Message-ID: <20241209161427.3580256-3-Tarun.Alle@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241209161427.3580256-1-Tarun.Alle@microchip.com> References: <20241209161427.3580256-1-Tarun.Alle@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds auto-negotiation support for lan887x T1 phy. Signed-off-by: Tarun Alle --- drivers/net/phy/microchip_t1.c | 147 +++++++++++++++++++++++++++------ 1 file changed, 121 insertions(+), 26 deletions(-) diff --git a/drivers/net/phy/microchip_t1.c b/drivers/net/phy/microchip_t1.c index b17bf6708003..b8e65cb7d29e 100644 --- a/drivers/net/phy/microchip_t1.c +++ b/drivers/net/phy/microchip_t1.c @@ -268,6 +268,11 @@ /* End offset of samples */ #define SQI_INLIERS_END (SQI_INLIERS_START + SQI_INLIERS_NUM) =20 +#define LAN887X_VEND_CTRL_STAT_REG 0x8013 +#define LAN887X_AN_LOCAL_CFG_FAULT BIT(10) +#define LAN887X_AN_LOCAL_SLAVE BIT(9) +#define LAN887X_AN_LOCAL_MASTER BIT(8) + #define DRIVER_AUTHOR "Nisar Sayed " #define DRIVER_DESC "Microchip LAN87XX/LAN937x/LAN887x T1 PHY driver" =20 @@ -1259,11 +1264,6 @@ static int lan887x_get_features(struct phy_device *p= hydev) /* Enable twisted pair */ linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported); =20 - /* First patch only supports 100Mbps and 1000Mbps force-mode. - * T1 Auto-Negotiation (Clause 98 of IEEE 802.3) will be added later. - */ - linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); - return 0; } =20 @@ -1344,25 +1344,34 @@ static int lan887x_phy_setup(struct phy_device *phy= dev) =20 static int lan887x_100M_setup(struct phy_device *phydev) { + static const struct lan887x_regwr_map phy_comm_cfg[] =3D { + {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8}, + {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x0038}, + {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x000f}, + }; int ret; =20 /* (Re)configure the speed/mode dependent T1 settings */ - if (phydev->master_slave_set =3D=3D MASTER_SLAVE_CFG_MASTER_FORCE || - phydev->master_slave_set =3D=3D MASTER_SLAVE_CFG_MASTER_PREFERRED){ - static const struct lan887x_regwr_map phy_cfg[] =3D { - {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8}, - {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x0038}, - {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x000f}, - }; - - ret =3D lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg)); + if (phydev->autoneg =3D=3D AUTONEG_DISABLE) { + if (phydev->master_slave_set =3D=3D MASTER_SLAVE_CFG_MASTER_FORCE || + phydev->master_slave_set =3D=3D + MASTER_SLAVE_CFG_MASTER_PREFERRED) { + ret =3D lan887x_phy_config(phydev, phy_comm_cfg, + ARRAY_SIZE(phy_comm_cfg)); + } else { + static const struct lan887x_regwr_map phy_cfg[] =3D { + {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, + 0x0038}, + {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, + 0x0014}, + }; + + ret =3D lan887x_phy_config(phydev, phy_cfg, + ARRAY_SIZE(phy_cfg)); + } } else { - static const struct lan887x_regwr_map phy_cfg[] =3D { - {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x0038}, - {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x0014}, - }; - - ret =3D lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg)); + ret =3D lan887x_phy_config(phydev, phy_comm_cfg, + ARRAY_SIZE(phy_comm_cfg)); } if (ret < 0) return ret; @@ -1384,8 +1393,16 @@ static int lan887x_1000M_setup(struct phy_device *ph= ydev) if (ret < 0) return ret; =20 - return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL, - LAN887X_DSP_PMA_CONTROL_LNK_SYNC); + if (phydev->autoneg =3D=3D AUTONEG_ENABLE) + ret =3D phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, + LAN887X_REG_REG26, + LAN887X_REG_REG26_HW_INIT_SEQ_EN); + else + ret =3D phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, + LAN887X_DSP_PMA_CONTROL, + LAN887X_DSP_PMA_CONTROL_LNK_SYNC); + + return ret; } =20 static int lan887x_link_setup(struct phy_device *phydev) @@ -1407,6 +1424,11 @@ static int lan887x_phy_reset(struct phy_device *phyd= ev) { int ret, val; =20 + /* Disable aneg */ + ret =3D genphy_c45_an_disable_aneg(phydev); + if (ret < 0) + return ret; + /* Clear 1000M link sync */ ret =3D phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTR= OL, LAN887X_DSP_PMA_CONTROL_LNK_SYNC); @@ -1435,23 +1457,68 @@ static int lan887x_phy_reset(struct phy_device *phy= dev) 5000, 10000, true); } =20 +/* LAN887X Errata: 100M master issue. Dual speed in Aneg is not supported.= */ +static int lan887x_config_advert(struct phy_device *phydev) +{ + linkmode_and(phydev->advertising, phydev->advertising, + phydev->supported); + + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT1_Full_BIT, + phydev->advertising)) { + linkmode_clear_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, + phydev->advertising); + phydev->speed =3D SPEED_1000; + } else if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, + phydev->advertising)) { + linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT1_Full_BIT, + phydev->advertising); + phydev->speed =3D SPEED_100; + } else { + return -EINVAL; + } + + return 0; +} + static int lan887x_phy_reconfig(struct phy_device *phydev) { int ret; =20 - linkmode_zero(phydev->advertising); + if (phydev->autoneg =3D=3D AUTONEG_ENABLE) + ret =3D genphy_c45_an_config_aneg(phydev); + else + ret =3D genphy_c45_pma_setup_forced(phydev); + if (ret < 0) + return ret; =20 - ret =3D genphy_c45_pma_setup_forced(phydev); + /* For link to comeup, (re)configure the speed/mode + * dependent T1 settings + */ + ret =3D lan887x_link_setup(phydev); if (ret < 0) return ret; =20 - return lan887x_link_setup(phydev); + /* Autoneg to be re-started only after all settings are done */ + if (phydev->autoneg =3D=3D AUTONEG_ENABLE) { + ret =3D genphy_c45_restart_aneg(phydev); + if (ret < 0) + return ret; + } + + return 0; } =20 static int lan887x_config_aneg(struct phy_device *phydev) { int ret; =20 + /* Reject the not support advertisement settings */ + if (phydev->autoneg =3D=3D AUTONEG_ENABLE) { + ret =3D lan887x_config_advert(phydev); + if (ret < 0) + return ret; + } + /* LAN887x Errata: speed configuration changes require soft reset * and chip soft reset */ @@ -2058,6 +2125,34 @@ static int lan887x_get_sqi(struct phy_device *phydev) return FIELD_GET(T1_DCQ_SQI_MSK, rc); } =20 +static int lan887x_read_status(struct phy_device *phydev) +{ + int rc; + + phydev->master_slave_state =3D MASTER_SLAVE_STATE_UNKNOWN; + + rc =3D genphy_c45_read_status(phydev); + if (rc < 0) + return rc; + + if (phydev->autoneg =3D=3D AUTONEG_ENABLE) { + /* Fetch resolved mode */ + rc =3D phy_read_mmd(phydev, MDIO_MMD_AN, + LAN887X_VEND_CTRL_STAT_REG); + if (rc < 0) + return rc; + + if (rc & LAN887X_AN_LOCAL_MASTER) + phydev->master_slave_state =3D MASTER_SLAVE_STATE_MASTER; + else if (rc & LAN887X_AN_LOCAL_SLAVE) + phydev->master_slave_state =3D MASTER_SLAVE_STATE_SLAVE; + else if (rc & LAN887X_AN_LOCAL_CFG_FAULT) + phydev->master_slave_state =3D MASTER_SLAVE_STATE_ERR; + } + + return 0; +} + static struct phy_driver microchip_t1_phy_driver[] =3D { { PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX), @@ -2106,7 +2201,7 @@ static struct phy_driver microchip_t1_phy_driver[] = =3D { .get_strings =3D lan887x_get_strings, .suspend =3D genphy_suspend, .resume =3D genphy_resume, - .read_status =3D genphy_c45_read_status, + .read_status =3D lan887x_read_status, .cable_test_start =3D lan887x_cable_test_start, .cable_test_get_status =3D lan887x_cable_test_get_status, .config_intr =3D lan887x_config_intr, --=20 2.34.1