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(unknown []) by gzsmtp4 (Coremail) with SMTP id PygvCgDXvw6P41ZnqMLvAg--.38878S2; Mon, 09 Dec 2024 20:33:23 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, krzk+dt@kernel.org, s.hauer@pengutronix.de, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, derek.foreman@collabora.com, detlev.casanova@collabora.com, Andy Yan , Michael Riesch Subject: [PATCH v5 12/18] drm/rockchip: vop2: Support for different layer select configuration between VPs Date: Mon, 9 Dec 2024 20:33:16 +0800 Message-ID: <20241209123318.2781950-1-andyshrk@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241209122943.2781431-1-andyshrk@163.com> References: <20241209122943.2781431-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PygvCgDXvw6P41ZnqMLvAg--.38878S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxtrW8JF4UZF47Zw18Gry8Xwb_yoWfGr4Dpa yUursIg3W5CF45tryUJay8Zr4rGwnxtay3uan3Kw1xGF1rKrWDJF4ktF93A3Z8KF93ZryU Xw1YgryDZrZrtFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jF-eOUUUUU= X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/1tbiMwWwXmdW3sfNVwABsr Content-Type: text/plain; charset="utf-8" From: Andy Yan In the upcoming VOP for rk3576, every VP has it's own LAYER_SEL register, and the configuration value of each VP for the same window maybe different, so extend the layer_sel_id to array, let it can descption the layer select configuration value for different VP. Signed-off-by: Andy Yan Tested-by: Michael Riesch # on RK3568 Tested-by: Detlev Casanova --- (no changes since v4) Changes in v4: - Typo fix: selet->select drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 4 +-- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 38 ++++++++++---------- 2 files changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.h index a867e154801a..dcfa791be99d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h @@ -166,9 +166,9 @@ struct vop2_win_data { const unsigned int supported_rotations; =20 /** - * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2 + * @layer_sel_id: defined by register OVERLAY_LAYER_SEL or PORTn_LAYER_SEL */ - unsigned int layer_sel_id; + unsigned int layer_sel_id[ROCKCHIP_MAX_CRTC]; uint64_t feature; =20 uint8_t axi_bus_id; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm= /rockchip/rockchip_vop2_reg.c index 0cff1327c38e..80f9debd7aa9 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -350,7 +350,8 @@ static const struct vop2_win_data rk3568_vop_win_data[]= =3D { .formats =3D formats_smart, .nformats =3D ARRAY_SIZE(formats_smart), .format_modifiers =3D format_modifiers, - .layer_sel_id =3D 3, + /* 0xf means this layer can't attached to this VP */ + .layer_sel_id =3D { 3, 3, 3, 0xf }, .supported_rotations =3D DRM_MODE_REFLECT_Y, .type =3D DRM_PLANE_TYPE_PRIMARY, .max_upscale_factor =3D 8, @@ -363,7 +364,7 @@ static const struct vop2_win_data rk3568_vop_win_data[]= =3D { .nformats =3D ARRAY_SIZE(formats_smart), .format_modifiers =3D format_modifiers, .base =3D 0x1e00, - .layer_sel_id =3D 7, + .layer_sel_id =3D { 7, 7, 7, 0xf }, .supported_rotations =3D DRM_MODE_REFLECT_Y, .type =3D DRM_PLANE_TYPE_PRIMARY, .max_upscale_factor =3D 8, @@ -376,7 +377,7 @@ static const struct vop2_win_data rk3568_vop_win_data[]= =3D { .nformats =3D ARRAY_SIZE(formats_rk356x_esmart), .format_modifiers =3D format_modifiers, .base =3D 0x1a00, - .layer_sel_id =3D 6, + .layer_sel_id =3D { 6, 6, 6, 0xf }, .supported_rotations =3D DRM_MODE_REFLECT_Y, .type =3D DRM_PLANE_TYPE_PRIMARY, .max_upscale_factor =3D 8, @@ -389,7 +390,7 @@ static const struct vop2_win_data rk3568_vop_win_data[]= =3D { .nformats =3D ARRAY_SIZE(formats_rk356x_esmart), .format_modifiers =3D format_modifiers, .base =3D 0x1800, - .layer_sel_id =3D 2, + .layer_sel_id =3D { 2, 2, 2, 0xf }, .supported_rotations =3D DRM_MODE_REFLECT_Y, .type =3D DRM_PLANE_TYPE_PRIMARY, .max_upscale_factor =3D 8, @@ -402,7 +403,7 @@ static const struct vop2_win_data rk3568_vop_win_data[]= =3D { .formats =3D formats_cluster, .nformats =3D ARRAY_SIZE(formats_cluster), .format_modifiers =3D format_modifiers_afbc, - .layer_sel_id =3D 0, + .layer_sel_id =3D { 0, 0, 0, 0xf }, .supported_rotations =3D DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, .max_upscale_factor =3D 4, @@ -417,7 +418,7 @@ static const struct vop2_win_data rk3568_vop_win_data[]= =3D { .formats =3D formats_cluster, .nformats =3D ARRAY_SIZE(formats_cluster), .format_modifiers =3D format_modifiers_afbc, - .layer_sel_id =3D 1, + .layer_sel_id =3D { 1, 1, 1, 0xf }, .supported_rotations =3D DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, .type =3D DRM_PLANE_TYPE_OVERLAY, @@ -582,7 +583,7 @@ static const struct vop2_win_data rk3588_vop_win_data[]= =3D { .formats =3D formats_cluster, .nformats =3D ARRAY_SIZE(formats_cluster), .format_modifiers =3D format_modifiers_afbc, - .layer_sel_id =3D 0, + .layer_sel_id =3D { 0, 0, 0, 0 }, .supported_rotations =3D DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, .axi_bus_id =3D 0, @@ -600,7 +601,7 @@ static const struct vop2_win_data rk3588_vop_win_data[]= =3D { .formats =3D formats_cluster, .nformats =3D ARRAY_SIZE(formats_cluster), .format_modifiers =3D format_modifiers_afbc, - .layer_sel_id =3D 1, + .layer_sel_id =3D { 1, 1, 1, 1 }, .supported_rotations =3D DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, .type =3D DRM_PLANE_TYPE_PRIMARY, @@ -618,7 +619,7 @@ static const struct vop2_win_data rk3588_vop_win_data[]= =3D { .formats =3D formats_cluster, .nformats =3D ARRAY_SIZE(formats_cluster), .format_modifiers =3D format_modifiers_afbc, - .layer_sel_id =3D 4, + .layer_sel_id =3D { 4, 4, 4, 4 }, .supported_rotations =3D DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, .type =3D DRM_PLANE_TYPE_PRIMARY, @@ -636,7 +637,7 @@ static const struct vop2_win_data rk3588_vop_win_data[]= =3D { .formats =3D formats_cluster, .nformats =3D ARRAY_SIZE(formats_cluster), .format_modifiers =3D format_modifiers_afbc, - .layer_sel_id =3D 5, + .layer_sel_id =3D { 5, 5, 5, 5 }, .supported_rotations =3D DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, .type =3D DRM_PLANE_TYPE_PRIMARY, @@ -654,7 +655,7 @@ static const struct vop2_win_data rk3588_vop_win_data[]= =3D { .nformats =3D ARRAY_SIZE(formats_esmart), .format_modifiers =3D format_modifiers, .base =3D 0x1800, - .layer_sel_id =3D 2, + .layer_sel_id =3D { 2, 2, 2, 2 }, .supported_rotations =3D DRM_MODE_REFLECT_Y, .type =3D DRM_PLANE_TYPE_OVERLAY, .axi_bus_id =3D 0, @@ -670,7 +671,7 @@ static const struct vop2_win_data rk3588_vop_win_data[]= =3D { .nformats =3D ARRAY_SIZE(formats_esmart), .format_modifiers =3D format_modifiers, .base =3D 0x1a00, - .layer_sel_id =3D 3, + .layer_sel_id =3D { 3, 3, 3, 3 }, .supported_rotations =3D DRM_MODE_REFLECT_Y, .type =3D DRM_PLANE_TYPE_OVERLAY, .axi_bus_id =3D 0, @@ -686,7 +687,7 @@ static const struct vop2_win_data rk3588_vop_win_data[]= =3D { .formats =3D formats_esmart, .nformats =3D ARRAY_SIZE(formats_esmart), .format_modifiers =3D format_modifiers, - .layer_sel_id =3D 6, + .layer_sel_id =3D { 6, 6, 6, 6 }, .supported_rotations =3D DRM_MODE_REFLECT_Y, .type =3D DRM_PLANE_TYPE_OVERLAY, .axi_bus_id =3D 1, @@ -702,7 +703,7 @@ static const struct vop2_win_data rk3588_vop_win_data[]= =3D { .nformats =3D ARRAY_SIZE(formats_esmart), .format_modifiers =3D format_modifiers, .base =3D 0x1e00, - .layer_sel_id =3D 7, + .layer_sel_id =3D { 7, 7, 7, 7 }, .supported_rotations =3D DRM_MODE_REFLECT_Y, .type =3D DRM_PLANE_TYPE_OVERLAY, .axi_bus_id =3D 1, @@ -1452,7 +1453,7 @@ static void rk3568_vop2_setup_layer_mixer(struct vop2= _video_port *vp) */ for (old_layer_id =3D 0; old_layer_id < vop2->data->win_size; old_layer_= id++) { layer_sel_id =3D (layer_sel >> (4 * old_layer_id)) & 0xf; - if (layer_sel_id =3D=3D win->data->layer_sel_id) + if (layer_sel_id =3D=3D win->data->layer_sel_id[vp->id]) break; } =20 @@ -1462,7 +1463,7 @@ static void rk3568_vop2_setup_layer_mixer(struct vop2= _video_port *vp) for (i =3D 0; i < vop2->data->win_size; i++) { old_win =3D &vop2->win[i]; layer_sel_id =3D (layer_sel >> (4 * (plane->state->normalized_zpos + of= s))) & 0xf; - if (layer_sel_id =3D=3D old_win->data->layer_sel_id) + if (layer_sel_id =3D=3D old_win->data->layer_sel_id[vp->id]) break; } =20 @@ -1512,13 +1513,14 @@ static void rk3568_vop2_setup_layer_mixer(struct vo= p2_video_port *vp) layer_sel &=3D ~RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpo= s + ofs, 0x7); layer_sel |=3D RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos= + ofs, - win->data->layer_sel_id); + win->data->layer_sel_id[vp->id]); /* * When we bind a window from layerM to layerN, we also need to move the= old * window on layerN to layerM to avoid one window selected by two or mor= e layers. */ layer_sel &=3D ~RK3568_OVL_LAYER_SEL__LAYER(old_layer_id, 0x7); - layer_sel |=3D RK3568_OVL_LAYER_SEL__LAYER(old_layer_id, old_win->data->= layer_sel_id); + layer_sel |=3D RK3568_OVL_LAYER_SEL__LAYER(old_layer_id, + old_win->data->layer_sel_id[vp->id]); } =20 vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel); --=20 2.34.1