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Mon, 09 Dec 2024 05:39:58 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B95dvGd015856 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Dec 2024 05:39:57 GMT Received: from [10.213.96.82] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 8 Dec 2024 21:39:55 -0800 From: Vivek Pernamitta Date: Mon, 9 Dec 2024 11:09:50 +0530 Subject: [PATCH v4] bus: mhi: host: pci_generic: Add support for QDU100 device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241209-qdu100_us-v4-1-f9010b2a09a2@quicinc.com> X-B4-Tracking: v=1; b=H4sIAKWCVmcC/43NTW7DIBCG4atErEvEDEOArnqPKqr4GRoWtRtTW 60i3z1OlE2sVMryG/G8nETjoXITr5uTGHiqrfbdMuhlI9IhdJ8sa162QIUEgFYe8whKfYxNhph thh3o5KJY3n8PXOrvtfW+X/ahtp9++LumJ7pcH1UmkiApWLTGckYDb8exptqlbeq/Ltmb8WvD2 UXmAISeHxpUem08ksISsQQw/xham6RD8YayNzE/a6iQdgjgnH/6H5OiKXFH2qC+M/t5ns+v2nn NqAEAAA== X-Change-ID: 20241127-qdu100_us-abd7d1613c8b To: Manivannan Sadhasivam CC: , , , , "Vivek Pernamitta" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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The Qualcomm X100 5G RAN Accelerator card is designed to enhance Open vRAN servers by offloading CPUs from intensive 5G baseband functions. Link: https://docs.qualcomm.com/bundle/publicresource/87-79371-1_REV_A_Qual= comm_X100_5G_RAN_Accelerator_Card_Product_Brief.pdf Signed-off-by: Vivek Pernamitta --- changes from V3: - Removed IP_SW1 and IP_SW2 support currently, will add once SW_IP1/2 channels support are added to mhi-net driver. - Removed qdu100 edl images, as EDL images are not needed. - Added space inbetween kernel_ulong_t and mhi_qcom_qdu100_info. - QDU100 XBL FW images were pushed to linux-firmware git repo https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.g= it/tree/qcom/qdu100 changes from V2: - updated commit text. changes from V1: - Changing naming convention from modem_qcom_qdu100* to mhi_qcom_qdu100*. - Updated commit text. - Fixed and corrected by passing mhi_pci_dev_info struct instead of mhi_controller_config. --- --- drivers/bus/mhi/host/pci_generic.c | 55 ++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 55 insertions(+) diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_= generic.c index 07645ce2119a71c9277356e962252b840379cd81..dee9fa9e7ae441fbc9a86e53694= 568c0ba192002 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -245,6 +245,58 @@ struct mhi_pci_dev_info { .channel =3D ch_num, \ } =20 +static const struct mhi_channel_config mhi_qcom_qdu100_channels[] =3D { + MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2), + MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2), + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1), + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1), + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3), + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3), + MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3), + MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4), + MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4), + MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4), + MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4), + MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4), + MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4), + MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5), + MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5), +}; + +static struct mhi_event_config mhi_qcom_qdu100_events[] =3D { + /* first ring is control+data ring */ + MHI_EVENT_CONFIG_CTRL(0, 64), + /* SAHARA dedicated event ring */ + MHI_EVENT_CONFIG_SW_DATA(1, 256), + /* Software channels dedicated event ring */ + MHI_EVENT_CONFIG_SW_DATA(2, 64), + MHI_EVENT_CONFIG_SW_DATA(3, 256), + MHI_EVENT_CONFIG_SW_DATA(4, 256), + /* Software IP channels dedicated event ring */ + MHI_EVENT_CONFIG_SW_DATA(5, 512), + MHI_EVENT_CONFIG_SW_DATA(6, 512), + MHI_EVENT_CONFIG_SW_DATA(7, 512), +}; + +static const struct mhi_controller_config mhi_qcom_qdu100_config =3D { + .max_channels =3D 128, + .timeout_ms =3D 120000, + .num_channels =3D ARRAY_SIZE(mhi_qcom_qdu100_channels), + .ch_cfg =3D mhi_qcom_qdu100_channels, + .num_events =3D ARRAY_SIZE(mhi_qcom_qdu100_events), + .event_cfg =3D mhi_qcom_qdu100_events, +}; + +static const struct mhi_pci_dev_info mhi_qcom_qdu100_info =3D { + .name =3D "qcom-qdu100", + .fw =3D "qcom/qdu100/xbl_s.melf", + .edl_trigger =3D true, + .config =3D &mhi_qcom_qdu100_config, + .bar_num =3D MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width =3D 32, + .sideband_wake =3D false, +}; + static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] =3D { MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), @@ -822,6 +874,9 @@ static const struct pci_device_id mhi_pci_id_table[] = =3D { /* NETPRISMA FCUN69 (SDX6X) */ { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1001), .driver_data =3D (kernel_ulong_t) &mhi_netprisma_fcun69_info }, + /* QDU100, x100-DU */ + { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601), + .driver_data =3D (kernel_ulong_t) &mhi_qcom_qdu100_info }, { } }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); --- base-commit: 28955f4fa2823e39f1ecfb3a37a364563527afbc change-id: 20241127-qdu100_us-abd7d1613c8b Best regards, --=20 Vivek Pernamitta