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Mon, 09 Dec 2024 16:04:52 -0800 (PST) From: Atish Patra Date: Mon, 09 Dec 2024 16:04:46 -0800 Subject: [PATCH 2/2] drivers/perf: riscv: Do not allow invalid raw event config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241209-pmu_event_fixes-v1-2-d9525e90072c@rivosinc.com> References: <20241209-pmu_event_fixes-v1-0-d9525e90072c@rivosinc.com> In-Reply-To: <20241209-pmu_event_fixes-v1-0-d9525e90072c@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Atish Patra , Anup Patel , Will Deacon , Mark Rutland , Mayuresh Chitale , Samuel Holland Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 The SBI specification allows only lower 48bits of hpmeventX to be configured via SBI PMU. Currently, the driver masks of the higher bits but doesn't return an error. This will lead to an additional SBI call for config matching which should return for an invalid event error in most of the cases. However, if a platform(i.e Rocket and sifive cores) implements a bitmap of all bits in the event encoding this will lead to an incorrect event being programmed leading to user confusion. Report the error to the user if higher bits are set during the event mapping itself to avoid the confusion and save an additional SBI call. Suggested-by: Samuel Holland Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 3473ba02abf3..fb6eda90f771 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -507,7 +507,7 @@ static int pmu_sbi_event_map(struct perf_event *event, = u64 *econfig) { u32 type =3D event->attr.type; u64 config =3D event->attr.config; - int ret; + int ret =3D -ENOENT; =20 /* * Ensure we are finished checking standard hardware events for @@ -536,8 +536,11 @@ static int pmu_sbi_event_map(struct perf_event *event,= u64 *econfig) =20 switch (config >> 62) { case 0: - ret =3D RISCV_PMU_RAW_EVENT_IDX; - *econfig =3D config & RISCV_PMU_RAW_EVENT_MASK; + /* Return error any bits [48-63] is set as it is not allowed by the sp= ec */ + if (!(config & ~RISCV_PMU_RAW_EVENT_MASK)) { + *econfig =3D config & RISCV_PMU_RAW_EVENT_MASK; + ret =3D RISCV_PMU_RAW_EVENT_IDX; + } break; case 2: ret =3D (config & 0xFFFF) | (SBI_PMU_EVENT_TYPE_FW << 16); @@ -554,7 +557,6 @@ static int pmu_sbi_event_map(struct perf_event *event, = u64 *econfig) } break; default: - ret =3D -ENOENT; break; } =20 --=20 2.34.1