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Mon, 09 Dec 2024 20:16:29 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B9KGSMG022003 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Dec 2024 20:16:28 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 9 Dec 2024 12:16:28 -0800 From: Abhinav Kumar Date: Mon, 9 Dec 2024 12:15:57 -0800 Subject: [PATCH v2] drm/msm/dpu: filter out too wide modes if no 3dmux is present Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241209-no_3dmux-v2-1-fcad057eb92e@quicinc.com> X-B4-Tracking: v=1; b=H4sIAPxPV2cC/23MQQ7CIBCF4as0sxYDg0B05T1MYwignUXBgm1qG u4udu3yf3n5NighUyhw6TbIYaFCKbbAQwdusPEZGPnWgBxPArlmMd2lH+eVKRRWqWC51mdo91c OD1p36ta3Hqi8U/7s8iJ+6x9kEUwwg9ajNsZKlNdpJkfRHV0aoa+1fgFwe2vDogAAAA== X-Change-ID: 20241206-no_3dmux-521a55ea0669 To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" CC: , , , , "Abhinav Kumar" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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In such a case, a layer exceeding the max_mixer_width cannot be split, hence cannot be supported. Filter out the modes which exceed the max_mixer_width when there is no 3dmux present. Also, add a check in the dpu_crtc_atomic_check() to return failure for such modes. Signed-off-by: Abhinav Kumar --- Note: this was only compile tested, so its pending validation on QCS615 --- Changes in v2: - replace MODE_BAD with MODE_BAD_HVALUE to indicate the failure better - Link to v1: https://lore.kernel.org/r/20241206-no_3dmux-v1-1-72ad2677a323= @quicinc.com --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 9f6ffd344693ecfb633095772a31ada5613345dc..87d76f388bef48c880ae70ddcdb= 76ccb0336ad32 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -732,6 +732,13 @@ static int _dpu_crtc_check_and_setup_lm_bounds(struct = drm_crtc *crtc, struct dpu_kms *dpu_kms =3D _dpu_crtc_get_kms(crtc); int i; =20 + /* if we cannot merge 2 LMs (no 3d mux) better to fail earlier + * before even checking the width after the split + */ + if (!dpu_kms->catalog->caps->has_3d_merge + && adj_mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width) + return -E2BIG; + for (i =3D 0; i < cstate->num_mixers; i++) { struct drm_rect *r =3D &cstate->lm_bounds[i]; r->x1 =3D crtc_split_width * i; @@ -1251,6 +1258,12 @@ static enum drm_mode_status dpu_crtc_mode_valid(stru= ct drm_crtc *crtc, { struct dpu_kms *dpu_kms =3D _dpu_crtc_get_kms(crtc); =20 + /* if there is no 3d_mux block we cannot merge LMs so we cannot + * split the large layer into 2 LMs, filter out such modes + */ + if (!dpu_kms->catalog->caps->has_3d_merge + && mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width) + return MODE_BAD_HVALUE; /* * max crtc width is equal to the max mixer width * 2 and max height is 4K */ --- base-commit: af2ea8ab7a546b430726183458da0a173d331272 change-id: 20241206-no_3dmux-521a55ea0669 Best regards, --=20 Abhinav Kumar