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Sun, 08 Dec 2024 07:07:43 -0800 (PST) From: Anup Patel To: Thomas Gleixner Cc: Marc Zyngier , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Palmer Dabbelt , Paul Walmsley , Atish Patra , Andrew Jones , Sunil V L , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, Anup Patel Subject: [PATCH 4/4] irqchip/riscv-imsic: Move to common MSI lib Date: Sun, 8 Dec 2024 20:37:11 +0530 Message-ID: <20241208150711.297624-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241208150711.297624-1-apatel@ventanamicro.com> References: <20241208150711.297624-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Simplify the non-leaf MSI domain handling in the RISC-V IMSIC driver by using msi_lib_init_dev_msi_info() and msi_lib_irq_domain_select() provided by common MSI lib. Signed-off-by: Thomas Gleixner Signed-off-by: Andrew Jones Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 8 +- drivers/irqchip/irq-riscv-imsic-platform.c | 114 +-------------------- 2 files changed, 6 insertions(+), 116 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 55d7122121e2..6b767b8c974f 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -587,13 +587,7 @@ config RISCV_IMSIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_MATRIX_ALLOCATOR select GENERIC_MSI_IRQ - -config RISCV_IMSIC_PCI - bool - depends on RISCV_IMSIC - depends on PCI - depends on PCI_MSI - default RISCV_IMSIC + select IRQ_MSI_LIB =20 config SIFIVE_PLIC bool diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index 33a8261e6017..5bc1f03cbacb 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -20,6 +20,7 @@ #include #include =20 +#include "irq-msi-lib.h" #include "irq-riscv-imsic-state.h" =20 static bool imsic_cpu_page_phys(unsigned int cpu, unsigned int guest_index, @@ -201,22 +202,6 @@ static void imsic_irq_domain_free(struct irq_domain *d= omain, unsigned int virq, irq_domain_free_irqs_parent(domain, virq, nr_irqs); } =20 -static int imsic_irq_domain_select(struct irq_domain *domain, struct irq_f= wspec *fwspec, - enum irq_domain_bus_token bus_token) -{ - const struct msi_parent_ops *ops =3D domain->msi_parent_ops; - u32 busmask =3D BIT(bus_token); - - if (fwspec->fwnode !=3D domain->fwnode || fwspec->param_count !=3D 0) - return 0; - - /* Handle pure domain searches */ - if (bus_token =3D=3D ops->bus_select_token) - return 1; - - return !!(ops->bus_select_mask & busmask); -} - #ifdef CONFIG_GENERIC_IRQ_DEBUGFS static void imsic_irq_debug_show(struct seq_file *m, struct irq_domain *d, struct irq_data *irqd, int ind) @@ -233,110 +218,21 @@ static void imsic_irq_debug_show(struct seq_file *m,= struct irq_domain *d, static const struct irq_domain_ops imsic_base_domain_ops =3D { .alloc =3D imsic_irq_domain_alloc, .free =3D imsic_irq_domain_free, - .select =3D imsic_irq_domain_select, + .select =3D msi_lib_irq_domain_select, #ifdef CONFIG_GENERIC_IRQ_DEBUGFS .debug_show =3D imsic_irq_debug_show, #endif }; =20 -#ifdef CONFIG_RISCV_IMSIC_PCI - -static void imsic_pci_mask_irq(struct irq_data *d) -{ - pci_msi_mask_irq(d); - irq_chip_mask_parent(d); -} - -static void imsic_pci_unmask_irq(struct irq_data *d) -{ - irq_chip_unmask_parent(d); - pci_msi_unmask_irq(d); -} - -#define MATCH_PCI_MSI BIT(DOMAIN_BUS_PCI_MSI) - -#else - -#define MATCH_PCI_MSI 0 - -#endif - -static bool imsic_init_dev_msi_info(struct device *dev, - struct irq_domain *domain, - struct irq_domain *real_parent, - struct msi_domain_info *info) -{ - const struct msi_parent_ops *pops =3D real_parent->msi_parent_ops; - - /* MSI parent domain specific settings */ - switch (real_parent->bus_token) { - case DOMAIN_BUS_NEXUS: - if (WARN_ON_ONCE(domain !=3D real_parent)) - return false; -#ifdef CONFIG_SMP - info->chip->irq_set_affinity =3D irq_chip_set_affinity_parent; -#endif - break; - default: - WARN_ON_ONCE(1); - return false; - } - - /* Is the target supported? */ - switch (info->bus_token) { -#ifdef CONFIG_RISCV_IMSIC_PCI - case DOMAIN_BUS_PCI_DEVICE_MSI: - case DOMAIN_BUS_PCI_DEVICE_MSIX: - info->chip->irq_mask =3D imsic_pci_mask_irq; - info->chip->irq_unmask =3D imsic_pci_unmask_irq; - break; -#endif - case DOMAIN_BUS_DEVICE_MSI: - /* - * Per-device MSI should never have any MSI feature bits - * set. It's sole purpose is to create a dumb interrupt - * chip which has a device specific irq_write_msi_msg() - * callback. - */ - if (WARN_ON_ONCE(info->flags)) - return false; - - /* Core managed MSI descriptors */ - info->flags |=3D MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS | - MSI_FLAG_FREE_MSI_DESCS; - break; - case DOMAIN_BUS_WIRED_TO_MSI: - break; - default: - WARN_ON_ONCE(1); - return false; - } - - /* Use hierarchial chip operations re-trigger */ - info->chip->irq_retrigger =3D irq_chip_retrigger_hierarchy; - - /* - * Mask out the domain specific MSI feature flags which are not - * supported by the real parent. - */ - info->flags &=3D pops->supported_flags; - - /* Enforce the required flags */ - info->flags |=3D pops->required_flags; - - return true; -} - -#define MATCH_PLATFORM_MSI BIT(DOMAIN_BUS_PLATFORM_MSI) - static const struct msi_parent_ops imsic_msi_parent_ops =3D { .supported_flags =3D MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX, .required_flags =3D MSI_FLAG_USE_DEF_DOM_OPS | - MSI_FLAG_USE_DEF_CHIP_OPS, + MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSI_MASK_PARENT, .bus_select_token =3D DOMAIN_BUS_NEXUS, .bus_select_mask =3D MATCH_PCI_MSI | MATCH_PLATFORM_MSI, - .init_dev_msi_info =3D imsic_init_dev_msi_info, + .init_dev_msi_info =3D msi_lib_init_dev_msi_info, }; =20 int imsic_irqdomain_init(void) --=20 2.43.0