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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH v2 11/16] cpufreq/amd-pstate: Cache EPP value and use that everywhere Date: Sun, 8 Dec 2024 00:30:26 -0600 Message-ID: <20241208063031.3113-12-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241208063031.3113-1-mario.limonciello@amd.com> References: <20241208063031.3113-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D8:EE_|CY8PR12MB7729:EE_ X-MS-Office365-Filtering-Correlation-Id: 74137e7e-9a1d-4f37-a51b-08dd1751e245 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?DAHjzW/43oft+Ud3h88wWD45FqJsqRA1bYLL1+VMwUSmRb60UyaRWE2scyoq?= =?us-ascii?Q?xQHG6c+nsnK1LNp/H1mV+9eg15jRSh2Nm7MQuMql0IginBQ4gMKV5Zplngnx?= =?us-ascii?Q?xAAR2LYi4tl0n4eKDRjBKd4AyiodZ9kKx1yR32/7R/tdtRIekU4rWG/QDcro?= =?us-ascii?Q?AIllcD6v2/e3aoxClBz5GmsmI6wYnL4MOeu/5ChUWmx3Vwp0phHRr9Tgd4a5?= =?us-ascii?Q?PSBLNLOAdfxwhXI40lh6bw3mRQw+X4I0KwLsTs+GMRalhvsWNKhztbIvCjNx?= =?us-ascii?Q?qmasxytfceVv7/7AJr1mo8TpDDdglKlmOum4uXGmYynVjKugWsxxRjydzBNR?= =?us-ascii?Q?nV/vK806q/VYgPWEfpp8+2diItCu9aiPI/i4Yv4hI8pLIfI5IBzkFe0mp6Z/?= =?us-ascii?Q?Q0+lT37Tte2Un45tuFlhPOzVgTlfoSp08KapufqBDFKFdU9nC1fJ07f+sNsL?= =?us-ascii?Q?nTLC/aWgnAbgbGLWVs1RAwuQmpLcUmkTT4y9h0COKt9DDLbIjgbXf2gtdJ7m?= =?us-ascii?Q?cDIE0dQ1JNCg8/6dFZqD25P+YE+Xg0o8WwbDXnH5NaatKO2FsUaorR1UzPLP?= =?us-ascii?Q?4pQo8KRmFEnFgADvE/4KG2FMgmzibndYHscN3KQsPB3Ag5Pj8VULo11sadin?= =?us-ascii?Q?pROItnQzi9wAw2HOKMiXGLoHcj67xS8ZgAJal0a1Z3zd0XSkvlqHQsDcfTtD?= =?us-ascii?Q?ulpH3woG0BXtK61fFCAp4ThOC17hybM6olRBO8Bo0gDJj1YLbWTv52ZoxcTJ?= =?us-ascii?Q?cRHgRXEk3wc89NfNsU9vFbbxWOAdHHQjdfwQFd8rP5XwRJIC2Ga1Q1bAap6R?= =?us-ascii?Q?Oobpoq2B/R7Y7tP36VSOts4pGOC6nHTLsQ8Fs9nuRjJy2/u+/twKGK3KC2nd?= =?us-ascii?Q?LZqDOR5RGGfrLu3nwXdsr+WLjvgmJibq9Y3hWuQk1KZ2iXmhXaLWRUxAh7y/?= =?us-ascii?Q?mSXuDSP/bjsApN4Ct1ASKOisyctMHehcQzizKAEQ5aCrP0r/v7u6Vu2Y8rqI?= =?us-ascii?Q?uXmEcdtWIUcG9EAeZMYFDdZKWYXsSG+9ES/+EROHydbcHnYNSx0TQ10HGa5r?= =?us-ascii?Q?FINpB/Ceno/xvOTFLqQuMY9oet1D+GlB0w5bcfYH4Qa0m9KDgjUegIi8CbD+?= =?us-ascii?Q?cbv8ReJE09osPBQVNf9qNb6rqBaApeJUP9nwoAVZ/+JQO0mi4cEZMQOzzJpi?= =?us-ascii?Q?g9zjGQr+UsLp2af6sv7zAxu1IHDxdeHtyNOVGurD5RGW2Mkvf92+BaaLOjey?= =?us-ascii?Q?3Y5sXGckN2StzVo5J2rLnFZUIRbE5zXbtY59CaTGYuwu8xzjSxtndbfJvJa8?= =?us-ascii?Q?5CH9BJvyOq1n19n6rvZueLf0wDfKwlzL9jCN1U30fIq2mrYpqp6iHVXoz/vB?= =?us-ascii?Q?VR82czQ0cOlZWq87Q4sr6i/gGqcGE/TAqiHxw6Q69JQAJdwprO59oX1TZc8b?= =?us-ascii?Q?tUMudXnbZRN0orL7xbiGoLXScxLnYr/P?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Dec 2024 06:31:01.0764 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74137e7e-9a1d-4f37-a51b-08dd1751e245 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7729 Content-Type: text/plain; charset="utf-8" Cache the value in cpudata->epp_cached, and use that for all callers. As all callers use cached value merge amd_pstate_get_energy_pref_index() into show_energy_performance_preference(). Check if the EPP value is changed before writing it to MSR or shared memory region. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- v2: * Drop extra mutex --- drivers/cpufreq/amd-pstate.c | 105 ++++++++++++++--------------------- 1 file changed, 43 insertions(+), 62 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index dc3c45b6f5103..d21acd961edcd 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -186,29 +186,28 @@ static inline int get_mode_idx_from_str(const char *s= tr, size_t size) static DEFINE_MUTEX(amd_pstate_limits_lock); static DEFINE_MUTEX(amd_pstate_driver_lock); =20 -static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) +static s16 msr_get_epp(struct amd_cpudata *cpudata) { + u64 value; int ret; =20 - if (!cppc_req_cached) { - ret =3D rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req_cached); - if (ret < 0) { - pr_debug("Could not retrieve energy perf value (%d)\n", ret); - return ret; - } + ret =3D rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); + if (ret < 0) { + pr_debug("Could not retrieve energy perf value (%d)\n", ret); + return ret; } =20 - return FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cppc_req_cached); + return FIELD_GET(AMD_CPPC_EPP_PERF_MASK, value); } =20 DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp); =20 -static inline s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc= _req_cached) +static inline s16 amd_pstate_get_epp(struct amd_cpudata *cpudata) { - return static_call(amd_pstate_get_epp)(cpudata, cppc_req_cached); + return static_call(amd_pstate_get_epp)(cpudata); } =20 -static s16 shmem_get_epp(struct amd_cpudata *cpudata, u64 dummy) +static s16 shmem_get_epp(struct amd_cpudata *cpudata) { u64 epp; int ret; @@ -222,35 +221,6 @@ static s16 shmem_get_epp(struct amd_cpudata *cpudata, = u64 dummy) return (s16)(epp & 0xff); } =20 -static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata) -{ - s16 epp; - int index =3D -EINVAL; - - epp =3D amd_pstate_get_epp(cpudata, 0); - if (epp < 0) - return epp; - - switch (epp) { - case AMD_CPPC_EPP_PERFORMANCE: - index =3D EPP_INDEX_PERFORMANCE; - break; - case AMD_CPPC_EPP_BALANCE_PERFORMANCE: - index =3D EPP_INDEX_BALANCE_PERFORMANCE; - break; - case AMD_CPPC_EPP_BALANCE_POWERSAVE: - index =3D EPP_INDEX_BALANCE_POWERSAVE; - break; - case AMD_CPPC_EPP_POWERSAVE: - index =3D EPP_INDEX_POWERSAVE; - break; - default: - break; - } - - return index; -} - static int msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch) { @@ -275,19 +245,23 @@ static inline int amd_pstate_update_perf(struct amd_c= pudata *cpudata, =20 static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) { - u64 value =3D READ_ONCE(cpudata->cppc_req_cached); + u64 value, prev; int ret; =20 + value =3D prev =3D READ_ONCE(cpudata->cppc_req_cached); value &=3D ~AMD_CPPC_EPP_PERF_MASK; value |=3D FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); =20 + if (value =3D=3D prev) + return 0; + ret =3D wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); if (ret) { pr_err("failed to set energy perf value (%d)\n", ret); return ret; } =20 - cpudata->epp_cached =3D epp; + WRITE_ONCE(cpudata->epp_cached, epp); WRITE_ONCE(cpudata->cppc_req_cached, value); =20 return ret; @@ -305,13 +279,16 @@ static int shmem_set_epp(struct amd_cpudata *cpudata,= u32 epp) int ret; struct cppc_perf_ctrls perf_ctrls; =20 + if (epp =3D=3D cpudata->epp_cached) + return 0; + perf_ctrls.energy_perf =3D epp; ret =3D cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); if (ret) { pr_debug("failed to set energy perf value (%d)\n", ret); return ret; } - cpudata->epp_cached =3D epp; + WRITE_ONCE(cpudata->epp_cached, epp); =20 return ret; } @@ -1214,9 +1191,22 @@ static ssize_t show_energy_performance_preference( struct amd_cpudata *cpudata =3D policy->driver_data; int preference; =20 - preference =3D amd_pstate_get_energy_pref_index(cpudata); - if (preference < 0) - return preference; + switch (cpudata->epp_cached) { + case AMD_CPPC_EPP_PERFORMANCE: + preference =3D EPP_INDEX_PERFORMANCE; + break; + case AMD_CPPC_EPP_BALANCE_PERFORMANCE: + preference =3D EPP_INDEX_BALANCE_PERFORMANCE; + break; + case AMD_CPPC_EPP_BALANCE_POWERSAVE: + preference =3D EPP_INDEX_BALANCE_POWERSAVE; + break; + case AMD_CPPC_EPP_POWERSAVE: + preference =3D EPP_INDEX_POWERSAVE; + break; + default: + return -EINVAL; + } =20 return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); } @@ -1501,7 +1491,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_pol= icy *policy) =20 policy->driver_data =3D cpudata; =20 - cpudata->epp_cached =3D cpudata->epp_default =3D amd_pstate_get_epp(cpuda= ta, 0); + cpudata->epp_cached =3D cpudata->epp_default =3D amd_pstate_get_epp(cpuda= ta); =20 policy->min =3D policy->cpuinfo.min_freq; policy->max =3D policy->cpuinfo.max_freq; @@ -1555,35 +1545,26 @@ static int amd_pstate_epp_update_limit(struct cpufr= eq_policy *policy) { struct amd_cpudata *cpudata =3D policy->driver_data; u64 value; - s16 epp; =20 amd_pstate_update_min_max_limit(policy); =20 value =3D READ_ONCE(cpudata->cppc_req_cached); =20 value &=3D ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | - AMD_CPPC_DES_PERF_MASK); + AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK); value |=3D FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, cpudata->max_limit_perf); value |=3D FIELD_PREP(AMD_CPPC_DES_PERF_MASK, 0); value |=3D FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, cpudata->min_limit_perf); =20 - /* Get BIOS pre-defined epp value */ - epp =3D amd_pstate_get_epp(cpudata, value); - if (epp < 0) { - /** - * This return value can only be negative for shared_memory - * systems where EPP register read/write not supported. - */ - return epp; - } - if (cpudata->policy =3D=3D CPUFREQ_POLICY_PERFORMANCE) - epp =3D 0; + WRITE_ONCE(cpudata->epp_cached, 0); + value |=3D FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, cpudata->epp_cached); =20 WRITE_ONCE(cpudata->cppc_req_cached, value); =20 if (trace_amd_pstate_epp_perf_enabled()) { - trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, epp, + trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, + cpudata->epp_cached, cpudata->min_limit_perf, cpudata->max_limit_perf, policy->boost_enabled); @@ -1592,7 +1573,7 @@ static int amd_pstate_epp_update_limit(struct cpufreq= _policy *policy) amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U, cpudata->max_limit_perf, false); =20 - return amd_pstate_set_epp(cpudata, epp); + return amd_pstate_set_epp(cpudata, READ_ONCE(cpudata->epp_cached)); } =20 static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) --=20 2.43.0