From nobody Wed Dec 17 19:39:39 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AE7E204583 for ; Fri, 6 Dec 2024 19:38:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733513914; cv=none; b=oniAAUskM0Yy+QbMArlVsTZhi26DoTDnZz/ZmRREYrgSp67g3zAYF81tX3OT8BacfnFlIesWP1vbd6PUi4sgwjIP/BP4GOwZXSEIVzzZ645VjnNGJBKZQ/GHE18C3rp8kAn93u0ppXAlR+VdrqR3Z5OfQXQS8JdnjMkqVhWNHDM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733513914; c=relaxed/simple; bh=b/j6b5Gous9RrT4FOdntQAYYy7LmiWUgmtd5pcxZO0Q=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=B8QKFCcqdgqBY4a/GXq7/DjVFM4sQW6xVfnKHEg3KcHKsxB6yqkv9zQtIsW1hGjGtstJ6FORDfevcTsni0p05ZYxcquxz5P2OYcVpNwEi/RsJo0DICvQGrNrXHk5I+OAA5aVP5QmvVaeUcMSeg75iUaOQ3A7G3oAgEfr/mbkY2Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=O2Dy4Ye/; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="O2Dy4Ye/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733513912; x=1765049912; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=b/j6b5Gous9RrT4FOdntQAYYy7LmiWUgmtd5pcxZO0Q=; b=O2Dy4Ye/BEOP2lMEJgz9VqM/6NHGGtn1u42ITKIMKcWvJIJ8YrQgxvJx hAH7LdZ8cGnh0L9q/TnbPC0NZ/W3mYCy6xYKPKabRBURFlX+mZ9of0OeS JPYWiO0X0tgsaV+M6lcUVoJYSmMcpCEsk9oorp2CJzfHTwNhYos07GmbT gcDN2mpskB19QtLPopfOKazyJDMDDaO/ThZmoR7ew6G9LlHsBLqGy6dNw hmFnHdsTygrzXl/x5q93/qKCQEWF9cI1a/rwdYC2I1rcfrROYAOevR1KR dzFcsPODOwb3tL/TIjyiqVwYPEckZ397QnuCk16NBkltpVqZQJJ0E6/8s g==; X-CSE-ConnectionGUID: 5fbsiA9xT0CvtTgBycftkw== X-CSE-MsgGUID: Zyt2+EETRzKp5oXwiABLPw== X-IronPort-AV: E=McAfee;i="6700,10204,11278"; a="34027878" X-IronPort-AV: E=Sophos;i="6.12,214,1728975600"; d="scan'208";a="34027878" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2024 11:38:32 -0800 X-CSE-ConnectionGUID: JA0c3wYgQpikQx8JgjdSDw== X-CSE-MsgGUID: iJclW5wwQ8O1zANGmwEFbw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,214,1728975600"; d="scan'208";a="94979001" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa009.fm.intel.com with ESMTP; 06 Dec 2024 11:38:31 -0800 Subject: [PATCH 1/5] x86/cpu: Introduce new microcode matching helper To: linux-kernel@vger.kernel.org Cc: x86@kernel.org,tglx@linutronix.de,bp@alien8.de,kan.liang@linux.intel.com,mingo@kernel.org,peterz@infradead.org,tony.luck@intel.com,pawan.kumar.gupta@linux.intel.com,Dave Hansen From: Dave Hansen Date: Fri, 06 Dec 2024 11:38:31 -0800 References: <20241206193829.89E12D0B@davehans-spike.ostc.intel.com> In-Reply-To: <20241206193829.89E12D0B@davehans-spike.ostc.intel.com> Message-Id: <20241206193831.3BBA3834@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The 'x86_cpu_id' and 'x86_cpu_desc' structures are very similar and need to be consolidated. There is a microcode version matching function for 'x86_cpu_desc' but not 'x86_cpu_id'. Create one for 'x86_cpu_id'. This essentially just leverages the x86_cpu_id->driver_data field to replace the less generic x86_cpu_desc->x86_microcode_rev field. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/cpu_device_id.h | 1 + b/arch/x86/kernel/cpu/match.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff -puN arch/x86/include/asm/cpu_device_id.h~min-ucode-rev arch/x86/inclu= de/asm/cpu_device_id.h --- a/arch/x86/include/asm/cpu_device_id.h~min-ucode-rev 2024-12-06 11:33:1= 5.663128241 -0800 +++ b/arch/x86/include/asm/cpu_device_id.h 2024-12-06 11:33:15.667128399 -0= 800 @@ -278,5 +278,6 @@ struct x86_cpu_desc { =20 extern const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id *mat= ch); extern bool x86_cpu_has_min_microcode_rev(const struct x86_cpu_desc *table= ); +extern bool x86_match_min_microcode_rev(const struct x86_cpu_id *table); =20 #endif /* _ASM_X86_CPU_DEVICE_ID */ diff -puN arch/x86/kernel/cpu/match.c~min-ucode-rev arch/x86/kernel/cpu/mat= ch.c --- a/arch/x86/kernel/cpu/match.c~min-ucode-rev 2024-12-06 11:33:15.6631282= 41 -0800 +++ b/arch/x86/kernel/cpu/match.c 2024-12-06 11:33:15.667128399 -0800 @@ -86,3 +86,14 @@ bool x86_cpu_has_min_microcode_rev(const return true; } EXPORT_SYMBOL_GPL(x86_cpu_has_min_microcode_rev); + +bool x86_match_min_microcode_rev(const struct x86_cpu_id *table) +{ + const struct x86_cpu_id *res =3D x86_match_cpu(table); + + if (!res || res->driver_data > boot_cpu_data.microcode) + return false; + + return true; +} +EXPORT_SYMBOL_GPL(x86_match_min_microcode_rev); _ From nobody Wed Dec 17 19:39:39 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D3B0204599 for ; Fri, 6 Dec 2024 19:38:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733513915; cv=none; b=Fgzmhail5gbnKQ7Gz51pnPa/kgkoPjOrSzcix5J6ra3IDBekiDuJuVZmQlpoRUxOMAzhCVtIoiIujC6VUbHiPPexz64dg0f5wthhOU++1/+k0rUGLAAHYpY7nYtA5psayPsnnfHrl+g3TBDoIziwaSM/S9gbdLx/ubFc6PcHd8Q= ARC-Message-Signature: i=1; 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d="scan'208";a="94979014" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa009.fm.intel.com with ESMTP; 06 Dec 2024 11:38:33 -0800 Subject: [PATCH 2/5] x86/cpu: Expose only stepping min/max interface To: linux-kernel@vger.kernel.org Cc: x86@kernel.org,tglx@linutronix.de,bp@alien8.de,kan.liang@linux.intel.com,mingo@kernel.org,peterz@infradead.org,tony.luck@intel.com,pawan.kumar.gupta@linux.intel.com,Dave Hansen From: Dave Hansen Date: Fri, 06 Dec 2024 11:38:32 -0800 References: <20241206193829.89E12D0B@davehans-spike.ostc.intel.com> In-Reply-To: <20241206193829.89E12D0B@davehans-spike.ostc.intel.com> Message-Id: <20241206193832.DCF208DC@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The x86_match_cpu() infrastructure can match CPU steppings. Since there are only 16 possible steppings, the matching infrastructure goes all out and stores the stepping match as a bitmap. That means it can match any possible steppings in a single list entry. Fun. But it exposes this bitmap to each of the X86_MATCH_*() helpers when none of them really need a bitmap. It makes up for this by exporting a helper (X86_STEPPINGS()) which converts a contiguous stepping range into the bitmap which every single user leverages. Instead of a bitmap, have the main helper for this sort of thing (X86_MATCH_VFM_STEPPING()) just take a stepping range. This ends up actually being even more compact than before. Leave the helper in place (renamed to __X86_STEPPINGS()) to make it more clear what is going on instead of just having a random GENMASK() in the middle of an already complicated macro. One oddity that I hit was this macro: #define VULNBL_INTEL_STEPPINGS(vfm, max_stepping, issues) \ X86_MATCH_VFM_STEPPINGS(vfm, X86_STEPPING_MIN, max_stepping, issues) It *could* have been converted over to take a min/max stepping value for each entry. But that would have been a bit too verbose and would prevent the one oddball in the list (INTEL_COMETLAKE_L stepping 0) from sticking out. Instead, just have it take a *maximum* stepping and imply that the match is from 0=3D>max_stepping. This is functional for all the cases now and also retains the nice property of having INTEL_COMETLAKE_L stepping 0 stick out like a sore thumb. Signed-off-by: Dave Hansen Suggested-by: Ingo Molnar --- b/arch/x86/include/asm/cpu_device_id.h | 15 +++--- b/arch/x86/kernel/apic/apic.c | 18 +++---- b/arch/x86/kernel/cpu/common.c | 78 ++++++++++++++++------------= ----- b/drivers/edac/i10nm_base.c | 20 ++++---- b/drivers/edac/skx_base.c | 2=20 b/include/linux/mod_devicetable.h | 2=20 6 files changed, 69 insertions(+), 66 deletions(-) diff -puN arch/x86/include/asm/cpu_device_id.h~zap-X86_STEPPINGS arch/x86/i= nclude/asm/cpu_device_id.h --- a/arch/x86/include/asm/cpu_device_id.h~zap-X86_STEPPINGS 2024-12-06 11:= 33:16.179148524 -0800 +++ b/arch/x86/include/asm/cpu_device_id.h 2024-12-06 11:33:16.191148995 -0= 800 @@ -56,7 +56,6 @@ /* x86_cpu_id::flags */ #define X86_CPU_ID_FLAG_ENTRY_VALID BIT(0) =20 -#define X86_STEPPINGS(mins, maxs) GENMASK(maxs, mins) /** * X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE - Base macro for CPU match= ing * @_vendor: The vendor name, e.g. INTEL, AMD, HYGON, ..., ANY @@ -208,6 +207,7 @@ VFM_MODEL(vfm), \ X86_STEPPING_ANY, X86_FEATURE_ANY, data) =20 +#define __X86_STEPPINGS(mins, maxs) GENMASK(maxs, mins) /** * X86_MATCH_VFM_STEPPINGS - Match encoded vendor/family/model/stepping * @vfm: Encoded 8-bits each for vendor, family, model @@ -218,12 +218,13 @@ * * feature is set to wildcard */ -#define X86_MATCH_VFM_STEPPINGS(vfm, steppings, data) \ - X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE( \ - VFM_VENDOR(vfm), \ - VFM_FAMILY(vfm), \ - VFM_MODEL(vfm), \ - steppings, X86_FEATURE_ANY, data) +#define X86_MATCH_VFM_STEPPINGS(vfm, min_step, max_step, data) \ + X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE( \ + VFM_VENDOR(vfm), \ + VFM_FAMILY(vfm), \ + VFM_MODEL(vfm), \ + __X86_STEPPINGS(min_step, max_step), \ + X86_FEATURE_ANY, data) =20 /** * X86_MATCH_VFM_FEATURE - Match encoded vendor/family/model/feature diff -puN arch/x86/kernel/apic/apic.c~zap-X86_STEPPINGS arch/x86/kernel/api= c/apic.c --- a/arch/x86/kernel/apic/apic.c~zap-X86_STEPPINGS 2024-12-06 11:33:16.183= 148680 -0800 +++ b/arch/x86/kernel/apic/apic.c 2024-12-06 11:33:16.191148995 -0800 @@ -509,19 +509,19 @@ static struct clock_event_device lapic_c static DEFINE_PER_CPU(struct clock_event_device, lapic_events); =20 static const struct x86_cpu_id deadline_match[] __initconst =3D { - X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL_X, X86_STEPPINGS(0x2, 0x2), 0x3a), = /* EP */ - X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL_X, X86_STEPPINGS(0x4, 0x4), 0x0f), = /* EX */ + X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL_X, 0x2, 0x2, 0x3a), /* EP */ + X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL_X, 0x4, 0x4, 0x0f), /* EX */ =20 X86_MATCH_VFM(INTEL_BROADWELL_X, 0x0b000020), =20 - X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x2, 0x2), 0x000= 00011), - X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x3, 0x3), 0x070= 0000e), - X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x4, 0x4), 0x0f0= 0000c), - X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x5, 0x5), 0x0e0= 00003), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, 0x2, 0x2, 0x00000011), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, 0x3, 0x3, 0x0700000e), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, 0x4, 0x4, 0x0f00000c), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, 0x5, 0x5, 0x0e000003), =20 - X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), 0x01000= 136), - X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), 0x02000= 014), - X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), 0), + X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, 0x3, 0x3, 0x01000136), + X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, 0x4, 0x4, 0x02000014), + X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, 0x5, 0xf, 0), =20 X86_MATCH_VFM(INTEL_HASWELL, 0x22), X86_MATCH_VFM(INTEL_HASWELL_L, 0x20), diff -puN arch/x86/kernel/cpu/common.c~zap-X86_STEPPINGS arch/x86/kernel/cp= u/common.c --- a/arch/x86/kernel/cpu/common.c~zap-X86_STEPPINGS 2024-12-06 11:33:16.18= 3148680 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-12-06 11:33:16.191148995 -0800 @@ -1201,8 +1201,8 @@ static const __initconst struct x86_cpu_ #define VULNBL(vendor, family, model, blacklist) \ X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) =20 -#define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \ - X86_MATCH_VFM_STEPPINGS(vfm, steppings, issues) +#define VULNBL_INTEL_STEPPINGS(vfm, max_stepping, issues) \ + X86_MATCH_VFM_STEPPINGS(vfm, X86_STEPPING_MIN, max_stepping, issues) =20 #define VULNBL_AMD(family, blacklist) \ VULNBL(AMD, family, X86_MODEL_ANY, blacklist) @@ -1227,43 +1227,43 @@ static const __initconst struct x86_cpu_ #define RFDS BIT(7) =20 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst =3D { - VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_L, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_G, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_X, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_G, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_X, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLE= ED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLE= ED | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED= | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLE= ED | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEE= D | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED), - VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_S= BDS | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_S= BDS | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO |= RETBLEED), - VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_= SBDS | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE_L, X86_STEPPING_ANY, GDS), - VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE, X86_STEPPING_ANY, GDS), - VULNBL_INTEL_STEPPINGS(INTEL_LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_S= BDS | RETBLEED), - VULNBL_INTEL_STEPPINGS(INTEL_ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLE= ED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE_L, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_P, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_S, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GRACEMONT, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO= _SBDS | RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO | RF= DS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MM= IO_SBDS | RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_D, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEPPING_ANY, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE, X86_STEPPING_MAX, SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_HASWELL, X86_STEPPING_MAX, SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_L, X86_STEPPING_MAX, SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_G, X86_STEPPING_MAX, SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_X, X86_STEPPING_MAX, MMIO), + VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPING_MAX, MMIO), + VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_G, X86_STEPPING_MAX, SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_X, X86_STEPPING_MAX, MMIO), + VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL, X86_STEPPING_MAX, SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPING_MAX, MMIO | RETBLE= ED | GDS), + VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_L, X86_STEPPING_MAX, MMIO | RETBLE= ED | GDS | SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE, X86_STEPPING_MAX, MMIO | RETBLEED= | GDS | SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE_L, X86_STEPPING_MAX, MMIO | RETBLE= ED | GDS | SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE, X86_STEPPING_MAX, MMIO | RETBLEE= D | GDS | SRBDS), + VULNBL_INTEL_STEPPINGS(INTEL_CANNONLAKE_L, X86_STEPPING_MAX, RETBLEED), + VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_L, X86_STEPPING_MAX, MMIO | MMIO_S= BDS | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_D, X86_STEPPING_MAX, MMIO | GDS), + VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPING_MAX, MMIO | GDS), + VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE, X86_STEPPING_MAX, MMIO | MMIO_S= BDS | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, 0x0, MMIO | RETBLEED), + VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPING_MAX, MMIO | MMIO_= SBDS | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE_L, X86_STEPPING_MAX, GDS), + VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE, X86_STEPPING_MAX, GDS), + VULNBL_INTEL_STEPPINGS(INTEL_LAKEFIELD, X86_STEPPING_MAX, MMIO | MMIO_S= BDS | RETBLEED), + VULNBL_INTEL_STEPPINGS(INTEL_ROCKETLAKE, X86_STEPPING_MAX, MMIO | RETBLE= ED | GDS), + VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE, X86_STEPPING_MAX, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE_L, X86_STEPPING_MAX, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE, X86_STEPPING_MAX, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_P, X86_STEPPING_MAX, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_S, X86_STEPPING_MAX, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GRACEMONT, X86_STEPPING_MAX, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT, X86_STEPPING_MAX, MMIO | MMIO= _SBDS | RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPING_MAX, MMIO | RF= DS), + VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_L, X86_STEPPING_MAX, MMIO | MM= IO_SBDS | RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT, X86_STEPPING_MAX, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_D, X86_STEPPING_MAX, RFDS), + VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEPPING_MAX, RFDS), =20 VULNBL_AMD(0x15, RETBLEED), VULNBL_AMD(0x16, RETBLEED), diff -puN drivers/edac/i10nm_base.c~zap-X86_STEPPINGS drivers/edac/i10nm_ba= se.c --- a/drivers/edac/i10nm_base.c~zap-X86_STEPPINGS 2024-12-06 11:33:16.18714= 8838 -0800 +++ b/drivers/edac/i10nm_base.c 2024-12-06 11:33:16.191148995 -0800 @@ -938,16 +938,16 @@ static struct res_config gnr_cfg =3D { }; =20 static const struct x86_cpu_id i10nm_cpuids[] =3D { - X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPINGS(0x0, 0x3), &i= 10nm_cfg0), - X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPINGS(0x4, 0xf), &i= 10nm_cfg1), - X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPINGS(0x0, 0x3), &i10nm_= cfg0), - X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPINGS(0x4, 0xf), &i10nm_= cfg1), - X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_D, X86_STEPPINGS(0x0, 0xf), &i10nm_= cfg1), - X86_MATCH_VFM_STEPPINGS(INTEL_SAPPHIRERAPIDS_X, X86_STEPPINGS(0x0, 0xf), = &spr_cfg), - X86_MATCH_VFM_STEPPINGS(INTEL_EMERALDRAPIDS_X, X86_STEPPINGS(0x0, 0xf), &= spr_cfg), - X86_MATCH_VFM_STEPPINGS(INTEL_GRANITERAPIDS_X, X86_STEPPINGS(0x0, 0xf), &= gnr_cfg), - X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_CRESTMONT_X, X86_STEPPINGS(0x0, 0xf), = &gnr_cfg), - X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_CRESTMONT, X86_STEPPINGS(0x0, 0xf), &g= nr_cfg), + X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_TREMONT_D, 0x0, 0x3, &i10nm_cfg0), + X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_TREMONT_D, 0x4, 0xf, &i10nm_cfg1), + X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_X, 0x0, 0x3, &i10nm_cfg0), + X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_X, 0x4, 0xf, &i10nm_cfg1), + X86_MATCH_VFM_STEPPINGS(INTEL_ICELAKE_D, 0x0, 0xf, &i10nm_cfg1), + X86_MATCH_VFM_STEPPINGS(INTEL_SAPPHIRERAPIDS_X, 0x0, 0xf, &spr_cfg), + X86_MATCH_VFM_STEPPINGS(INTEL_EMERALDRAPIDS_X, 0x0, 0xf, &spr_cfg), + X86_MATCH_VFM_STEPPINGS(INTEL_GRANITERAPIDS_X, 0x0, 0xf, &gnr_cfg), + X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_CRESTMONT_X, 0x0, 0xf, &gnr_cfg), + X86_MATCH_VFM_STEPPINGS(INTEL_ATOM_CRESTMONT, 0x0, 0xf, &gnr_cfg), {} }; MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids); diff -puN drivers/edac/skx_base.c~zap-X86_STEPPINGS drivers/edac/skx_base.c --- a/drivers/edac/skx_base.c~zap-X86_STEPPINGS 2024-12-06 11:33:16.1871488= 38 -0800 +++ b/drivers/edac/skx_base.c 2024-12-06 11:33:16.191148995 -0800 @@ -164,7 +164,7 @@ static struct res_config skx_cfg =3D { }; =20 static const struct x86_cpu_id skx_cpuids[] =3D { - X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPINGS(0x0, 0xf), &skx_cf= g), + X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, 0x0, 0xf, &skx_cfg), { } }; MODULE_DEVICE_TABLE(x86cpu, skx_cpuids); diff -puN include/linux/mod_devicetable.h~zap-X86_STEPPINGS include/linux/m= od_devicetable.h --- a/include/linux/mod_devicetable.h~zap-X86_STEPPINGS 2024-12-06 11:33:16= .187148838 -0800 +++ b/include/linux/mod_devicetable.h 2024-12-06 11:33:16.191148995 -0800 @@ -700,6 +700,8 @@ struct x86_cpu_id { #define X86_FAMILY_ANY 0 #define X86_MODEL_ANY 0 #define X86_STEPPING_ANY 0 +#define X86_STEPPING_MIN 0 +#define X86_STEPPING_MAX 0xf #define X86_FEATURE_ANY 0 /* Same as FPU, you can't test for that */ =20 /* _ From nobody Wed Dec 17 19:39:39 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E3B4206286 for ; Fri, 6 Dec 2024 19:38:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733513917; cv=none; b=JiSdbPazo8cSaujX0qVaPAG/opPYhvVNQwFeUnvwMGclRTKrz0GyFQuowZaBAIpVPb8BRbvMtFLXLCTQv3Mv3TXeXoB6tqCOC17HTbJbIhFb7bF83dYGImJ9Q6RAqkaOgGofuDUmGzbKRj+dCPjaombXWYBBsjF6UPhaUkyHODg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733513917; c=relaxed/simple; bh=VtbOhO5Fcm+Lvu2qyiy3/HJvm06tqTpf5L0cvQxTqSw=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=tdrQ15Jfqc5k/bgMCOg5vKHTyPDTKbN29bW+7Ywi9PMFfkSvLLdPjHtA+VKC8SDyUJXqWvkD5dCcc7HyWI9nMDn4+cdyUP5ZcUnLHgP4oaPrOCll3aFRCSaUNx0kdfSSTby7nha76etmOp/AscCS35ueTxQiDWMY2cwxiEfBZuw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=eiecnL7L; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="eiecnL7L" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733513915; x=1765049915; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=VtbOhO5Fcm+Lvu2qyiy3/HJvm06tqTpf5L0cvQxTqSw=; b=eiecnL7LWUxKX0DSJbVCNuEpeZkueTgILlM8bwRXF5EZA02lmTu6rK46 eS1LqhOMBOWjlMYD7QKwyv3g6Q6/n57rTqRBpZ86f9NMcRpSzAkGhPYfl B+lJRfzOIz2xwAi2fk5Vs8RhpPSe9eOkNCUMpuMVsRvU3tO3zlpN8Wuwv Ve9z/B9r3ePaj7vXUwflAgCQZExEvuJePxEJqgvxu/OVGlUe6tY2MZyIH GdQqWlBP/8XEWe6uMZIxzpADP+e8Y5XibYFO7qu4ht7pnCDjkR+vIftGs /kguUUethoF+TRF2slfp1va4VqB0KdKweV87EKHN3RhrcQJe0i6dxzDro g==; X-CSE-ConnectionGUID: 8YZCIMEVTxOwcR69T/E0aw== X-CSE-MsgGUID: QNt7mLgoQYulhpbSbo+XNg== X-IronPort-AV: E=McAfee;i="6700,10204,11278"; a="34027895" X-IronPort-AV: E=Sophos;i="6.12,214,1728975600"; d="scan'208";a="34027895" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2024 11:38:35 -0800 X-CSE-ConnectionGUID: fB/hFe0cRS2CWIUwTAWAhQ== X-CSE-MsgGUID: k5RFNKJ8S16S5GW9dUjb5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,214,1728975600"; d="scan'208";a="94979022" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa009.fm.intel.com with ESMTP; 06 Dec 2024 11:38:34 -0800 Subject: [PATCH 3/5] x86/cpu: Replace PEBS use of 'x86_cpu_desc' use with 'x86_cpu_id' To: linux-kernel@vger.kernel.org Cc: x86@kernel.org,tglx@linutronix.de,bp@alien8.de,kan.liang@linux.intel.com,mingo@kernel.org,peterz@infradead.org,tony.luck@intel.com,pawan.kumar.gupta@linux.intel.com,Dave Hansen From: Dave Hansen Date: Fri, 06 Dec 2024 11:38:34 -0800 References: <20241206193829.89E12D0B@davehans-spike.ostc.intel.com> In-Reply-To: <20241206193829.89E12D0B@davehans-spike.ostc.intel.com> Message-Id: <20241206193834.3ABE2E95@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The 'x86_cpu_desc' and 'x86_cpu_id' structures are very similar. Reduce duplicate infrastructure by moving the few users of 'x86_cpu_id' to the much more common variant. The existing X86_MATCH_VFM_STEPPINGS() helper matches ranges of steppings. Instead of introducing a single-stepping match function which could get confusing when paired with the range, just use the stepping min/max match helper and use min=3D=3Dmax. Note that this makes the table more vertically compact because multiple entries like this: INTEL_CPU_DESC(INTEL_SKYLAKE_X, 4, 0x00000000), INTEL_CPU_DESC(INTEL_SKYLAKE_X, 5, 0x00000000), INTEL_CPU_DESC(INTEL_SKYLAKE_X, 6, 0x00000000), INTEL_CPU_DESC(INTEL_SKYLAKE_X, 7, 0x00000000), can be consolidated down to a single stepping range. Signed-off-by: Dave Hansen --- b/arch/x86/events/intel/core.c | 63 +++++++++++++++++-------------------= ----- 1 file changed, 27 insertions(+), 36 deletions(-) diff -puN arch/x86/events/intel/core.c~zap-x86_cpu_desc arch/x86/events/int= el/core.c --- a/arch/x86/events/intel/core.c~zap-x86_cpu_desc 2024-12-06 11:33:16.775= 171950 -0800 +++ b/arch/x86/events/intel/core.c 2024-12-06 11:33:16.779172107 -0800 @@ -5371,42 +5371,33 @@ static __init void intel_clovertown_quir x86_pmu.pebs_constraints =3D NULL; } =20 -static const struct x86_cpu_desc isolation_ucodes[] =3D { - INTEL_CPU_DESC(INTEL_HASWELL, 3, 0x0000001f), - INTEL_CPU_DESC(INTEL_HASWELL_L, 1, 0x0000001e), - INTEL_CPU_DESC(INTEL_HASWELL_G, 1, 0x00000015), - INTEL_CPU_DESC(INTEL_HASWELL_X, 2, 0x00000037), - INTEL_CPU_DESC(INTEL_HASWELL_X, 4, 0x0000000a), - INTEL_CPU_DESC(INTEL_BROADWELL, 4, 0x00000023), - INTEL_CPU_DESC(INTEL_BROADWELL_G, 1, 0x00000014), - INTEL_CPU_DESC(INTEL_BROADWELL_D, 2, 0x00000010), - INTEL_CPU_DESC(INTEL_BROADWELL_D, 3, 0x07000009), - INTEL_CPU_DESC(INTEL_BROADWELL_D, 4, 0x0f000009), - INTEL_CPU_DESC(INTEL_BROADWELL_D, 5, 0x0e000002), - INTEL_CPU_DESC(INTEL_BROADWELL_X, 1, 0x0b000014), - INTEL_CPU_DESC(INTEL_SKYLAKE_X, 3, 0x00000021), - INTEL_CPU_DESC(INTEL_SKYLAKE_X, 4, 0x00000000), - INTEL_CPU_DESC(INTEL_SKYLAKE_X, 5, 0x00000000), - INTEL_CPU_DESC(INTEL_SKYLAKE_X, 6, 0x00000000), - INTEL_CPU_DESC(INTEL_SKYLAKE_X, 7, 0x00000000), - INTEL_CPU_DESC(INTEL_SKYLAKE_X, 11, 0x00000000), - INTEL_CPU_DESC(INTEL_SKYLAKE_L, 3, 0x0000007c), - INTEL_CPU_DESC(INTEL_SKYLAKE, 3, 0x0000007c), - INTEL_CPU_DESC(INTEL_KABYLAKE, 9, 0x0000004e), - INTEL_CPU_DESC(INTEL_KABYLAKE_L, 9, 0x0000004e), - INTEL_CPU_DESC(INTEL_KABYLAKE_L, 10, 0x0000004e), - INTEL_CPU_DESC(INTEL_KABYLAKE_L, 11, 0x0000004e), - INTEL_CPU_DESC(INTEL_KABYLAKE_L, 12, 0x0000004e), - INTEL_CPU_DESC(INTEL_KABYLAKE, 10, 0x0000004e), - INTEL_CPU_DESC(INTEL_KABYLAKE, 11, 0x0000004e), - INTEL_CPU_DESC(INTEL_KABYLAKE, 12, 0x0000004e), - INTEL_CPU_DESC(INTEL_KABYLAKE, 13, 0x0000004e), +static const struct x86_cpu_id isolation_ucodes[] =3D { + X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL, 3, 3, 0x0000001f), + X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL_L, 1, 1, 0x0000001e), + X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL_G, 1, 1, 0x00000015), + X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL_X, 2, 2, 0x00000037), + X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL_X, 4, 4, 0x0000000a), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL, 4, 4, 0x00000023), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_G, 1, 1, 0x00000014), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, 2, 2, 0x00000010), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, 3, 3, 0x07000009), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, 4, 4, 0x0f000009), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, 5, 5, 0x0e000002), + X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_X, 1, 1, 0x0b000014), + X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, 3, 3, 0x00000021), + X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, 4, 7, 0x00000000), + X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, 11, 11, 0x00000000), + X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_L, 3, 3, 0x0000007c), + X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE, 3, 3, 0x0000007c), + X86_MATCH_VFM_STEPPINGS(INTEL_KABYLAKE, 9, 9, 0x0000004e), + X86_MATCH_VFM_STEPPINGS(INTEL_KABYLAKE_L, 9, 12, 0x0000004e), + X86_MATCH_VFM_STEPPINGS(INTEL_KABYLAKE, 10, 13, 0x0000004e), {} }; =20 static void intel_check_pebs_isolation(void) { - x86_pmu.pebs_no_isolation =3D !x86_cpu_has_min_microcode_rev(isolation_uc= odes); + x86_pmu.pebs_no_isolation =3D !x86_match_min_microcode_rev(isolation_ucod= es); } =20 static __init void intel_pebs_isolation_quirk(void) @@ -5416,16 +5407,16 @@ static __init void intel_pebs_isolation_ intel_check_pebs_isolation(); } =20 -static const struct x86_cpu_desc pebs_ucodes[] =3D { - INTEL_CPU_DESC(INTEL_SANDYBRIDGE, 7, 0x00000028), - INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X, 6, 0x00000618), - INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X, 7, 0x0000070c), +static const struct x86_cpu_id pebs_ucodes[] =3D { + X86_MATCH_VFM_STEPPINGS(INTEL_SANDYBRIDGE, 7, 7, 0x00000028), + X86_MATCH_VFM_STEPPINGS(INTEL_SANDYBRIDGE_X, 6, 6, 0x00000618), + X86_MATCH_VFM_STEPPINGS(INTEL_SANDYBRIDGE_X, 7, 7, 0x0000070c), {} }; =20 static bool intel_snb_pebs_broken(void) { - return !x86_cpu_has_min_microcode_rev(pebs_ucodes); + return !x86_match_min_microcode_rev(pebs_ucodes); } =20 static void intel_snb_check_microcode(void) _ From nobody Wed Dec 17 19:39:39 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1ECC20ADF7 for ; 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a="34027902" X-IronPort-AV: E=Sophos;i="6.12,214,1728975600"; d="scan'208";a="34027902" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2024 11:38:36 -0800 X-CSE-ConnectionGUID: Ck38/9QGTUGuJSjuhJfX9g== X-CSE-MsgGUID: y6vhAnC9SeCSyaBD9zfWOg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,214,1728975600"; d="scan'208";a="94979042" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa009.fm.intel.com with ESMTP; 06 Dec 2024 11:38:36 -0800 Subject: [PATCH 4/5] x86/cpu: Move AMD erratum 1386 table over to 'x86_cpu_id' To: linux-kernel@vger.kernel.org Cc: x86@kernel.org,tglx@linutronix.de,bp@alien8.de,kan.liang@linux.intel.com,mingo@kernel.org,peterz@infradead.org,tony.luck@intel.com,pawan.kumar.gupta@linux.intel.com,Dave Hansen From: Dave Hansen Date: Fri, 06 Dec 2024 11:38:35 -0800 References: <20241206193829.89E12D0B@davehans-spike.ostc.intel.com> In-Reply-To: <20241206193829.89E12D0B@davehans-spike.ostc.intel.com> Message-Id: <20241206193835.9B87AADD@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The AMD erratum 1386 detection code uses and old style 'x86_cpu_desc' table. Replace it with 'x86_cpu_id' so the old style can be removed. I did not create a new helper macro here. The new table is certainly more noisy than the old and it can be improved on. But I was hesitant to create a new macro just for a single site that is only two ugly lines in the end. Signed-off-by: Dave Hansen --- b/arch/x86/kernel/cpu/amd.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff -puN arch/x86/kernel/cpu/amd.c~amd-x86_cpu_id arch/x86/kernel/cpu/amd.c --- a/arch/x86/kernel/cpu/amd.c~amd-x86_cpu_id 2024-12-06 11:33:17.27119144= 6 -0800 +++ b/arch/x86/kernel/cpu/amd.c 2024-12-06 11:33:17.275191602 -0800 @@ -795,10 +795,9 @@ static void init_amd_bd(struct cpuinfo_x clear_rdrand_cpuid_bit(c); } =20 -static const struct x86_cpu_desc erratum_1386_microcode[] =3D { - AMD_CPU_DESC(0x17, 0x1, 0x2, 0x0800126e), - AMD_CPU_DESC(0x17, 0x31, 0x0, 0x08301052), - {}, +static const struct x86_cpu_id erratum_1386_microcode[] =3D { + X86_MATCH_VFM_STEPPINGS(VFM_MAKE(X86_VENDOR_AMD, 0x17, 0x01), 0x2, 0x2, 0= x0800126e), + X86_MATCH_VFM_STEPPINGS(VFM_MAKE(X86_VENDOR_AMD, 0x17, 0x31), 0x0, 0x0, 0= x08301052), }; =20 static void fix_erratum_1386(struct cpuinfo_x86 *c) @@ -814,7 +813,7 @@ static void fix_erratum_1386(struct cpui * Clear the feature flag only on microcode revisions which * don't have the fix. */ - if (x86_cpu_has_min_microcode_rev(erratum_1386_microcode)) + if (x86_match_min_microcode_rev(erratum_1386_microcode)) return; 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X-CSE-ConnectionGUID: pu0WhWQVQ4untXxqaGhDcw== X-CSE-MsgGUID: u95Dg95fTgOS487zKsTIHg== X-IronPort-AV: E=McAfee;i="6700,10204,11278"; a="34027913" X-IronPort-AV: E=Sophos;i="6.12,214,1728975600"; d="scan'208";a="34027913" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2024 11:38:38 -0800 X-CSE-ConnectionGUID: YEesrAm3Ti2Fqol5sWgfag== X-CSE-MsgGUID: 9ZwYC+M9Sj2HEEe6BMfKiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,214,1728975600"; d="scan'208";a="94979054" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa009.fm.intel.com with ESMTP; 06 Dec 2024 11:38:38 -0800 Subject: [PATCH 5/5] x86/cpu: Remove 'x86_cpu_desc' infrastructure To: linux-kernel@vger.kernel.org Cc: x86@kernel.org,tglx@linutronix.de,bp@alien8.de,kan.liang@linux.intel.com,mingo@kernel.org,peterz@infradead.org,tony.luck@intel.com,pawan.kumar.gupta@linux.intel.com,Dave Hansen From: Dave Hansen Date: Fri, 06 Dec 2024 11:38:37 -0800 References: <20241206193829.89E12D0B@davehans-spike.ostc.intel.com> In-Reply-To: <20241206193829.89E12D0B@davehans-spike.ostc.intel.com> Message-Id: <20241206193837.B3001666@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen All the users of 'x86_cpu_desc' are gone. Zap it from the tree. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/cpu_device_id.h | 35 ----------------------------= ----- b/arch/x86/kernel/cpu/match.c | 31 ----------------------------- 2 files changed, 66 deletions(-) diff -puN arch/x86/include/asm/cpu_device_id.h~zap-x86_cpu_desc-3 arch/x86/= include/asm/cpu_device_id.h --- a/arch/x86/include/asm/cpu_device_id.h~zap-x86_cpu_desc-3 2024-12-06 11= :33:17.751210312 -0800 +++ b/arch/x86/include/asm/cpu_device_id.h 2024-12-06 11:33:17.755210470 -0= 800 @@ -243,42 +243,7 @@ VFM_MODEL(vfm), \ X86_STEPPING_ANY, feature, data) =20 -/* - * Match specific microcode revisions. - * - * vendor/family/model/stepping must be all set. - * - * Only checks against the boot CPU. When mixed-stepping configs are - * valid for a CPU model, add a quirk for every valid stepping and - * do the fine-tuning in the quirk handler. - */ - -struct x86_cpu_desc { - u8 x86_family; - u8 x86_vendor; - u8 x86_model; - u8 x86_stepping; - u32 x86_microcode_rev; -}; - -#define INTEL_CPU_DESC(vfm, stepping, revision) { \ - .x86_family =3D VFM_FAMILY(vfm), \ - .x86_vendor =3D VFM_VENDOR(vfm), \ - .x86_model =3D VFM_MODEL(vfm), \ - .x86_stepping =3D (stepping), \ - .x86_microcode_rev =3D (revision), \ -} - -#define AMD_CPU_DESC(fam, model, stepping, revision) { \ - .x86_family =3D (fam), \ - .x86_vendor =3D X86_VENDOR_AMD, \ - .x86_model =3D (model), \ - .x86_stepping =3D (stepping), \ - .x86_microcode_rev =3D (revision), \ -} - extern const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id *mat= ch); -extern bool x86_cpu_has_min_microcode_rev(const struct x86_cpu_desc *table= ); extern bool x86_match_min_microcode_rev(const struct x86_cpu_id *table); =20 #endif /* _ASM_X86_CPU_DEVICE_ID */ diff -puN arch/x86/kernel/cpu/match.c~zap-x86_cpu_desc-3 arch/x86/kernel/cp= u/match.c --- a/arch/x86/kernel/cpu/match.c~zap-x86_cpu_desc-3 2024-12-06 11:33:17.75= 5210470 -0800 +++ b/arch/x86/kernel/cpu/match.c 2024-12-06 11:33:17.755210470 -0800 @@ -56,37 +56,6 @@ const struct x86_cpu_id *x86_match_cpu(c } EXPORT_SYMBOL(x86_match_cpu); =20 -static const struct x86_cpu_desc * -x86_match_cpu_with_stepping(const struct x86_cpu_desc *match) -{ - struct cpuinfo_x86 *c =3D &boot_cpu_data; - const struct x86_cpu_desc *m; - - for (m =3D match; m->x86_family | m->x86_model; m++) { - if (c->x86_vendor !=3D m->x86_vendor) - continue; - if (c->x86 !=3D m->x86_family) - continue; - if (c->x86_model !=3D m->x86_model) - continue; - if (c->x86_stepping !=3D m->x86_stepping) - continue; - return m; - } - return NULL; -} - -bool x86_cpu_has_min_microcode_rev(const struct x86_cpu_desc *table) -{ - const struct x86_cpu_desc *res =3D x86_match_cpu_with_stepping(table); - - if (!res || res->x86_microcode_rev > boot_cpu_data.microcode) - return false; - - return true; -} -EXPORT_SYMBOL_GPL(x86_cpu_has_min_microcode_rev); - bool x86_match_min_microcode_rev(const struct x86_cpu_id *table) { const struct x86_cpu_id *res =3D x86_match_cpu(table); _