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Fri, 06 Dec 2024 05:51:18 -0800 (PST) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-7fd3274ca0esm101286a12.20.2024.12.06.05.51.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Dec 2024 05:51:18 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nick Chan Subject: [PATCH] arm64: dts: apple: Split s8000/s8003 SoC DTS files Date: Fri, 6 Dec 2024 21:49:18 +0800 Message-ID: <20241206135051.56049-1-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Despite what the code comments said, the DTS files were not split properly. Since these two SoCs are now known to have minor differences like in latencies for cpufreq state transistions, split the DTS files now. Signed-off-by: Nick Chan --- Hi, I am preparing multiple series for cpufreq and backlight, both of which modifies the Apple A9 DTS files. I am sending this first to make it easier to handle conflicts. This patch depends on PMGR nodes for Apple A7-A11 SoCs[1] since it also renames the pmgr bindings files. [1]: https://lore.kernel.org/asahi/20241203050640.109378-1-towinchenmi@gmai= l.com/T Nick Chan .../{s8000-pmgr.dtsi =3D> s800-0-3-pmgr.dtsi} | 0 arch/arm64/boot/dts/apple/s800-0-3.dtsi | 162 ++++++++++++++++++ arch/arm64/boot/dts/apple/s8000.dtsi | 155 +---------------- arch/arm64/boot/dts/apple/s8003.dtsi | 10 +- 4 files changed, 168 insertions(+), 159 deletions(-) rename arch/arm64/boot/dts/apple/{s8000-pmgr.dtsi =3D> s800-0-3-pmgr.dtsi}= (100%) create mode 100644 arch/arm64/boot/dts/apple/s800-0-3.dtsi diff --git a/arch/arm64/boot/dts/apple/s8000-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/s800-0-3-pmgr.dtsi similarity index 100% rename from arch/arm64/boot/dts/apple/s8000-pmgr.dtsi rename to arch/arm64/boot/dts/apple/s800-0-3-pmgr.dtsi diff --git a/arch/arm64/boot/dts/apple/s800-0-3.dtsi b/arch/arm64/boot/dts/= apple/s800-0-3.dtsi new file mode 100644 index 000000000000..1e0b8f631ac0 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s800-0-3.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple S8000/S8003 "A9" SoC + * + * This file contains parts common to both variants of A9 + * + * Copyright (c) 2022, Konrad Dybcio + */ + +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&aic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + clkref: clock-ref { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "clkref"; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "apple,twister"; + reg =3D <0x0 0x0>; + cpu-release-addr =3D <0 0>; /* To be filled in by loader */ + enable-method =3D "spin-table"; + device_type =3D "cpu"; + }; + + cpu1: cpu@1 { + compatible =3D "apple,twister"; + reg =3D <0x0 0x1>; + cpu-release-addr =3D <0 0>; /* To be filled in by loader */ + enable-method =3D "spin-table"; + device_type =3D "cpu"; + }; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + nonposted-mmio; + ranges; + + serial0: serial@20a0c0000 { + compatible =3D "apple,s5l-uart"; + reg =3D <0x2 0x0a0c0000 0x0 0x4000>; + reg-io-width =3D <4>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + /* Use the bootloader-enabled clocks for now. */ + clocks =3D <&clkref>, <&clkref>; + clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart0>; + status =3D "disabled"; + }; + + pmgr: power-management@20e000000 { + compatible =3D "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0xe000000 0 0x8c000>; + }; + + aic: interrupt-controller@20e100000 { + compatible =3D "apple,s8000-aic", "apple,aic"; + reg =3D <0x2 0x0e100000 0x0 0x100000>; + #interrupt-cells =3D <3>; + interrupt-controller; + power-domains =3D <&ps_aic>; + }; + + pinctrl_ap: pinctrl@20f100000 { + compatible =3D "apple,s8000-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x0f100000 0x0 0x100000>; + power-domains =3D <&ps_gpio>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_ap 0 0 208>; + apple,npins =3D <208>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + }; + + pinctrl_aop: pinctrl@2100f0000 { + compatible =3D "apple,s8000-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x100f0000 0x0 0x100000>; + power-domains =3D <&ps_aop_gpio>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_aop 0 0 42>; + apple,npins =3D <42>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + }; + + pmgr_mini: power-management@210200000 { + compatible =3D "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0x10200000 0 0x84000>; + }; + + wdt: watchdog@2102b0000 { + compatible =3D "apple,s8000-wdt", "apple,wdt"; + reg =3D <0x2 0x102b0000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&aic>; + interrupt-names =3D "phys", "virt"; + /* Note that A9 doesn't actually have a hypervisor (EL2 is not implement= ed). */ + interrupts =3D , + ; + }; +}; + +#include "s800-0-3-pmgr.dtsi" + +/* + * The A9 was made by two separate fabs on two different process + * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made + * the S8003 (APL1022) on 16nm. There are some minor differences + * such as timing in cpufreq state transistions. + */ diff --git a/arch/arm64/boot/dts/apple/s8000.dtsi b/arch/arm64/boot/dts/app= le/s8000.dtsi index 84d6b4939ac4..c7e39abda7e1 100644 --- a/arch/arm64/boot/dts/apple/s8000.dtsi +++ b/arch/arm64/boot/dts/apple/s8000.dtsi @@ -7,160 +7,11 @@ * Copyright (c) 2022, Konrad Dybcio */ =20 -#include -#include -#include -#include - -/ { - interrupt-parent =3D <&aic>; - #address-cells =3D <2>; - #size-cells =3D <2>; - - clkref: clock-ref { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <24000000>; - clock-output-names =3D "clkref"; - }; - - cpus { - #address-cells =3D <2>; - #size-cells =3D <0>; - - cpu0: cpu@0 { - compatible =3D "apple,twister"; - reg =3D <0x0 0x0>; - cpu-release-addr =3D <0 0>; /* To be filled in by loader */ - enable-method =3D "spin-table"; - device_type =3D "cpu"; - }; - - cpu1: cpu@1 { - compatible =3D "apple,twister"; - reg =3D <0x0 0x1>; - cpu-release-addr =3D <0 0>; /* To be filled in by loader */ - enable-method =3D "spin-table"; - device_type =3D "cpu"; - }; - }; - - soc { - compatible =3D "simple-bus"; - #address-cells =3D <2>; - #size-cells =3D <2>; - nonposted-mmio; - ranges; - - serial0: serial@20a0c0000 { - compatible =3D "apple,s5l-uart"; - reg =3D <0x2 0x0a0c0000 0x0 0x4000>; - reg-io-width =3D <4>; - interrupt-parent =3D <&aic>; - interrupts =3D ; - /* Use the bootloader-enabled clocks for now. */ - clocks =3D <&clkref>, <&clkref>; - clock-names =3D "uart", "clk_uart_baud0"; - power-domains =3D <&ps_uart0>; - status =3D "disabled"; - }; - - pmgr: power-management@20e000000 { - compatible =3D "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - reg =3D <0x2 0xe000000 0 0x8c000>; - }; - - aic: interrupt-controller@20e100000 { - compatible =3D "apple,s8000-aic", "apple,aic"; - reg =3D <0x2 0x0e100000 0x0 0x100000>; - #interrupt-cells =3D <3>; - interrupt-controller; - power-domains =3D <&ps_aic>; - }; - - pinctrl_ap: pinctrl@20f100000 { - compatible =3D "apple,s8000-pinctrl", "apple,pinctrl"; - reg =3D <0x2 0x0f100000 0x0 0x100000>; - power-domains =3D <&ps_gpio>; - - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&pinctrl_ap 0 0 208>; - apple,npins =3D <208>; - - interrupt-controller; - #interrupt-cells =3D <2>; - interrupt-parent =3D <&aic>; - interrupts =3D , - , - , - , - , - , - ; - }; - - pinctrl_aop: pinctrl@2100f0000 { - compatible =3D "apple,s8000-pinctrl", "apple,pinctrl"; - reg =3D <0x2 0x100f0000 0x0 0x100000>; - power-domains =3D <&ps_aop_gpio>; - - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&pinctrl_aop 0 0 42>; - apple,npins =3D <42>; - - interrupt-controller; - #interrupt-cells =3D <2>; - interrupt-parent =3D <&aic>; - interrupts =3D , - , - , - , - , - , - ; - }; - - pmgr_mini: power-management@210200000 { - compatible =3D "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - reg =3D <0x2 0x10200000 0 0x84000>; - }; - - wdt: watchdog@2102b0000 { - compatible =3D "apple,s8000-wdt", "apple,wdt"; - reg =3D <0x2 0x102b0000 0x0 0x4000>; - clocks =3D <&clkref>; - interrupt-parent =3D <&aic>; - interrupts =3D ; - }; - }; - - timer { - compatible =3D "arm,armv8-timer"; - interrupt-parent =3D <&aic>; - interrupt-names =3D "phys", "virt"; - /* Note that A9 doesn't actually have a hypervisor (EL2 is not implement= ed). */ - interrupts =3D , - ; - }; -}; - -#include "s8000-pmgr.dtsi" +#include "s800-0-3.dtsi" =20 /* * The A9 was made by two separate fabs on two different process * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made - * the S8003 (APL1022) on 16nm. While they are seemingly the same, - * they do have distinct part numbers and devices using them have - * distinct model names. There are currently no known differences - * between these as far as Linux is concerned, but let's keep things - * structured properly to make it easier to alter the behaviour of - * one of the chips if need be. + * the S8003 (APL1022) on 16nm. There are some minor differences + * such as timing in cpufreq state transistions. */ diff --git a/arch/arm64/boot/dts/apple/s8003.dtsi b/arch/arm64/boot/dts/app= le/s8003.dtsi index 7e4ad4f7e499..807e3452f8a7 100644 --- a/arch/arm64/boot/dts/apple/s8003.dtsi +++ b/arch/arm64/boot/dts/apple/s8003.dtsi @@ -7,15 +7,11 @@ * Copyright (c) 2022, Konrad Dybcio */ =20 -#include "s8000.dtsi" +#include "s800-0-3.dtsi" =20 /* * The A9 was made by two separate fabs on two different process * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made - * the S8003 (APL1022) on 16nm. While they are seemingly the same, - * they do have distinct part numbers and devices using them have - * distinct model names. There are currently no known differences - * between these as far as Linux is concerned, but let's keep things - * structured properly to make it easier to alter the behaviour of - * one of the chips if need be. + * the S8003 (APL1022) on 16nm. There are some minor differences + * such as timing in cpufreq state transistions. */ base-commit: d47006c7111b57dd2377d072681935aebb9dde25 --=20 2.47.1