From nobody Fri Dec 19 08:44:37 2025 Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB2B11FBE90 for ; Fri, 6 Dec 2024 10:18:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.35 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733480302; cv=none; b=Axmi+475BzKcqjnUhiKa4biwKmRfcYnkw1HH4pDrVrYQqt7WoINAC6S/lV+UxcbdIjMy5X217jEPQ9DxmBm5SnKHYx3cIUPHbLno8RubCzQ9Vi90D/FbrjfZ6H/aF8SVOg6r5kVaAW4BPOPS58pJgyhuhRcGeSZg4vw9iNDonhM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733480302; c=relaxed/simple; bh=ZZQ57p6ylzFGJO0VHxVH8U+YK1pdsYbdIw77G6g4F8U=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Mp6lh7yPLHf7I5HmDNhMHiuUFNLZ2IgJGKx4eqxBT1uVzB16IBYYVgp7m4jIQmV2+ptq/ragpw0j26gRW86ZUSQpGKmT+GYWP+UrM/hjYtTI3y2hPOVpQX7pov//EleoKHPordJaLZ98B/O2ma+bqbPLarTrh3IChuxW9ovXsgI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.35 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.112]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4Y4Rwm0C8Qz1T4md; Fri, 6 Dec 2024 18:15:52 +0800 (CST) Received: from kwepemg200008.china.huawei.com (unknown [7.202.181.35]) by mail.maildlp.com (Postfix) with ESMTPS id EF8031401DC; Fri, 6 Dec 2024 18:18:11 +0800 (CST) Received: from huawei.com (10.90.53.73) by kwepemg200008.china.huawei.com (7.202.181.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 6 Dec 2024 18:18:10 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH -next v5 04/22] arm64: entry: Rework arm64_preempt_schedule_irq() Date: Fri, 6 Dec 2024 18:17:26 +0800 Message-ID: <20241206101744.4161990-5-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241206101744.4161990-1-ruanjinjie@huawei.com> References: <20241206101744.4161990-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemg200008.china.huawei.com (7.202.181.35) Content-Type: text/plain; charset="utf-8" The generic entry do preempt_schedule_irq() by checking if need_resched() satisfied, but arm64 has some of its own additional checks such as GIC priority masking. In preparation for moving arm64 over to the generic entry code, rework arm64_preempt_schedule_irq() to check whether it need resched in a check function called arm64_need_resched(). No functional changes. Signed-off-by: Jinjie Ruan --- arch/arm64/kernel/entry-common.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-com= mon.c index 7a588515ee07..da68c089b74b 100644 --- a/arch/arm64/kernel/entry-common.c +++ b/arch/arm64/kernel/entry-common.c @@ -83,10 +83,10 @@ DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_re= sched); #define need_irq_preemption() (IS_ENABLED(CONFIG_PREEMPTION)) #endif =20 -static void __sched arm64_preempt_schedule_irq(void) +static inline bool arm64_need_resched(void) { if (!need_irq_preemption()) - return; + return false; =20 /* * Note: thread_info::preempt_count includes both thread_info::count @@ -94,7 +94,7 @@ static void __sched arm64_preempt_schedule_irq(void) * preempt_count(). */ if (READ_ONCE(current_thread_info()->preempt_count) !=3D 0) - return; + return false; =20 /* * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC @@ -103,7 +103,7 @@ static void __sched arm64_preempt_schedule_irq(void) * DAIF we must have handled an NMI, so skip preemption. */ if (system_uses_irq_prio_masking() && read_sysreg(daif)) - return; + return false; =20 /* * Preempting a task from an IRQ means we leave copies of PSTATE @@ -113,8 +113,10 @@ static void __sched arm64_preempt_schedule_irq(void) * Only allow a task to be preempted once cpufeatures have been * enabled. */ - if (system_capabilities_finalized()) - preempt_schedule_irq(); + if (!system_capabilities_finalized()) + return false; + + return true; } =20 /* @@ -139,7 +141,8 @@ static __always_inline void __exit_to_kernel_mode(struc= t pt_regs *regs, return; } =20 - arm64_preempt_schedule_irq(); + if (arm64_need_resched()) + preempt_schedule_irq(); =20 trace_hardirqs_on(); } else { --=20 2.34.1