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Thu, 05 Dec 2024 21:59:16 -0800 (PST) From: Inochi Amaoto To: Chen Wang , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Evan Green , Charlie Jenkins , Andrew Jones , Jesse Taube , Andy Chiu , Alexandre Ghiti , Inochi Amaoto , Samuel Holland , Yong-Xuan Wang Cc: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Yixun Lan , Longbin Li , Conor Dooley Subject: [PATCH v3 1/3] dt-bindings: riscv: add bfloat16 ISA extension description Date: Fri, 6 Dec 2024 13:58:27 +0800 Message-ID: <20241206055829.1059293-2-inochiama@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241206055829.1059293-1-inochiama@gmail.com> References: <20241206055829.1059293-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add description for the BFloat16 precision Floating-Point ISA extension, (Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62 ("Added Chapter title to BF16") of the riscv-isa-manual. Signed-off-by: Inochi Amaoto Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 9c7dd7e75e0c..0a1f1a76d129 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -329,6 +329,12 @@ properties: instructions, as ratified in commit 056b6ff ("Zfa is ratified"= ) of riscv-isa-manual. =20 + - const: zfbfmin + description: + The standard Zfbfmin extension which provides minimal support = for + 16-bit half-precision brain floating-point instructions, as ra= tified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-is= a-manual. + - const: zfh description: The standard Zfh extension for 16-bit half-precision binary @@ -525,6 +531,18 @@ properties: in commit 6f702a2 ("Vector extensions are now ratified") of riscv-v-spec. =20 + - const: zvfbfmin + description: + The standard Zvfbfmin extension for minimal support for vector= ed + 16-bit half-precision brain floating-point instructions, as ra= tified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-is= a-manual. + + - const: zvfbfwma + description: + The standard Zvfbfwma extension for vectored half-precision br= ain + floating-point widening multiply-accumulate instructions, as r= atified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-is= a-manual. + - const: zvfh description: The standard Zvfh extension for vectored half-precision @@ -663,6 +681,33 @@ properties: then: contains: const: zca + # Zfbfmin depends on F + - if: + contains: + const: zfbfmin + then: + contains: + const: f + # Zvfbfmin depends on V or Zve32f + - if: + contains: + const: zvfbfmin + then: + oneOf: + - contains: + const: v + - contains: + const: zve32f + # Zvfbfwma depends on Zfbfmin and Zvfbfmin + - if: + contains: + const: zvfbfwma + then: + allOf: + - contains: + const: zfbfmin + - contains: + const: zvfbfmin =20 allOf: # Zcf extension does not exist on rv64 --=20 2.47.1