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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2024 05:17:38.9939 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c8ffb0e2-7f80-4364-bd76-08dd15b54d8d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7661 Content-Type: text/plain; charset="utf-8" Definition of these macros are very simple and they are used at only one place. Get rid of unnecessary redirection. Acked-by: Namhyung Kim Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index f02939655b2a..26dd5e5874f9 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -28,10 +28,6 @@ static u32 ibs_caps; #include #include =20 -#define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT) -#define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT - - /* * IBS states: * @@ -670,7 +666,7 @@ static struct perf_ibs perf_ibs_fetch =3D { .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSFETCHCTL, - .config_mask =3D IBS_FETCH_CONFIG_MASK, + .config_mask =3D IBS_FETCH_MAX_CNT | IBS_FETCH_RAND_EN, .cnt_mask =3D IBS_FETCH_MAX_CNT, .enable_mask =3D IBS_FETCH_ENABLE, .valid_mask =3D IBS_FETCH_VAL, @@ -694,7 +690,7 @@ static struct perf_ibs perf_ibs_op =3D { .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSOPCTL, - .config_mask =3D IBS_OP_CONFIG_MASK, + .config_mask =3D IBS_OP_MAX_CNT, .cnt_mask =3D IBS_OP_MAX_CNT | IBS_OP_CUR_CNT | IBS_OP_CUR_CNT_RAND, .enable_mask =3D IBS_OP_ENABLE, --=20 2.47.0 From nobody Thu Dec 18 00:09:41 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2050.outbound.protection.outlook.com [40.107.92.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 322AC196C67; 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Thu, 5 Dec 2024 23:17:38 -0600 From: Ravi Bangoria To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 02/10] perf/amd/ibs: Remove pointless sample period check Date: Fri, 6 Dec 2024 05:17:05 +0000 Message-ID: <20241206051713.991-3-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241206051713.991-1-ravi.bangoria@amd.com> References: <20241206051713.991-1-ravi.bangoria@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CC:EE_|CY8PR12MB8067:EE_ X-MS-Office365-Filtering-Correlation-Id: 2f4e45ae-e01a-41bd-b3b4-08dd15b5512d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|7416014|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2024 05:17:45.0129 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2f4e45ae-e01a-41bd-b3b4-08dd15b5512d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8067 Content-Type: text/plain; charset="utf-8" Valid perf event sample period value for IBS PMUs (Fetch and Op both) is limited to multiple of 0x10. perf_ibs_init() has this check: if (!event->attr.sample_freq && hwc->sample_period & 0x0f) return -EINVAL; But it's broken since hwc->sample_period will always be 0 when event->attr.sample_freq is 0 (irrespective of event->attr.freq value.) One option to fix this is to change the condition: - if (!event->attr.sample_freq && hwc->sample_period & 0x0f) + if (!event->attr.freq && hwc->sample_period & 0x0f) However, that will break all userspace tools which have been using IBS event with sample_period not multiple of 0x10. Another option is to remove the condition altogether and mask lower nibble _silently_, same as what current code is inadvertently doing. I'm preferring this approach as it keeps the existing behavior. Acked-by: Namhyung Kim Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 26dd5e5874f9..484606a9bf6b 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -294,13 +294,8 @@ static int perf_ibs_init(struct perf_event *event) if (config & perf_ibs->cnt_mask) /* raw max_cnt may not be set */ return -EINVAL; - if (!event->attr.sample_freq && hwc->sample_period & 0x0f) - /* - * lower 4 bits can not be set in ibs max cnt, - * but allowing it in case we adjust the - * sample period to set a frequency. - */ - return -EINVAL; + + /* Silently mask off lower nibble. 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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001CC.mail.protection.outlook.com (10.167.242.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8230.7 via Frontend Transport; Fri, 6 Dec 2024 05:17:50 +0000 Received: from BLR-L-RBANGORI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 5 Dec 2024 23:17:44 -0600 From: Ravi Bangoria To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 03/10] perf/amd/ibs: Fix ->config to sample period calculation for OP pmu Date: Fri, 6 Dec 2024 05:17:06 +0000 Message-ID: <20241206051713.991-4-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241206051713.991-1-ravi.bangoria@amd.com> References: <20241206051713.991-1-ravi.bangoria@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CC:EE_|DS7PR12MB6239:EE_ X-MS-Office365-Filtering-Correlation-Id: adb10e14-d604-4252-dca1-08dd15b55461 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|7416014|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2024 05:17:50.3879 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: adb10e14-d604-4252-dca1-08dd15b55461 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6239 Content-Type: text/plain; charset="utf-8" Instead of using standard perf_event_attr->freq=3D0 and ->sample_period fields, IBS event in 'sample period mode' can also be opened by setting period value directly in perf_event_attr->config in a MaxCnt bit-field format. IBS OP MaxCnt bits are defined as: (high bits) IbsOpCtl[26:20] =3D IbsOpMaxCnt[26:20] (low bits) IbsOpCtl[15:0] =3D IbsOpMaxCnt[19:4] Perf event sample period can be derived from MaxCnt bits as: sample_period =3D (high bits) | ((low_bits) << 4); However, current code just masks MaxCnt bits and shifts all of them, including high bits, which is incorrect. Fix it. Acked-by: Namhyung Kim Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 484606a9bf6b..63e1c1c11727 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -268,7 +268,7 @@ static int perf_ibs_init(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; struct perf_ibs *perf_ibs; - u64 max_cnt, config; + u64 config; int ret; =20 perf_ibs =3D get_ibs_pmu(event->attr.type); @@ -300,10 +300,19 @@ static int perf_ibs_init(struct perf_event *event) if (!hwc->sample_period) hwc->sample_period =3D 0x10; } else { - max_cnt =3D config & perf_ibs->cnt_mask; + u64 period =3D 0; + + if (perf_ibs =3D=3D &perf_ibs_op) { + period =3D (config & IBS_OP_MAX_CNT) << 4; + if (ibs_caps & IBS_CAPS_OPCNTEXT) + period |=3D config & IBS_OP_MAX_CNT_EXT_MASK; + } else { + period =3D (config & IBS_FETCH_MAX_CNT) << 4; + } + config &=3D ~perf_ibs->cnt_mask; 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X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?NSWEVPRzQHgQtiG1fzEz3Ay81bigoFybJR5L3hp2DO0jFhltSaGthyZS3RfE?= =?us-ascii?Q?XH7BghuczJjFJXIvvGoSY2QEVfR+HNYgRjTKL3Os83UnxVP8dDM4bkt/8EB0?= =?us-ascii?Q?k/Z/dj9T8txA05CBIFMiHvq0BB8eHnXOAFdbofHMd+176plOHmVyF9J+mUOO?= =?us-ascii?Q?LAW8h1UX4H1eazF5TV1kFmcwEzuzMB8JhCTX6R4Hhl0eQR4kpQ7zsUguQn4p?= =?us-ascii?Q?4j/HJmKTQUCaRogZee0AahGtsrwku10atbsbRbV/ttpU2jzKHk/0EzKsULHw?= =?us-ascii?Q?ZmuuELOCGu7YazyJy5U0uB+AOSkkoMgM4RLOOMg1qvjXvJQVkYaCaXMniVXH?= =?us-ascii?Q?7UeQU1yaElJ4RSv4lc8BD1nE2Y9+MICsUb8lPTn586ammEOeyDb1DtHNb5h+?= =?us-ascii?Q?usaVXxr4ARfm1xgZT0adPDr2cUr7I69uFk7x5LIPXM0jsD1bRNGz4BB+xkCl?= =?us-ascii?Q?UFIW1u2+/3JNUsCy416+ydAPqGXVGxkkPfMfxQRf/Z6TCgxuSaGioMQme2Yu?= =?us-ascii?Q?7uYKkEkJARUhAqrtWRDjt93F1EIzGHtmI6+6/aB7T3Mv13KfuHsQxX0LWi0S?= =?us-ascii?Q?u8vPtNWdRmvV4s9EyFDotRze+2cqM2bfs0K74KJDtTppw5ydZJ75un9coYlN?= =?us-ascii?Q?rHU9L4HAeTIc1GPLGcWfCtmk24Gh7bsUDV9BBHBFvU0UGhjT8XEj+EbtGoy7?= =?us-ascii?Q?ADT7CZjwjuLg38WkpBf7EN1nXMFLXD9HosqWZNDly0gYtCjGU9BDNiPQMki3?= =?us-ascii?Q?/2Uk3++zR17zXtGn3bm5OeTPLFuhGoCmEtGmfb5/EkhEDzIKuz6XsQauZugn?= =?us-ascii?Q?OpuU9L3yeZVQal+KQ1kpVh2R/giWzQ7rxsMX6YEihDu9o5PRnalikBUSXaol?= =?us-ascii?Q?cHZjFMlP9oBK+zsFTMEJ53dTYC0aSTDR4SHwIZ9awZfVTtzSeEibSE8gPA3f?= =?us-ascii?Q?NSJPEk4dKPqiM+PByoO1cTLkhkK6hJAl5GpO3jJQ9zw7/fX8woz+//4EfSMq?= =?us-ascii?Q?TLjAZJwDvf0jY1MsGnm/+vSGQv52m3IPs7xNtHLOzqLGmXvOGqWeVBEoW4uR?= =?us-ascii?Q?qz31HBY4IqsMtbE7D2QwUvjGj7xIvP8ZU4HeOAnxc7M6XnIPBnxBnRoYG2eT?= =?us-ascii?Q?LYSN7HT+/HSvIW3EW1tv3qJyG2O0zcWbFw0EEi2wbG8pZLv480Gz4ADOgWWx?= =?us-ascii?Q?OYV+VFydyF3yQaLhPnSetla2zvR61rHge4T0CpsTaeEwNwGHWHYZ5sZMpxdO?= =?us-ascii?Q?bLUjhppUIj+5iieeAqzXFyceWjVK1QV05922cg7SxaZh9SyprOjHekQ4AyDV?= =?us-ascii?Q?L2jyVCxfb1IZzL9j5iVaQLcF03Cy4YCy58FZj3IGpt5cOll0Cv7J3pn+a5qH?= =?us-ascii?Q?4SG3yIgnPzisUxnG+TRoodw9MHRyCX6OwYQZaDHb5ze6MfL9xTN9jeLVv9DQ?= =?us-ascii?Q?wfrbeX9Bxb8MZtnYlEgYX9j1rthSdvUw?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2024 05:17:56.2160 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7aa98b0a-c6a3-4855-2a12-08dd15b557db X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7254 Content-Type: text/plain; charset="utf-8" IBS Op uses two counters: MaxCnt and CurCnt. MaxCnt is programmed with the desired sample period. IBS hw generates sample when CurCnt reaches to MaxCnt. The size of these counter used to be 20 bits but later they were extended to 27 bits. The 7 bit extension is indicated by CPUID Fn8000_001B_EAX[6 / OpCntExt]. perf_ibs->cnt_mask variable contains bit masks for MaxCnt and CurCnt. But IBS driver does not set upper 7 bits of CurCnt in cnt_mask even when OpCntExt CPUID bit is set. Fix this. IBS driver uses cnt_mask[CurCnt] bits only while disabling an event. Fortunately, CurCnt bits are not read from MSR while re-enabling the event, instead MaxCnt is programmed with desired period and CurCnt is set to 0. Hence, we did not see any issues so far. Acked-by: Namhyung Kim Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 3 ++- arch/x86/include/asm/perf_event.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 63e1c1c11727..11123c174a3b 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1221,7 +1221,8 @@ static __init int perf_ibs_op_init(void) if (ibs_caps & IBS_CAPS_OPCNTEXT) { perf_ibs_op.max_period |=3D IBS_OP_MAX_CNT_EXT_MASK; perf_ibs_op.config_mask |=3D IBS_OP_MAX_CNT_EXT_MASK; - perf_ibs_op.cnt_mask |=3D IBS_OP_MAX_CNT_EXT_MASK; + perf_ibs_op.cnt_mask |=3D (IBS_OP_MAX_CNT_EXT_MASK | + IBS_OP_CUR_CNT_EXT_MASK); } =20 if (ibs_caps & IBS_CAPS_ZEN4) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index cb9c4679f45c..aff9fc693b11 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -510,6 +510,7 @@ struct pebs_xmm { */ #define IBS_OP_CUR_CNT (0xFFF80ULL<<32) #define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32) +#define IBS_OP_CUR_CNT_EXT_MASK (0x7FULL<<52) #define IBS_OP_CNT_CTL (1ULL<<19) #define IBS_OP_VAL (1ULL<<18) #define IBS_OP_ENABLE (1ULL<<17) --=20 2.47.0 From nobody Thu Dec 18 00:09:41 2025 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2066.outbound.protection.outlook.com [40.107.220.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CE981957E7; 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Thu, 5 Dec 2024 23:17:55 -0600 From: Ravi Bangoria To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 05/10] perf/amd/ibs: Don't allow freq mode event creation through ->config interface Date: Fri, 6 Dec 2024 05:17:08 +0000 Message-ID: <20241206051713.991-6-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241206051713.991-1-ravi.bangoria@amd.com> References: <20241206051713.991-1-ravi.bangoria@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CD:EE_|PH7PR12MB6611:EE_ X-MS-Office365-Filtering-Correlation-Id: ebc42b38-0744-4abd-1ef3-08dd15b56229 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2024 05:18:13.5041 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ebc42b38-0744-4abd-1ef3-08dd15b56229 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CD.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6611 Content-Type: text/plain; charset="utf-8" Most perf_event_attr->config bits directly maps to IBS_{FETCH|OP}_CTL MSR. Since the sample period is programmed in these control registers, IBS PMU driver allows opening an IBS event by setting sample period value directly in perf_event_attr->config instead of using explicit perf_event_attr->sample_period interface. However, this logic is not applicable for freq mode events since the semantics of control register fields are applicable only to fixed sample period whereas the freq mode event adjusts sample period after each and every sample. Currently, IBS driver (unintentionally) allows creating freq mode event via ->config interface, which is semantically wrong as well as detrimental because it can be misused to bypass perf_event_max_sample_rate checks. Don't allow freq mode event creation through perf_event_attr->config interface. Acked-by: Namhyung Kim Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 11123c174a3b..a687ffb09905 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -302,6 +302,9 @@ static int perf_ibs_init(struct perf_event *event) } else { u64 period =3D 0; =20 + if (event->attr.freq) + return -EINVAL; + if (perf_ibs =3D=3D &perf_ibs_op) { period =3D (config & IBS_OP_MAX_CNT) << 4; if (ibs_caps & IBS_CAPS_OPCNTEXT) --=20 2.47.0 From nobody Thu Dec 18 00:09:41 2025 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2056.outbound.protection.outlook.com [40.107.102.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73C991946DF; Fri, 6 Dec 2024 05:18:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.102.56 ARC-Seal: i=2; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2024 05:18:18.2229 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b60babd-eb4e-4b5c-259e-08dd15b564f9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CD.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6928 Content-Type: text/plain; charset="utf-8" 0x10 is the minimum sample period for IBS Fetch and 0x90 for IBS Op. Current IBS pmu driver uses 0x10 for both the pmus, which is incorrect. Fix it by adding pmu specific minimum period values in struct perf_ibs. Also, bail out opening a 'sample period mode' event if the user requested sample period is less than pmu supported minimum value. For a 'freq mode' event, start calibrating sample period from pmu specific minimum period. Acked-by: Namhyung Kim Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index a687ffb09905..cc58ef4d8de3 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -83,6 +83,7 @@ struct perf_ibs { u64 cnt_mask; u64 enable_mask; u64 valid_mask; + u16 min_period; u64 max_period; unsigned long offset_mask[1]; int offset_max; @@ -295,10 +296,14 @@ static int perf_ibs_init(struct perf_event *event) /* raw max_cnt may not be set */ return -EINVAL; =20 - /* Silently mask off lower nibble. IBS hw mandates it. */ - hwc->sample_period &=3D ~0x0FULL; - if (!hwc->sample_period) - hwc->sample_period =3D 0x10; + if (event->attr.freq) { + hwc->sample_period =3D perf_ibs->min_period; + } else { + /* Silently mask off lower nibble. IBS hw mandates it. */ + hwc->sample_period &=3D ~0x0FULL; + if (hwc->sample_period < perf_ibs->min_period) + return -EINVAL; + } } else { u64 period =3D 0; =20 @@ -316,10 +321,10 @@ static int perf_ibs_init(struct perf_event *event) config &=3D ~perf_ibs->cnt_mask; event->attr.sample_period =3D period; hwc->sample_period =3D period; - } =20 - if (!hwc->sample_period) - return -EINVAL; + if (hwc->sample_period < perf_ibs->min_period) + return -EINVAL; + } =20 /* * If we modify hwc->sample_period, we also need to update @@ -340,7 +345,8 @@ static int perf_ibs_set_period(struct perf_ibs *perf_ib= s, int overflow; =20 /* ignore lower 4 bits in min count: */ - overflow =3D perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, perio= d); + overflow =3D perf_event_set_period(hwc, perf_ibs->min_period, + perf_ibs->max_period, period); local64_set(&hwc->prev_count, 0); =20 return overflow; @@ -677,6 +683,7 @@ static struct perf_ibs perf_ibs_fetch =3D { .cnt_mask =3D IBS_FETCH_MAX_CNT, .enable_mask =3D IBS_FETCH_ENABLE, .valid_mask =3D IBS_FETCH_VAL, + .min_period =3D 0x10, .max_period =3D IBS_FETCH_MAX_CNT << 4, .offset_mask =3D { MSR_AMD64_IBSFETCH_REG_MASK }, .offset_max =3D MSR_AMD64_IBSFETCH_REG_COUNT, @@ -702,6 +709,7 @@ static struct perf_ibs perf_ibs_op =3D { IBS_OP_CUR_CNT_RAND, .enable_mask =3D IBS_OP_ENABLE, .valid_mask =3D IBS_OP_VAL, + .min_period =3D 0x90, .max_period =3D IBS_OP_MAX_CNT << 4, .offset_mask =3D { MSR_AMD64_IBSOP_REG_MASK }, .offset_max =3D MSR_AMD64_IBSOP_REG_COUNT, --=20 2.47.0 From nobody Thu Dec 18 00:09:41 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2084.outbound.protection.outlook.com [40.107.92.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36D4F193438; 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Thu, 5 Dec 2024 23:18:17 -0600 From: Ravi Bangoria To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 07/10] perf/amd/ibs: Add ->check_period() callback Date: Fri, 6 Dec 2024 05:17:10 +0000 Message-ID: <20241206051713.991-8-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241206051713.991-1-ravi.bangoria@amd.com> References: <20241206051713.991-1-ravi.bangoria@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CE:EE_|PH8PR12MB6868:EE_ X-MS-Office365-Filtering-Correlation-Id: 91189fc0-668c-45e8-6c06-08dd15b56867 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014|7416014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2024 05:18:23.9788 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 91189fc0-668c-45e8-6c06-08dd15b56867 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6868 Content-Type: text/plain; charset="utf-8" IBS Fetch and IBS Op pmus have constraints on sample period. The sample period is verified at the time of opening an event but not at the ioctl() interface. Hence, a user can open an event with valid period but change it later with ioctl(). Add a ->check_period() callback to verify the period provided at ioctl() is also valid. Acked-by: Namhyung Kim Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index cc58ef4d8de3..54a434722c79 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -551,6 +551,28 @@ static void perf_ibs_del(struct perf_event *event, int= flags) =20 static void perf_ibs_read(struct perf_event *event) { } =20 +static int perf_ibs_check_period(struct perf_event *event, u64 value) +{ + struct perf_ibs *perf_ibs; + u64 low_nibble; + + if (event->attr.freq) + return 0; + + perf_ibs =3D container_of(event->pmu, struct perf_ibs, pmu); + low_nibble =3D value & 0xFULL; + + /* + * This contradicts with perf_ibs_init() which allows sample period + * with lower nibble bits set but silently masks them off. Whereas + * this returns error. + */ + if (low_nibble || value < perf_ibs->min_period) + return -EINVAL; + + return 0; +} + /* * We need to initialize with empty group if all attributes in the * group are dynamic. @@ -676,6 +698,7 @@ static struct perf_ibs perf_ibs_fetch =3D { .start =3D perf_ibs_start, .stop =3D perf_ibs_stop, .read =3D perf_ibs_read, + .check_period =3D perf_ibs_check_period, .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSFETCHCTL, @@ -701,6 +724,7 @@ static struct perf_ibs perf_ibs_op =3D { .start =3D perf_ibs_start, .stop =3D perf_ibs_stop, .read =3D perf_ibs_read, + .check_period =3D perf_ibs_check_period, .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSOPCTL, --=20 2.47.0 From nobody Thu Dec 18 00:09:41 2025 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2048.outbound.protection.outlook.com [40.107.93.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76ACF1D5CE3; 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Thu, 5 Dec 2024 23:18:23 -0600 From: Ravi Bangoria To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 08/10] perf/core: Introduce pmu->adjust_period() callback Date: Fri, 6 Dec 2024 05:17:11 +0000 Message-ID: <20241206051713.991-9-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241206051713.991-1-ravi.bangoria@amd.com> References: <20241206051713.991-1-ravi.bangoria@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001C8:EE_|SJ2PR12MB9115:EE_ X-MS-Office365-Filtering-Correlation-Id: 9b74c856-5d06-49bd-f87b-08dd15b56bb2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|1800799024|376014|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2024 05:18:29.5070 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9b74c856-5d06-49bd-f87b-08dd15b56bb2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001C8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9115 Content-Type: text/plain; charset="utf-8" Many hardware pmus have constraints about sample period. For ex, minimum supported sample period for IBS Op pmu is 0x90, the sample period must be multiple of 0x10 for IBS Fetch and IBS Op. Add an optional callback adjust_period() to struct pmu to allow pmu specific drivers to adjust sample period calculated by generic code. This will ensure the sample_period value will always be valid and no additional code is required in PMU specific drivers to re-adjust the period. Acked-by: Namhyung Kim Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 11 +++++++++++ include/linux/perf_event.h | 5 +++++ kernel/events/core.c | 12 ++++++++++-- 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 54a434722c79..e41f83989b4e 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -573,6 +573,15 @@ static int perf_ibs_check_period(struct perf_event *ev= ent, u64 value) return 0; } =20 +static u64 perf_ibs_adjust_period(struct perf_event *event, u64 period) +{ + struct perf_ibs *perf_ibs =3D container_of(event->pmu, struct perf_ibs, p= mu); + + period &=3D ~0xFULL; + + return period < perf_ibs->min_period ? perf_ibs->min_period : period; +} + /* * We need to initialize with empty group if all attributes in the * group are dynamic. @@ -699,6 +708,7 @@ static struct perf_ibs perf_ibs_fetch =3D { .stop =3D perf_ibs_stop, .read =3D perf_ibs_read, .check_period =3D perf_ibs_check_period, + .adjust_period =3D perf_ibs_adjust_period, .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSFETCHCTL, @@ -725,6 +735,7 @@ static struct perf_ibs perf_ibs_op =3D { .stop =3D perf_ibs_stop, .read =3D perf_ibs_read, .check_period =3D perf_ibs_check_period, + .adjust_period =3D perf_ibs_adjust_period, .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSOPCTL, diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index bf831b1485ff..d588d3dda492 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -582,6 +582,11 @@ struct pmu { * Check period value for PERF_EVENT_IOC_PERIOD ioctl. */ int (*check_period) (struct perf_event *event, u64 value); /* optional */ + + /* + * Adjust period value according to pmu constraints. + */ + u64 (*adjust_period) (struct perf_event *event, u64 period); /* optional= */ }; =20 enum perf_addr_filter_action_t { diff --git a/kernel/events/core.c b/kernel/events/core.c index 4c6f6c286b2d..6858f8d9b16c 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -4192,9 +4192,9 @@ static void perf_adjust_period(struct perf_event *eve= nt, u64 nsec, u64 count, bo if (!sample_period) sample_period =3D 1; =20 - hwc->sample_period =3D sample_period; + hwc->sample_period =3D event->pmu->adjust_period(event, sample_period); =20 - if (local64_read(&hwc->period_left) > 8*sample_period) { + if (local64_read(&hwc->period_left) > 8*hwc->sample_period) { if (disable) event->pmu->stop(event, PERF_EF_UPDATE); =20 @@ -11562,6 +11562,11 @@ static int perf_event_nop_int(struct perf_event *e= vent, u64 value) return 0; } =20 +static u64 perf_pmu_nop_adjust_period(struct perf_event *event, u64 period) +{ + return period; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2024 05:18:35.4133 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1cfec2fc-4ef3-4712-326c-08dd15b56f38 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001C8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8507 Content-Type: text/plain; charset="utf-8" A variant of DEFINE_SUITE() but sets ->exclusive bit for the test so the test will be executed sequentially. Signed-off-by: Ravi Bangoria --- tools/perf/tests/tests.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/perf/tests/tests.h b/tools/perf/tests/tests.h index cb58b43aa063..8aea344536b8 100644 --- a/tools/perf/tests/tests.h +++ b/tools/perf/tests/tests.h @@ -81,6 +81,16 @@ struct test_suite { .test_cases =3D tests__##_name, \ } =20 +#define DEFINE_SUITE_EXCLUSIVE(description, _name) \ + struct test_case tests__##_name[] =3D { \ + TEST_CASE_EXCLUSIVE(description, _name),\ + { .name =3D NULL, } \ + }; \ + struct test_suite suite__##_name =3D { \ + .desc =3D description, \ + .test_cases =3D tests__##_name, \ + } + /* Tests */ DECLARE_SUITE(vmlinux_matches_kallsyms); DECLARE_SUITE(openat_syscall_event); --=20 2.47.0 From nobody Thu Dec 18 00:09:41 2025 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2082.outbound.protection.outlook.com [40.107.236.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E25DE19F115; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2024 05:18:41.5102 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b4a7f343-3eba-4fe0-81ee-08dd15b572da X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7499 Content-Type: text/plain; charset="utf-8" IBS Fetch and IBS Op pmus has various constraints on supported sample periods. Add perf unit tests to test those. Running it in parallel with other tests causes intermittent failures. Mark it exclusive to force it to run sequentially. Signed-off-by: Ravi Bangoria --- tools/perf/arch/x86/include/arch-tests.h | 1 + tools/perf/arch/x86/tests/Build | 1 + tools/perf/arch/x86/tests/amd-ibs-period.c | 953 +++++++++++++++++++++ tools/perf/arch/x86/tests/arch-tests.c | 2 + 4 files changed, 957 insertions(+) create mode 100644 tools/perf/arch/x86/tests/amd-ibs-period.c diff --git a/tools/perf/arch/x86/include/arch-tests.h b/tools/perf/arch/x86= /include/arch-tests.h index c0421a26b875..4fd425157d7d 100644 --- a/tools/perf/arch/x86/include/arch-tests.h +++ b/tools/perf/arch/x86/include/arch-tests.h @@ -14,6 +14,7 @@ int test__intel_pt_hybrid_compat(struct test_suite *test,= int subtest); int test__bp_modify(struct test_suite *test, int subtest); int test__x86_sample_parsing(struct test_suite *test, int subtest); int test__amd_ibs_via_core_pmu(struct test_suite *test, int subtest); +int test__amd_ibs_period(struct test_suite *test, int subtest); int test__hybrid(struct test_suite *test, int subtest); =20 extern struct test_suite *arch_tests[]; diff --git a/tools/perf/arch/x86/tests/Build b/tools/perf/arch/x86/tests/Bu= ild index 3227053f3355..db4b7945fc40 100644 --- a/tools/perf/arch/x86/tests/Build +++ b/tools/perf/arch/x86/tests/Build @@ -10,6 +10,7 @@ perf-test-$(CONFIG_AUXTRACE) +=3D insn-x86.o endif perf-test-$(CONFIG_X86_64) +=3D bp-modify.o perf-test-y +=3D amd-ibs-via-core-pmu.o +perf-test-y +=3D amd-ibs-period.o =20 ifdef SHELLCHECK SHELL_TESTS :=3D gen-insn-x86-dat.sh diff --git a/tools/perf/arch/x86/tests/amd-ibs-period.c b/tools/perf/arch/x= 86/tests/amd-ibs-period.c new file mode 100644 index 000000000000..9d208df1917a --- /dev/null +++ b/tools/perf/arch/x86/tests/amd-ibs-period.c @@ -0,0 +1,953 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include + +#include "arch-tests.h" +#include "linux/perf_event.h" +#include "linux/zalloc.h" +#include "tests/tests.h" +#include "../perf-sys.h" +#include "pmu.h" +#include "pmus.h" +#include "debug.h" +#include "util.h" +#include "strbuf.h" +#include "../util/env.h" + +#define PAGE_SIZE sysconf(_SC_PAGESIZE) + +#define PERF_MMAP_DATA_PAGES 32L +#define PERF_MMAP_DATA_SIZE (PERF_MMAP_DATA_PAGES * PAGE_SIZE) +#define PERF_MMAP_DATA_MASK (PERF_MMAP_DATA_SIZE - 1) +#define PERF_MMAP_TOTAL_PAGES (PERF_MMAP_DATA_PAGES + 1) +#define PERF_MMAP_TOTAL_SIZE (PERF_MMAP_TOTAL_PAGES * PAGE_SIZE) + +#define rmb() asm volatile("lfence":::"memory") + +enum { + FD_ERROR, + FD_SUCCESS, +}; + +enum { + IBS_FETCH, + IBS_OP, +}; + +struct perf_pmu *fetch_pmu; +struct perf_pmu *op_pmu; +unsigned int perf_event_max_sample_rate; + +/* Dummy workload to generate IBS samples. */ +static int dummy_workload_1(unsigned long count) +{ + int (*func)(void); + int ret =3D 0; + char *p; + char insn1[] =3D { + 0xb8, 0x01, 0x00, 0x00, 0x00, /* mov 1,%eax */ + 0xc3, /* ret */ + 0xcc, /* int 3 */ + }; + + char insn2[] =3D { + 0xb8, 0x02, 0x00, 0x00, 0x00, /* mov 2,%eax */ + 0xc3, /* ret */ + 0xcc, /* int 3 */ + }; + + p =3D zalloc(2 * PAGE_SIZE); + if (!p) { + printf("malloc() failed. %m"); + return 1; + } + + func =3D (void *)((unsigned long)(p + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1)); + + ret =3D mprotect(func, PAGE_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC); + if (ret) { + printf("mprotect() failed. %m"); + goto out; + } + + if (count < 100000) + count =3D 100000; + else if (count > 1000000) + count =3D 1000000; + while (count--) { + memcpy(func, insn1, sizeof(insn1)); + if (func() !=3D 1) { + pr_debug("ERROR insn1\n"); + ret =3D -1; + goto out; + } + memcpy(func, insn2, sizeof(insn2)); + if (func() !=3D 2) { + pr_debug("ERROR insn2\n"); + ret =3D -1; + goto out; + } + } + +out: + free(p); + return ret; +} + +/* Another dummy workload to generate IBS samples. */ +static void dummy_workload_2(char *perf) +{ + char bench[] =3D " bench sched messaging -g 10 -l 5000 > /dev/null 2>&1"; + char taskset[] =3D "taskset -c 0 "; + int ret __maybe_unused; + struct strbuf sb; + char *cmd; + + strbuf_init(&sb, 0); + strbuf_add(&sb, taskset, strlen(taskset)); + strbuf_add(&sb, perf, strlen(perf)); + strbuf_add(&sb, bench, strlen(bench)); + cmd =3D strbuf_detach(&sb, NULL); + ret =3D system(cmd); + free(cmd); +} + +static int sched_affine(int cpu) +{ + cpu_set_t set; + + CPU_ZERO(&set); + CPU_SET(cpu, &set); + if (sched_setaffinity(getpid(), sizeof(set), &set) =3D=3D -1) { + pr_debug("sched_setaffinity() failed. [%m]"); + return -1; + } + return 0; +} + +static void +copy_sample_data(void *src, unsigned long offset, void *dest, size_t size) +{ + size_t chunk1_size, chunk2_size; + + if ((offset + size) < (size_t)PERF_MMAP_DATA_SIZE) { + memcpy(dest, src + offset, size); + } else { + chunk1_size =3D PERF_MMAP_DATA_SIZE - offset; + chunk2_size =3D size - chunk1_size; + + memcpy(dest, src + offset, chunk1_size); + memcpy(dest + chunk1_size, src, chunk2_size); + } +} + +static int rb_read(struct perf_event_mmap_page *rb, void *dest, size_t siz= e) +{ + void *base; + unsigned long data_tail, data_head; + + /* Casting to (void *) is needed. */ + base =3D (void *)rb + PAGE_SIZE; + + data_head =3D rb->data_head; + rmb(); + data_tail =3D rb->data_tail; + + if ((data_head - data_tail) < size) + return -1; + + data_tail &=3D PERF_MMAP_DATA_MASK; + copy_sample_data(base, data_tail, dest, size); + rb->data_tail +=3D size; + return 0; +} + +static void rb_skip(struct perf_event_mmap_page *rb, size_t size) +{ + size_t data_head =3D rb->data_head; + + rmb(); + + if ((rb->data_tail + size) > data_head) + rb->data_tail =3D data_head; + else + rb->data_tail +=3D size; +} + +/* Sample period value taken from perf sample must match with expected val= ue. */ +static int period_equal(unsigned long exp_period, unsigned long act_period) +{ + return exp_period =3D=3D act_period ? 0 : -1; +} + +/* + * Sample period value taken from perf sample must be >=3D minimum sample = period + * supported by IBS HW. + */ +static int period_higher(unsigned long min_period, unsigned long act_perio= d) +{ + return min_period <=3D act_period ? 0 : -1; +} + +static int rb_drain_samples(struct perf_event_mmap_page *rb, + unsigned long exp_period, + int *nr_samples, + int (*callback)(unsigned long, unsigned long)) +{ + struct perf_event_header hdr; + unsigned long period; + int ret =3D 0; + + /* + * PERF_RECORD_SAMPLE: + * struct { + * struct perf_event_header hdr; + * { u64 period; } && PERF_SAMPLE_PERIOD + * }; + */ + while (1) { + if (rb_read(rb, &hdr, sizeof(hdr))) + return ret; + + if (hdr.type =3D=3D PERF_RECORD_SAMPLE) { + (*nr_samples)++; + period =3D 0; + if (rb_read(rb, &period, sizeof(period))) + pr_debug("rb_read(period) error. [%m]"); + ret |=3D callback(exp_period, period); + } else { + rb_skip(rb, hdr.size - sizeof(hdr)); + } + } + return ret; +} + +static long perf_event_open(struct perf_event_attr *attr, pid_t pid, + int cpu, int group_fd, unsigned long flags) +{ + return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags); +} + +static void fetch_prepare_attr(struct perf_event_attr *attr, + unsigned long config, int freq, + unsigned long sample_period) +{ + memset(attr, 0, sizeof(struct perf_event_attr)); + + attr->type =3D fetch_pmu->type; + attr->size =3D sizeof(struct perf_event_attr); + attr->config =3D config; + attr->disabled =3D 1; + attr->sample_type =3D PERF_SAMPLE_PERIOD; + attr->freq =3D freq; + attr->sample_period =3D sample_period; /* =3D ->sample_freq */ +} + +static void op_prepare_attr(struct perf_event_attr *attr, + unsigned long config, int freq, + unsigned long sample_period) +{ + memset(attr, 0, sizeof(struct perf_event_attr)); + + attr->type =3D op_pmu->type; + attr->size =3D sizeof(struct perf_event_attr); + attr->config =3D config; + attr->disabled =3D 1; + attr->sample_type =3D PERF_SAMPLE_PERIOD; + attr->freq =3D freq; + attr->sample_period =3D sample_period; /* =3D ->sample_freq */ +} + +struct ibs_configs { + /* Input */ + unsigned long config; + + /* Expected output */ + unsigned long period; + int fd; +}; + +/* + * Somehow first Fetch event with sample period =3D 0x10 causes 0 + * samples. So start with large period and decrease it gradually. + */ +struct ibs_configs fetch_configs[] =3D { + { .config =3D 0xffff, .period =3D 0xffff0, .fd =3D FD_SUCCESS }, + { .config =3D 0x1000, .period =3D 0x10000, .fd =3D FD_SUCCESS }, + { .config =3D 0xff, .period =3D 0xff0, .fd =3D FD_SUCCESS }, + { .config =3D 0x1, .period =3D 0x10, .fd =3D FD_SUCCESS }, + { .config =3D 0x0, .period =3D -1, .fd =3D FD_ERROR }, + { .config =3D 0x10000, .period =3D -1, .fd =3D FD_ERROR }, +}; + +struct ibs_configs op_configs[] =3D { + { .config =3D 0x0, .period =3D -1, .fd =3D FD_ERROR }, + { .config =3D 0x1, .period =3D -1, .fd =3D FD_ERROR }, + { .config =3D 0x8, .period =3D -1, .fd =3D FD_ERROR }, + { .config =3D 0x9, .period =3D 0x90, .fd =3D FD_SUCCESS }, + { .config =3D 0xf, .period =3D 0xf0, .fd =3D FD_SUCCESS }, + { .config =3D 0x1000, .period =3D 0x10000, .fd =3D FD_SUCCESS }, + { .config =3D 0xffff, .period =3D 0xffff0, .fd =3D FD_SUCCESS }, + { .config =3D 0x10000, .period =3D -1, .fd =3D FD_ERROR }, + { .config =3D 0x100000, .period =3D 0x100000, .fd =3D FD_SUCCESS }, + { .config =3D 0xf00000, .period =3D 0xf00000, .fd =3D FD_SUCCESS }, + { .config =3D 0xf0ffff, .period =3D 0xfffff0, .fd =3D FD_SUCCESS }, + { .config =3D 0x1f0ffff, .period =3D 0x1fffff0, .fd =3D FD_SUCCESS }, + { .config =3D 0x7f0ffff, .period =3D 0x7fffff0, .fd =3D FD_SUCCESS }, + { .config =3D 0x8f0ffff, .period =3D -1, .fd =3D FD_ERROR }, + { .config =3D 0x17f0ffff, .period =3D -1, .fd =3D FD_ERROR }, +}; + +static int __ibs_config_test(int ibs_type, struct ibs_configs *config, int= *nr_samples) +{ + struct perf_event_attr attr; + int fd, i; + void *rb; + int ret =3D 0; + + if (ibs_type =3D=3D IBS_FETCH) + fetch_prepare_attr(&attr, config->config, 0, 0); + else + op_prepare_attr(&attr, config->config, 0, 0); + + /* CPU0, All processes */ + fd =3D perf_event_open(&attr, -1, 0, -1, 0); + if (config->fd =3D=3D FD_ERROR) { + if (fd !=3D -1) { + close(fd); + return -1; + } + return 0; + } + if (fd <=3D -1) + return -1; + + rb =3D mmap(NULL, PERF_MMAP_TOTAL_SIZE, PROT_READ | PROT_WRITE, + MAP_SHARED, fd, 0); + if (rb =3D=3D MAP_FAILED) { + pr_debug("mmap() failed. [%m]\n"); + return -1; + } + + ioctl(fd, PERF_EVENT_IOC_RESET, 0); + ioctl(fd, PERF_EVENT_IOC_ENABLE, 0); + + i =3D 5; + while (i--) { + dummy_workload_1(1000000); + + ret =3D rb_drain_samples(rb, config->period, nr_samples, + period_equal); + if (ret) + break; + } + + ioctl(fd, PERF_EVENT_IOC_DISABLE, 0); + munmap(rb, PERF_MMAP_TOTAL_SIZE); + close(fd); + return ret; +} + +static int ibs_config_test(void) +{ + int nr_samples =3D 0; + unsigned long i; + int ret =3D 0; + int r; + + pr_debug("\nIBS config tests:\n"); + pr_debug("-----------------\n"); + + pr_debug("Fetch PMU tests:\n"); + for (i =3D 0; i < ARRAY_SIZE(fetch_configs); i++) { + nr_samples =3D 0; + r =3D __ibs_config_test(IBS_FETCH, &(fetch_configs[i]), &nr_samples); + + if (fetch_configs[i].fd =3D=3D FD_ERROR) { + pr_debug("0x%-16lx: %-4s\n", fetch_configs[i].config, + !r ? "Ok" : "Fail"); + } else { + /* + * Although nr_samples =3D=3D 0 is reported as Fail here, + * the failure status is not cascaded up because, we + * can not decide whether test really failed or not + * without actual samples. + */ + pr_debug("0x%-16lx: %-4s (nr samples: %d)\n", fetch_configs[i].config, + (!r && nr_samples !=3D 0) ? "Ok" : "Fail", nr_samples); + } + + ret |=3D r; + } + + pr_debug("Op PMU tests:\n"); + for (i =3D 0; i < ARRAY_SIZE(op_configs); i++) { + nr_samples =3D 0; + r =3D __ibs_config_test(IBS_OP, &(op_configs[i]), &nr_samples); + + if (op_configs[i].fd =3D=3D FD_ERROR) { + pr_debug("0x%-16lx: %-4s\n", op_configs[i].config, + !r ? "Ok" : "Fail"); + } else { + /* + * Although nr_samples =3D=3D 0 is reported as Fail here, + * the failure status is not cascaded up because, we + * can not decide whether test really failed or not + * without actual samples. + */ + pr_debug("0x%-16lx: %-4s (nr samples: %d)\n", op_configs[i].config, + (!r && nr_samples !=3D 0) ? "Ok" : "Fail", nr_samples); + } + + ret |=3D r; + } + + return ret; +} + +struct ibs_period { + /* Input */ + int freq; + unsigned long sample_freq; + + /* Output */ + int ret; + unsigned long period; +}; + +struct ibs_period fetch_period[] =3D { + { .freq =3D 0, .sample_freq =3D 0, .ret =3D FD_ERROR, .period = =3D -1 }, + { .freq =3D 0, .sample_freq =3D 1, .ret =3D FD_ERROR, .period = =3D -1 }, + { .freq =3D 0, .sample_freq =3D 0xf, .ret =3D FD_ERROR, .period = =3D -1 }, + { .freq =3D 0, .sample_freq =3D 0x10, .ret =3D FD_SUCCESS, .period = =3D 0x10 }, + { .freq =3D 0, .sample_freq =3D 0x11, .ret =3D FD_SUCCESS, .period = =3D 0x10 }, + { .freq =3D 0, .sample_freq =3D 0x8f, .ret =3D FD_SUCCESS, .period = =3D 0x80 }, + { .freq =3D 0, .sample_freq =3D 0x90, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 0, .sample_freq =3D 0x91, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 0, .sample_freq =3D 0x4d2, .ret =3D FD_SUCCESS, .period = =3D 0x4d0 }, + { .freq =3D 0, .sample_freq =3D 0x1007, .ret =3D FD_SUCCESS, .period = =3D 0x1000 }, + { .freq =3D 0, .sample_freq =3D 0xfff0, .ret =3D FD_SUCCESS, .period = =3D 0xfff0 }, + { .freq =3D 0, .sample_freq =3D 0xffff, .ret =3D FD_SUCCESS, .period = =3D 0xfff0 }, + { .freq =3D 0, .sample_freq =3D 0x10010, .ret =3D FD_SUCCESS, .period = =3D 0x10010 }, + { .freq =3D 0, .sample_freq =3D 0x7fffff, .ret =3D FD_SUCCESS, .period = =3D 0x7ffff0 }, + { .freq =3D 1, .sample_freq =3D 0, .ret =3D FD_ERROR, .period = =3D -1 }, + { .freq =3D 1, .sample_freq =3D 1, .ret =3D FD_SUCCESS, .period = =3D 0x10 }, + { .freq =3D 1, .sample_freq =3D 0xf, .ret =3D FD_SUCCESS, .period = =3D 0x10 }, + { .freq =3D 1, .sample_freq =3D 0x10, .ret =3D FD_SUCCESS, .period = =3D 0x10 }, + { .freq =3D 1, .sample_freq =3D 0x11, .ret =3D FD_SUCCESS, .period = =3D 0x10 }, + { .freq =3D 1, .sample_freq =3D 0x8f, .ret =3D FD_SUCCESS, .period = =3D 0x10 }, + { .freq =3D 1, .sample_freq =3D 0x90, .ret =3D FD_SUCCESS, .period = =3D 0x10 }, + { .freq =3D 1, .sample_freq =3D 0x91, .ret =3D FD_SUCCESS, .period = =3D 0x10 }, + { .freq =3D 1, .sample_freq =3D 0x4d2, .ret =3D FD_SUCCESS, .period = =3D 0x10 }, + { .freq =3D 1, .sample_freq =3D 0x1007, .ret =3D FD_SUCCESS, .period = =3D 0x10 }, + { .freq =3D 1, .sample_freq =3D 0xfff0, .ret =3D FD_SUCCESS, .period = =3D 0x10 }, + { .freq =3D 1, .sample_freq =3D 0xffff, .ret =3D FD_SUCCESS, .period = =3D 0x10 }, + { .freq =3D 1, .sample_freq =3D 0x10010, .ret =3D FD_SUCCESS, .period = =3D 0x10 }, + + /* ret=3D-1 because it's beyond default perf_event_max_sample_rate (10000= 0) */ + { .freq =3D 1, .sample_freq =3D 0x7fffff, .ret =3D FD_ERROR, .period = =3D -1 }, +}; + +struct ibs_period op_period[] =3D { + { .freq =3D 0, .sample_freq =3D 0, .ret =3D FD_ERROR, .period = =3D -1 }, + { .freq =3D 0, .sample_freq =3D 1, .ret =3D FD_ERROR, .period = =3D -1 }, + { .freq =3D 0, .sample_freq =3D 0xf, .ret =3D FD_ERROR, .period = =3D -1 }, + { .freq =3D 0, .sample_freq =3D 0x10, .ret =3D FD_ERROR, .period = =3D -1 }, + { .freq =3D 0, .sample_freq =3D 0x11, .ret =3D FD_ERROR, .period = =3D -1 }, + { .freq =3D 0, .sample_freq =3D 0x8f, .ret =3D FD_ERROR, .period = =3D -1 }, + { .freq =3D 0, .sample_freq =3D 0x90, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 0, .sample_freq =3D 0x91, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 0, .sample_freq =3D 0x4d2, .ret =3D FD_SUCCESS, .period = =3D 0x4d0 }, + { .freq =3D 0, .sample_freq =3D 0x1007, .ret =3D FD_SUCCESS, .period = =3D 0x1000 }, + { .freq =3D 0, .sample_freq =3D 0xfff0, .ret =3D FD_SUCCESS, .period = =3D 0xfff0 }, + { .freq =3D 0, .sample_freq =3D 0xffff, .ret =3D FD_SUCCESS, .period = =3D 0xfff0 }, + { .freq =3D 0, .sample_freq =3D 0x10010, .ret =3D FD_SUCCESS, .period = =3D 0x10010 }, + { .freq =3D 0, .sample_freq =3D 0x7fffff, .ret =3D FD_SUCCESS, .period = =3D 0x7ffff0 }, + { .freq =3D 1, .sample_freq =3D 0, .ret =3D FD_ERROR, .period = =3D -1 }, + { .freq =3D 1, .sample_freq =3D 1, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 1, .sample_freq =3D 0xf, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 1, .sample_freq =3D 0x10, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 1, .sample_freq =3D 0x11, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 1, .sample_freq =3D 0x8f, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 1, .sample_freq =3D 0x90, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 1, .sample_freq =3D 0x91, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 1, .sample_freq =3D 0x4d2, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 1, .sample_freq =3D 0x1007, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 1, .sample_freq =3D 0xfff0, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 1, .sample_freq =3D 0xffff, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + { .freq =3D 1, .sample_freq =3D 0x10010, .ret =3D FD_SUCCESS, .period = =3D 0x90 }, + + /* ret=3D-1 because it's beyond default perf_event_max_sample_rate (10000= 0) */ + { .freq =3D 1, .sample_freq =3D 0x7fffff, .ret =3D FD_ERROR, .period = =3D -1 }, +}; + +static int __ibs_period_constraint_test(int ibs_type, struct ibs_period *p= eriod, + int *nr_samples) +{ + struct perf_event_attr attr; + int ret =3D 0; + void *rb; + int fd; + + if (period->freq && period->sample_freq >=3D perf_event_max_sample_rate) { + nr_samples =3D 0; + return 0; + } + + if (ibs_type =3D=3D IBS_FETCH) + fetch_prepare_attr(&attr, 0, period->freq, period->sample_freq); + else + op_prepare_attr(&attr, 0, period->freq, period->sample_freq); + + /* CPU0, All processes */ + fd =3D perf_event_open(&attr, -1, 0, -1, 0); + if (period->ret =3D=3D FD_ERROR) { + if (fd !=3D -1) { + close(fd); + return -1; + } + return 0; + } + if (fd <=3D -1) + return -1; + + rb =3D mmap(NULL, PERF_MMAP_TOTAL_SIZE, PROT_READ | PROT_WRITE, + MAP_SHARED, fd, 0); + if (rb =3D=3D MAP_FAILED) { + pr_debug("mmap() failed. [%m]\n"); + close(fd); + return -1; + } + + ioctl(fd, PERF_EVENT_IOC_RESET, 0); + ioctl(fd, PERF_EVENT_IOC_ENABLE, 0); + + if (period->freq) { + dummy_workload_1(100000); + ret =3D rb_drain_samples(rb, period->period, nr_samples, + period_higher); + } else { + dummy_workload_1(period->sample_freq * 10); + ret =3D rb_drain_samples(rb, period->period, nr_samples, + period_equal); + } + + ioctl(fd, PERF_EVENT_IOC_DISABLE, 0); + munmap(rb, PERF_MMAP_TOTAL_SIZE); + close(fd); + return ret; +} + +static int ibs_period_constraint_test(void) +{ + unsigned long i; + int nr_samples; + int ret =3D 0; + int r; + + pr_debug("\nIBS sample period constraint tests:\n"); + pr_debug("-----------------------------------\n"); + + pr_debug("Fetch PMU test:\n"); + for (i =3D 0; i < ARRAY_SIZE(fetch_period); i++) { + nr_samples =3D 0; + r =3D __ibs_period_constraint_test(IBS_FETCH, &fetch_period[i], + &nr_samples); + + if (fetch_period[i].ret =3D=3D FD_ERROR) { + pr_debug("freq %d, sample_freq %7ld: %-4s\n", + fetch_period[i].freq, fetch_period[i].sample_freq, + !r ? "Ok" : "Fail"); + } else { + /* + * Although nr_samples =3D=3D 0 is reported as Fail here, + * the failure status is not cascaded up because, we + * can not decide whether test really failed or not + * without actual samples. + */ + pr_debug("freq %d, sample_freq %7ld: %-4s (nr samples: %d)\n", + fetch_period[i].freq, fetch_period[i].sample_freq, + (!r && nr_samples !=3D 0) ? "Ok" : "Fail", nr_samples); + } + ret |=3D r; + } + + pr_debug("Op PMU test:\n"); + for (i =3D 0; i < ARRAY_SIZE(op_period); i++) { + nr_samples =3D 0; + r =3D __ibs_period_constraint_test(IBS_OP, &op_period[i], + &nr_samples); + + if (op_period[i].ret =3D=3D FD_ERROR) { + pr_debug("freq %d, sample_freq %7ld: %-4s\n", + op_period[i].freq, op_period[i].sample_freq, + !r ? "Ok" : "Fail"); + } else { + /* + * Although nr_samples =3D=3D 0 is reported as Fail here, + * the failure status is not cascaded up because, we + * can not decide whether test really failed or not + * without actual samples. + */ + pr_debug("freq %d, sample_freq %7ld: %-4s (nr samples: %d)\n", + op_period[i].freq, op_period[i].sample_freq, + (!r && nr_samples !=3D 0) ? "Ok" : "Fail", nr_samples); + } + ret |=3D r; + } + + return ret; +} + +struct ibs_ioctl { + /* Input */ + int freq; + unsigned long period; + + /* Expected output */ + int ret; +}; + +struct ibs_ioctl fetch_ioctl[] =3D { + { .freq =3D 0, .period =3D 0x0, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x1, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0xf, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x10, .ret =3D FD_SUCCESS }, + { .freq =3D 0, .period =3D 0x11, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x1f, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x20, .ret =3D FD_SUCCESS }, + { .freq =3D 0, .period =3D 0x80, .ret =3D FD_SUCCESS }, + { .freq =3D 0, .period =3D 0x8f, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x90, .ret =3D FD_SUCCESS }, + { .freq =3D 0, .period =3D 0x91, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x100, .ret =3D FD_SUCCESS }, + { .freq =3D 0, .period =3D 0xfff0, .ret =3D FD_SUCCESS }, + { .freq =3D 0, .period =3D 0xffff, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x10000, .ret =3D FD_SUCCESS }, + { .freq =3D 0, .period =3D 0x1fff0, .ret =3D FD_SUCCESS }, + { .freq =3D 0, .period =3D 0x1fff5, .ret =3D FD_ERROR }, + { .freq =3D 1, .period =3D 0x0, .ret =3D FD_ERROR }, + { .freq =3D 1, .period =3D 0x1, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0xf, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x10, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x11, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x1f, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x20, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x80, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x8f, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x90, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x91, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x100, .ret =3D FD_SUCCESS }, +}; + +struct ibs_ioctl op_ioctl[] =3D { + { .freq =3D 0, .period =3D 0x0, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x1, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0xf, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x10, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x11, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x1f, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x20, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x80, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x8f, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x90, .ret =3D FD_SUCCESS }, + { .freq =3D 0, .period =3D 0x91, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x100, .ret =3D FD_SUCCESS }, + { .freq =3D 0, .period =3D 0xfff0, .ret =3D FD_SUCCESS }, + { .freq =3D 0, .period =3D 0xffff, .ret =3D FD_ERROR }, + { .freq =3D 0, .period =3D 0x10000, .ret =3D FD_SUCCESS }, + { .freq =3D 0, .period =3D 0x1fff0, .ret =3D FD_SUCCESS }, + { .freq =3D 0, .period =3D 0x1fff5, .ret =3D FD_ERROR }, + { .freq =3D 1, .period =3D 0x0, .ret =3D FD_ERROR }, + { .freq =3D 1, .period =3D 0x1, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0xf, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x10, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x11, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x1f, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x20, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x80, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x8f, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x90, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x91, .ret =3D FD_SUCCESS }, + { .freq =3D 1, .period =3D 0x100, .ret =3D FD_SUCCESS }, +}; + +static int __ibs_ioctl_test(int ibs_type, struct ibs_ioctl *ibs_ioctl) +{ + struct perf_event_attr attr; + int ret =3D 0; + int fd; + int r; + + if (ibs_type =3D=3D IBS_FETCH) + fetch_prepare_attr(&attr, 0, ibs_ioctl->freq, 1000); + else + op_prepare_attr(&attr, 0, ibs_ioctl->freq, 1000); + + /* CPU0, All processes */ + fd =3D perf_event_open(&attr, -1, 0, -1, 0); + if (fd <=3D -1) { + pr_debug("event_open() Failed\n"); + return -1; + } + + r =3D ioctl(fd, PERF_EVENT_IOC_PERIOD, &ibs_ioctl->period); + if ((ibs_ioctl->ret =3D=3D FD_SUCCESS && r <=3D -1) || + (ibs_ioctl->ret =3D=3D FD_ERROR && r >=3D 0)) { + ret =3D -1; + } + + close(fd); + return ret; +} + +static int ibs_ioctl_test(void) +{ + unsigned long i; + int ret =3D 0; + int r; + + pr_debug("\nIBS ioctl() tests:\n"); + pr_debug("------------------\n"); + + pr_debug("Fetch PMU tests\n"); + for (i =3D 0; i < ARRAY_SIZE(fetch_ioctl); i++) { + r =3D __ibs_ioctl_test(IBS_FETCH, &fetch_ioctl[i]); + + pr_debug("ioctl(%s =3D 0x%-7lx): %s\n", + fetch_ioctl[i].freq ? "freq " : "period", + fetch_ioctl[i].period, r ? "Fail" : "Ok"); + ret |=3D r; + } + + pr_debug("Op PMU tests\n"); + for (i =3D 0; i < ARRAY_SIZE(op_ioctl); i++) { + r =3D __ibs_ioctl_test(IBS_OP, &op_ioctl[i]); + + pr_debug("ioctl(%s =3D 0x%-7lx): %s\n", + op_ioctl[i].freq ? "freq " : "period", + op_ioctl[i].period, r ? "Fail" : "Ok"); + ret |=3D r; + } + + return ret; +} + +static int ibs_freq_neg_test(void) +{ + struct perf_event_attr attr; + int fd; + + pr_debug("\nIBS freq (negative) tests:\n"); + pr_debug("--------------------------\n"); + + /* + * Assuming perf_event_max_sample_rate <=3D 100000, + * config: 0x300D40 =3D=3D> MaxCnt: 200000 + */ + op_prepare_attr(&attr, 0x300D40, 1, 0); + + /* CPU0, All processes */ + fd =3D perf_event_open(&attr, -1, 0, -1, 0); + if (fd !=3D -1) { + pr_debug("freq 1, sample_freq 200000: Fail\n"); + close(fd); + return -1; + } + + pr_debug("freq 1, sample_freq 200000: Ok\n"); + + return 0; +} + +static int __ibs_l3missonly_test(char *perf, int ibs_type, int *nr_samples= , int min_period) +{ + struct perf_event_attr attr; + int ret =3D 0; + void *rb; + int fd; + + if (ibs_type =3D=3D IBS_FETCH) + fetch_prepare_attr(&attr, 0x800000000000000UL, 1, 10000); + else + op_prepare_attr(&attr, 0x10000, 1, 10000); + + /* CPU0, All processes */ + fd =3D perf_event_open(&attr, -1, 0, -1, 0); + if (fd =3D=3D -1) { + pr_debug("perf_event_open() failed. [%m]\n"); + return -1; + } + + rb =3D mmap(NULL, PERF_MMAP_TOTAL_SIZE, PROT_READ | PROT_WRITE, + MAP_SHARED, fd, 0); + if (rb =3D=3D MAP_FAILED) { + pr_debug("mmap() failed. [%m]\n"); + close(fd); + return -1; + } + + ioctl(fd, PERF_EVENT_IOC_RESET, 0); + ioctl(fd, PERF_EVENT_IOC_ENABLE, 0); + + dummy_workload_2(perf); + + ioctl(fd, PERF_EVENT_IOC_DISABLE, 0); + + ret =3D rb_drain_samples(rb, min_period, nr_samples, period_higher); + + munmap(rb, PERF_MMAP_TOTAL_SIZE); + close(fd); + return ret; +} + +static int ibs_l3missonly_test(char *perf) +{ + int nr_samples =3D 0; + int ret =3D 0; + int r =3D 0; + + pr_debug("\nIBS L3MissOnly test: (takes a while)\n"); + pr_debug("--------------------\n"); + + if (perf_pmu__has_format(fetch_pmu, "l3missonly")) { + nr_samples =3D 0; + r =3D __ibs_l3missonly_test(perf, IBS_FETCH, &nr_samples, 0x10); + /* + * Although nr_samples =3D=3D 0 is reported as Fail here, + * the failure status is not cascaded up because, we + * can not decide whether test really failed or not + * without actual samples. + */ + pr_debug("Fetch L3MissOnly: %-4s (nr_samples: %d)\n", + (!r && nr_samples !=3D 0) ? "Ok" : "Fail", nr_samples); + ret |=3D r; + } + + if (perf_pmu__has_format(op_pmu, "l3missonly")) { + nr_samples =3D 0; + r =3D __ibs_l3missonly_test(perf, IBS_OP, &nr_samples, 0x90); + /* + * Although nr_samples =3D=3D 0 is reported as Fail here, + * the failure status is not cascaded up because, we + * can not decide whether test really failed or not + * without actual samples. + */ + pr_debug("Op L3MissOnly: %-4s (nr_samples: %d)\n", + (!r && nr_samples !=3D 0) ? "Ok" : "Fail", nr_samples); + ret |=3D r; + } + + return ret; +} + +static unsigned int get_perf_event_max_sample_rate(void) +{ + unsigned int max_sample_rate =3D 100000; + FILE *fp; + int ret; + + fp =3D fopen("/proc/sys/kernel/perf_event_max_sample_rate", "r"); + if (!fp) { + pr_debug("Can't open perf_event_max_sample_rate. Asssuming %d\n", + max_sample_rate); + goto out; + } + + ret =3D fscanf(fp, "%d", &max_sample_rate); + if (ret =3D=3D EOF) { + pr_debug("Can't read perf_event_max_sample_rate. Assuming 100000\n"); + max_sample_rate =3D 100000; + } + fclose(fp); + +out: + return max_sample_rate; +} + +int test__amd_ibs_period(struct test_suite *test __maybe_unused, + int subtest __maybe_unused) +{ + char perf[PATH_MAX] =3D {'\0'}; + int ret =3D TEST_OK; + + perf_event_max_sample_rate =3D get_perf_event_max_sample_rate(); + fetch_pmu =3D perf_pmus__find("ibs_fetch"); + op_pmu =3D perf_pmus__find("ibs_op"); + + if (!x86__is_amd_cpu() || !fetch_pmu || !op_pmu) + return TEST_SKIP; + + perf_exe(perf, sizeof(perf)); + + if (sched_affine(0)) + return TEST_FAIL; + + /* + * Perf event can be opened in two modes: + * 1 Freq mode + * perf_event_attr->freq =3D 1, ->sample_freq =3D + * 2 Sample period mode + * perf_event_attr->freq =3D 0, ->sample_period =3D + * + * Instead of using above interface, IBS event in 'sample period mode' + * can also be opened by passing value directly in a MaxCnt + * bitfields of perf_event_attr->config. Test this IBS specific special + * interface. + */ + if (ibs_config_test()) + ret =3D TEST_FAIL; + + /* + * IBS Fetch and Op PMUs have HW constraints on minimum sample period. + * Also, sample period value must be in multiple of 0x10. Test that IBS + * driver honors HW constraints for various possible values in Freq as + * well as Sample Period mode IBS events. + */ + if (ibs_period_constraint_test()) + ret =3D TEST_FAIL; + + /* + * Test ioctl() with various sample period values for IBS event. + */ + if (ibs_ioctl_test()) + ret =3D TEST_FAIL; + + /* + * Test that opening of freq mode IBS event fails when the freq value + * is passed through ->config, not explicitly in ->sample_freq. Also + * use high freq value (beyond perf_event_max_sample_rate) to test IBS + * driver do not bypass perf_event_max_sample_rate checks. + */ + if (ibs_freq_neg_test()) + ret =3D TEST_FAIL; + + /* + * L3MissOnly is a post-processing filter, i.e. IBS HW checks for L3 + * Miss at the completion of the tagged uOp. The sample is discarded + * if the tagged uOp did not cause L3Miss. Also, IBS HW internally + * resets CurCnt to a small pseudo-random value and resumes counting. + * A new uOp is tagged once CurCnt reaches to MaxCnt. But the process + * repeats until the tagged uOp causes an L3 Miss. + * + * With the freq mode event, the next sample period is calculated by + * generic kernel on every sample to achieve desired freq of samples. + * + * Since the number of times HW internally reset CurCnt and the pseudo- + * random value of CurCnt for all those occurrences are not known to SW, + * the sample period adjustment by kernel goes for a toes for freq mode + * IBS events. Kernel will set very small period for the next sample if + * the window between current sample and prev sample is too high due to + * multiple samples being rejected by IBS internally. + * + * Test that IBS sample period constraints are honored when L3MissOnly + * is ON. + */ + if (ibs_l3missonly_test(perf)) + ret =3D TEST_FAIL; + + return ret; +} diff --git a/tools/perf/arch/x86/tests/arch-tests.c b/tools/perf/arch/x86/t= ests/arch-tests.c index a216a5d172ed..bfee2432515b 100644 --- a/tools/perf/arch/x86/tests/arch-tests.c +++ b/tools/perf/arch/x86/tests/arch-tests.c @@ -25,6 +25,7 @@ DEFINE_SUITE("x86 bp modify", bp_modify); #endif DEFINE_SUITE("x86 Sample parsing", x86_sample_parsing); DEFINE_SUITE("AMD IBS via core pmu", amd_ibs_via_core_pmu); +DEFINE_SUITE_EXCLUSIVE("AMD IBS sample period", amd_ibs_period); static struct test_case hybrid_tests[] =3D { TEST_CASE_REASON("x86 hybrid event parsing", hybrid, "not hybrid"), { .name =3D NULL, } @@ -50,6 +51,7 @@ struct test_suite *arch_tests[] =3D { #endif &suite__x86_sample_parsing, &suite__amd_ibs_via_core_pmu, + &suite__amd_ibs_period, &suite__hybrid, NULL, }; --=20 2.47.0