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Fri, 06 Dec 2024 01:36:02 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B61a0LB016843 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 6 Dec 2024 01:36:00 GMT Received: from yijiyang-gv.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 5 Dec 2024 17:35:56 -0800 From: Yijie Yang Date: Fri, 6 Dec 2024 09:35:04 +0800 Subject: [PATCH v5 1/2] arm64: dts: qcom: qcs8300: add the first 2.5G ethernet Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241206-dts_qcs8300-v5-1-422e4fda292d@quicinc.com> References: <20241206-dts_qcs8300-v5-0-422e4fda292d@quicinc.com> In-Reply-To: <20241206-dts_qcs8300-v5-0-422e4fda292d@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran CC: , , , , Yijie Yang , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Add the internal SGMII/SerDes PHY node as well. Reviewed-by: Konrad Dybcio Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 43 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index 2c35f96c3f289d5e2e57e0e30ef5e17cd1286188..4e37a3ed29f302192dfb37e1489= ec325c84d6ea8 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -772,6 +772,15 @@ lpass_ag_noc: interconnect@3c40000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + serdes0: phy@8909000 { + compatible =3D "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmi= i-phy"; + reg =3D <0x0 0x08909000 0x0 0x00000e10>; + clocks =3D <&gcc GCC_SGMI_CLKREF_EN>; + clock-names =3D "sgmi_ref"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + pmu@9091000 { compatible =3D "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg =3D <0x0 0x9091000 0x0 0x1000>; @@ -1308,6 +1317,40 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; =20 + ethernet0: ethernet@23040000 { + compatible =3D "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; + reg =3D <0x0 0x23040000 0x0 0x00010000>, + <0x0 0x23056000 0x0 0x00000100>; + reg-names =3D "stmmaceth", "rgmii"; + + interrupts =3D , + ; + interrupt-names =3D "macirq", "sfty"; + + clocks =3D <&gcc GCC_EMAC0_AXI_CLK>, + <&gcc GCC_EMAC0_SLV_AHB_CLK>, + <&gcc GCC_EMAC0_PTP_CLK>, + <&gcc GCC_EMAC0_PHY_AUX_CLK>; + clock-names =3D "stmmaceth", + "pclk", + "ptp_ref", + "phyaux"; + power-domains =3D <&gcc GCC_EMAC0_GDSC>; + + phys =3D <&serdes0>; + phy-names =3D "serdes"; + + iommus =3D <&apps_smmu 0x120 0xf>; + dma-coherent; + + snps,tso; + snps,pbl =3D <32>; + rx-fifo-depth =3D <16384>; + tx-fifo-depth =3D <20480>; + + status =3D "disabled"; + }; + nspa_noc: interconnect@260c0000 { compatible =3D "qcom,qcs8300-nspa-noc"; reg =3D <0x0 0x260c0000 0x0 0x16080>; --=20 2.34.1 From nobody Wed Dec 18 05:50:49 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAB6E76048; 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Add the MDC and MDIO pin functions for ethernet0 on qcs8300-ride. Enable the ethernet port on qcs8300-ride. Signed-off-by: Yijie Yang Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 112 ++++++++++++++++++++++++++= ++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dt= s/qcom/qcs8300-ride.dts index 7eed19a694c39dbe791afb6a991db65acb37e597..302542305726da669f0c515da12= cbdec51036c51 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -210,6 +210,95 @@ vreg_l9c: ldo9 { }; }; =20 +ðernet0 { + phy-mode =3D "2500base-x"; + phy-handle =3D <&phy0>; + + pinctrl-0 =3D <ðernet0_default>; + pinctrl-names =3D "default"; + + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,ps-speed =3D <1000>; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy0: phy@8 { + compatible =3D "ethernet-phy-id31c3.1c33"; + reg =3D <0x8>; + device_type =3D "ethernet-phy"; + interrupts-extended =3D <&tlmm 4 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&tlmm 31 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; +}; + &gcc { clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, @@ -247,6 +336,29 @@ &rpmhcc { clock-names =3D "xo"; }; =20 +&serdes0 { + phy-supply =3D <&vreg_l5a>; + status =3D "okay"; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins =3D "gpio5"; + function =3D "emac0_mdc"; + drive-strength =3D <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins =3D "gpio6"; + function =3D "emac0_mdio"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; +}; + &uart7 { status =3D "okay"; }; --=20 2.34.1