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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 11/15] cpufreq/amd-pstate: Cache EPP value and use that everywhere Date: Thu, 5 Dec 2024 16:28:43 -0600 Message-ID: <20241205222847.7889-12-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A347:EE_|PH7PR12MB6884:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d07fbd9-79a5-4484-86d5-08dd157c3e00 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?tjEe1fMFYo6D7L1s7esIYSL/PokUm/bJguyW+SY6zrOAYxrl6153nQEYrT3W?= =?us-ascii?Q?cZfN34eHiw/RDbdPXHjBZLfbfWLYDoAhVTICIyqAEKe+BQMPgeuLLBl3nUQN?= =?us-ascii?Q?4MzATzrqDA01CHs3MoRBJv8V+8rhztEtNY+VI3K13lXipc+GJ6yWmJ73rT1H?= =?us-ascii?Q?UlHzvXGvKb1SI2U3Al/+RqXCWh59uzZECuSglIInujzca7TSLNc/6ssle1Gz?= =?us-ascii?Q?ZjYNNJGcoo2/CQFKSwmi2UgMtsIrnA8nmMRDrYTiqQCZsj4+hqrkJcsOBSBa?= =?us-ascii?Q?kMR1ueiqWhQtQzX3cPocsQcOMHf7uSVTAOvdaXdhC/lZ5Vk6p7Kxr9Hxnh5I?= =?us-ascii?Q?eg6PosOJF4C/UamKIY4ToQ4rg3hcPRxbgAuI1r96UEOHyXOIj5oTF9YIN1qV?= =?us-ascii?Q?vIY2hv2UR2OQKJtgViUWH2Yul1hwRvmrZcRccvuy5CAb3v7+oAV3aBYnRRJH?= =?us-ascii?Q?SPN2zV8szrBOYr1m8YfyYQJz7wIGU6jD9MQq5FzQ4bei9uNzZ4Brq2T/ksZ0?= =?us-ascii?Q?pbssE8MGpzl/aiRhDyiP0pVvyai6lMggzB4ZreTXS17gEAZGczKJSOxIrBSR?= =?us-ascii?Q?3IJRSNpCJXrJFgOxXEhr2HTBDaFWFo6yxlujcLbgHDQMLY3KWft5WpjzxUrU?= =?us-ascii?Q?06AAYyMDqHLynztQOKwynhTdYMSGTemTE/fH4ndb8HdPWDlKE5LdHLVzTqz5?= =?us-ascii?Q?dT6XZL3RUOXN7WpzDyBONyAe342c0unI6KodLGoJfidIVMF+qLeZ8rnlPnmP?= =?us-ascii?Q?2uKUQKB0qiWrn0KaAmVyWE01EvwtzNpjrWyXgoefqCJz7Vj/igK/N8E1gBf3?= =?us-ascii?Q?/TlxktgjjfHAwlMFTfPn5kIpsV9Y+JvdUhgZonFD2qloi7ERSyhKf5XB1/Ju?= =?us-ascii?Q?nTiJpuaBxFObS7tWWuPoHB8Rt/ECxSW0KnxShPBpcj5BD9rwV3Yq7iGvD/4+?= =?us-ascii?Q?OH21dA9iN1woikvHASXxeVZ2QxlmKI5qLBnKNs+lYT8xZBjLbdiikwnX2ZoR?= =?us-ascii?Q?ZSMQidRWYNDN/Lp5CUijaO0uTlyUdCZrOZE61jlvxdjq5VxrrWCMoPF4piCi?= =?us-ascii?Q?hUADW9jzSLsfyAIN9mMEpH/FhDK2v/Cgjvh+Bv8q0sZifko4rxlP4QzarGnO?= =?us-ascii?Q?cn7poY43XvcN+F0Ut3EmvBXVFCVbV/3lZIHLS9LABuqkMH1FlZiiLPGfMZGr?= =?us-ascii?Q?ByzmLqoCplUHx6P6wJ1BvApqD6BypyjZ+cWM6XWyi6I5joHrPQxDnYmvP89t?= =?us-ascii?Q?J2K+gXV77cl96kwVQe1zqXUU1x2zD9Yc8EP3z/iO4f7k/RlwF/iWSHs2ZEb+?= =?us-ascii?Q?UfUYwQc3NVDgyoCXaOfvLGO+HiwePwn49wTQOVi8wabe9aXyKuh43qok/ggE?= =?us-ascii?Q?E0D/4WSh9RM1zyejVMuB8A0Lf08luzc0OZNQf5xt+S5TXFTS8qSKSeE5Vkd3?= =?us-ascii?Q?pQSaxd+DKT8omMsiDHFoQm3mM5hZvV9r?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:11.5890 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d07fbd9-79a5-4484-86d5-08dd157c3e00 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A347.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6884 Content-Type: text/plain; charset="utf-8" Cache the value in cpudata->epp_cached, and use that for all callers. As all callers use cached value merge amd_pstate_get_energy_pref_index() into show_energy_performance_preference(). Check if the EPP value is changed before writing it to MSR or shared memory region. Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 107 +++++++++++++++-------------------- 1 file changed, 45 insertions(+), 62 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 5ee53b45c1ca1..20de3a9fd992d 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -186,29 +186,28 @@ static inline int get_mode_idx_from_str(const char *s= tr, size_t size) static DEFINE_MUTEX(amd_pstate_limits_lock); static DEFINE_MUTEX(amd_pstate_driver_lock); =20 -static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) +static s16 msr_get_epp(struct amd_cpudata *cpudata) { + u64 value; int ret; =20 - if (!cppc_req_cached) { - ret =3D rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req_cached); - if (ret < 0) { - pr_debug("Could not retrieve energy perf value (%d)\n", ret); - return ret; - } + ret =3D rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); + if (ret < 0) { + pr_debug("Could not retrieve energy perf value (%d)\n", ret); + return ret; } =20 - return FIELD_GET(AMD_PSTATE_EPP_PERF_MASK, cppc_req_cached); + return FIELD_GET(AMD_PSTATE_EPP_PERF_MASK, value); } =20 DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp); =20 -static inline s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc= _req_cached) +static inline s16 amd_pstate_get_epp(struct amd_cpudata *cpudata) { - return static_call(amd_pstate_get_epp)(cpudata, cppc_req_cached); + return static_call(amd_pstate_get_epp)(cpudata); } =20 -static s16 shmem_get_epp(struct amd_cpudata *cpudata, u64 dummy) +static s16 shmem_get_epp(struct amd_cpudata *cpudata) { u64 epp; int ret; @@ -222,35 +221,6 @@ static s16 shmem_get_epp(struct amd_cpudata *cpudata, = u64 dummy) return (s16)(epp & 0xff); } =20 -static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata) -{ - s16 epp; - int index =3D -EINVAL; - - epp =3D amd_pstate_get_epp(cpudata, 0); - if (epp < 0) - return epp; - - switch (epp) { - case AMD_CPPC_EPP_PERFORMANCE: - index =3D EPP_INDEX_PERFORMANCE; - break; - case AMD_CPPC_EPP_BALANCE_PERFORMANCE: - index =3D EPP_INDEX_BALANCE_PERFORMANCE; - break; - case AMD_CPPC_EPP_BALANCE_POWERSAVE: - index =3D EPP_INDEX_BALANCE_POWERSAVE; - break; - case AMD_CPPC_EPP_POWERSAVE: - index =3D EPP_INDEX_POWERSAVE; - break; - default: - break; - } - - return index; -} - static int msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch) { @@ -275,19 +245,23 @@ static inline int amd_pstate_update_perf(struct amd_c= pudata *cpudata, =20 static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) { - u64 value =3D READ_ONCE(cpudata->cppc_req_cached); + u64 value, prev; int ret; =20 + value =3D prev =3D READ_ONCE(cpudata->cppc_req_cached); value &=3D ~AMD_PSTATE_EPP_PERF_MASK; value |=3D FIELD_PREP(AMD_PSTATE_EPP_PERF_MASK, epp); =20 + if (value =3D=3D prev) + return 0; + ret =3D wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); if (ret) { pr_err("failed to set energy perf value (%d)\n", ret); return ret; } =20 - cpudata->epp_cached =3D epp; + WRITE_ONCE(cpudata->epp_cached, epp); WRITE_ONCE(cpudata->cppc_req_cached, value); =20 return ret; @@ -305,13 +279,16 @@ static int shmem_set_epp(struct amd_cpudata *cpudata,= u32 epp) int ret; struct cppc_perf_ctrls perf_ctrls; =20 + if (epp =3D=3D cpudata->epp_cached) + return 0; + perf_ctrls.energy_perf =3D epp; ret =3D cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); if (ret) { pr_debug("failed to set energy perf value (%d)\n", ret); return ret; } - cpudata->epp_cached =3D epp; + WRITE_ONCE(cpudata->epp_cached, epp); =20 return ret; } @@ -1216,9 +1193,22 @@ static ssize_t show_energy_performance_preference( struct amd_cpudata *cpudata =3D policy->driver_data; int preference; =20 - preference =3D amd_pstate_get_energy_pref_index(cpudata); - if (preference < 0) - return preference; + switch (cpudata->epp_cached) { + case AMD_CPPC_EPP_PERFORMANCE: + preference =3D EPP_INDEX_PERFORMANCE; + break; + case AMD_CPPC_EPP_BALANCE_PERFORMANCE: + preference =3D EPP_INDEX_BALANCE_PERFORMANCE; + break; + case AMD_CPPC_EPP_BALANCE_POWERSAVE: + preference =3D EPP_INDEX_BALANCE_POWERSAVE; + break; + case AMD_CPPC_EPP_POWERSAVE: + preference =3D EPP_INDEX_POWERSAVE; + break; + default: + return -EINVAL; + } =20 return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); } @@ -1503,7 +1493,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_pol= icy *policy) =20 policy->driver_data =3D cpudata; =20 - cpudata->epp_cached =3D cpudata->epp_default =3D amd_pstate_get_epp(cpuda= ta, 0); + cpudata->epp_cached =3D cpudata->epp_default =3D amd_pstate_get_epp(cpuda= ta); =20 policy->min =3D policy->cpuinfo.min_freq; policy->max =3D policy->cpuinfo.max_freq; @@ -1557,35 +1547,26 @@ static int amd_pstate_epp_update_limit(struct cpufr= eq_policy *policy) { struct amd_cpudata *cpudata =3D policy->driver_data; u64 value; - s16 epp; =20 amd_pstate_update_min_max_limit(policy); =20 value =3D READ_ONCE(cpudata->cppc_req_cached); =20 value &=3D ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | - AMD_PSTATE_DES_PERF_MASK); + AMD_PSTATE_DES_PERF_MASK | AMD_PSTATE_EPP_PERF_MASK); value |=3D FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, cpudata->max_limit_perf); value |=3D FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, 0); value |=3D FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, cpudata->min_limit_perf); =20 - /* Get BIOS pre-defined epp value */ - epp =3D amd_pstate_get_epp(cpudata, value); - if (epp < 0) { - /** - * This return value can only be negative for shared_memory - * systems where EPP register read/write not supported. - */ - return epp; - } - if (cpudata->policy =3D=3D CPUFREQ_POLICY_PERFORMANCE) - epp =3D 0; + WRITE_ONCE(cpudata->epp_cached, 0); + value |=3D FIELD_PREP(AMD_PSTATE_EPP_PERF_MASK, cpudata->epp_cached); =20 WRITE_ONCE(cpudata->cppc_req_cached, value); =20 if (trace_amd_pstate_epp_perf_enabled()) { - trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, epp, + trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, + cpudata->epp_cached, cpudata->min_limit_perf, cpudata->max_limit_perf, cpudata->boost_state); @@ -1594,7 +1575,7 @@ static int amd_pstate_epp_update_limit(struct cpufreq= _policy *policy) amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U, cpudata->max_limit_perf, false); =20 - return amd_pstate_set_epp(cpudata, epp); + return amd_pstate_set_epp(cpudata, READ_ONCE(cpudata->epp_cached)); } =20 static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) @@ -1610,6 +1591,8 @@ static int amd_pstate_epp_set_policy(struct cpufreq_p= olicy *policy) =20 cpudata->policy =3D policy->policy; =20 + guard(mutex)(&amd_pstate_limits_lock); + ret =3D amd_pstate_epp_update_limit(policy); if (ret) return ret; --=20 2.43.0