From nobody Thu Dec 18 00:09:36 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1D53225772 for ; Thu, 5 Dec 2024 17:41:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733420504; cv=none; b=EcV6KWAAwz9Gt5rhFc4iuBaGS8QIkQeiyk64AmA4Dp9J/SZUEcv983gHJMIGrdFu0Op9KMEj1A1tR25f6X1Sj3LaeHyumKoLaqjnUWgbmIoJnd++Ls7XPtbg7vhKoHhqJif9Js76AsxOyYECJTUDXTlfYtklIIjaouFgsa1SVVA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733420504; c=relaxed/simple; bh=qkOSoUzBaI2Fy8SWilouKpsw5RFfufxg16Ai+gil2WI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AnLdEnsDssGMUd3wRRuXnSAw1FXpa/sx4+jh+2rCY6IIoF2I/SbOLaHoqu9KM+1UaNNh7kX3rG1wtk2gJHUhecwHEgSmuPZ1nzw14U1wQjyFipC4BwtaxdBOAlylARVBL9QN7F906OnWfHtvyywKXbriZoQQISlCmq/N0OfGwO0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=CtXWiCQ0; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="CtXWiCQ0" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-434a2033562so11919965e9.1 for ; Thu, 05 Dec 2024 09:41:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733420501; x=1734025301; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XKTSOcD5L+z2qw5+nXllrVScKZxcBqJj6UXu4K9Ii9s=; b=CtXWiCQ0iAj64ySZJ7k+jQsVdV09vNpwwFL+aNbKMMlei6LJjCeLPG+Co6/JcinROG 8DxX2qlGnRgF0cX0qmoBmARpsgHyhB9blHXWNkx8neADPgc1nJKaavHUaJkjtkD/2B4n EjIDAyHA1tojW+PDJkpEtLAcjedgZntREbSxE4dwE6WIc17mFvU3FQZ95/TwnYw+MqS8 jqGryan9d5BvDis7sWMbIurNYl1DNEzqkGGXI/CtG178YXc0LhqIrCK45fJZLSxxMuXk 2YEZ1OVkloOQkXuEF9Ug1mfRSAw7vbyRiiM4nvl5SRUkwV03Q5J4zhEzzk6m2cHns0KB q4aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733420501; x=1734025301; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XKTSOcD5L+z2qw5+nXllrVScKZxcBqJj6UXu4K9Ii9s=; b=vPQuW4D6qlCDoXD7W67epbSyM8C0yVsEjAVEDJ8pZaWFM+c6t6FBZlNdrpMbkb2/UE moAHBeP8fufmDUBPdFu0XZjnMJqUMTWeyhzCh0riM2N6lcV453rWaX1tY5pzvtGoxkLI gqq6yZ2vUN32GYyTtsUfFuEweQD+lEliNxbYRRxd4w6l0qGEOjvF1sQS2t9z48t2qrlP ivMYu/TPqfJrdca5N67+Eu1R9339+v6Dm3qNgZiaF9LHob8HazjC2EM4kUrKkSd7x1vc HfPNhWgPsXjvcKRVnHsBn3QKbJ5E7p3IwBAsX9Kp1nNLY3b99cJmSjSmmXFVfzKSBvJA eBOA== X-Gm-Message-State: AOJu0Yx7WDmJcM9KQmXMS+2xCDtM2MBM6WMxSN3z+z/BaWEdqSknHWSi Tehu2MCYpvVvQzYurGVlbd1PEFVvWnZOUJSSrKpNS9uw7AGSD1mZkBuuM36Gst8= X-Gm-Gg: ASbGncuD4Rc/y2PFOwt882jTYBbs4eSMxa6FUNCy49ktavcROp5jgMmmwZgzZ9hv94j X/e6copenp3Ey+UsiWX5uOeMBS0Y3GLJXHPnAGZBUW9e5YkcUp07JdoQy9w+ysFpGIcOlMc0oFS UuuW+MJXifwjjRtaNOrE79cKVCeTkF/7ExKqTlPEtY+G1tlhC+C2PJalO5N5YXmtyh0c0SgOoiv snBLx/8SB5/jEvagCj620+2PgBnRmO6d38WD3Qz691Br6r/yvK7oPswkleahMC0go9ESMkY4ZZ1 pT9cBHnYdh8uBnT/jqWNJcqnBiUCvoDV X-Google-Smtp-Source: AGHT+IGqhJzyDS4e04vMn1WyVytA3R0WpmSjXAbWRrFlxmWxFGHaT0ntvkzlA3YzSBZ0INS2vdnPeQ== X-Received: by 2002:a05:600c:3ca1:b0:434:9e1d:7626 with SMTP id 5b1f17b1804b1-434dded7366mr1195635e9.25.1733420501143; Thu, 05 Dec 2024 09:41:41 -0800 (PST) Received: from ta2.c.googlers.com.com (32.134.38.34.bc.googleusercontent.com. [34.38.134.32]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434da0d6961sm30318525e9.12.2024.12.05.09.41.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Dec 2024 09:41:40 -0800 (PST) From: Tudor Ambarus To: jassisinghbrar@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, peter.griffin@linaro.org, Tudor Ambarus Subject: [PATCH v3 1/3] dt-bindings: mailbox: add bindings for samsung,exynos Date: Thu, 5 Dec 2024 17:41:35 +0000 Message-ID: <20241205174137.190545-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.47.0.338.g60cca15819-goog In-Reply-To: <20241205174137.190545-1-tudor.ambarus@linaro.org> References: <20241205174137.190545-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bindings for the Samsung Exynos Mailbox Controller. Signed-off-by: Tudor Ambarus --- .../bindings/mailbox/samsung,exynos.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/samsung,exyno= s.yaml diff --git a/Documentation/devicetree/bindings/mailbox/samsung,exynos.yaml = b/Documentation/devicetree/bindings/mailbox/samsung,exynos.yaml new file mode 100644 index 000000000000..1fddec1fc64c --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/samsung,exynos.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/samsung,exynos.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Mailbox Controller + +maintainers: + - Tudor Ambarus + +description: | + The samsung exynos mailbox controller has 16 flag bits for hardware inte= rrupt + generation and a shared register for passing mailbox messages. When the + controller is used by the ACPM protocol the shared register is ignored a= nd + the mailbox controller acts as a doorbell. The controller just raises the + interrupt to the firmware after the ACPM protocol has written the messag= e to + SRAM. + +properties: + compatible: + const: google,gs101-acpm-mbox + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pclk + + interrupts: + description: IRQ line for the RX mailbox. + maxItems: 1 + + '#mbox-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - '#mbox-cells' + +additionalProperties: false + +examples: + # Doorbell mode. + - | + #include + #include + + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + ap2apm_mailbox: mailbox@17610000 { + compatible =3D "google,gs101-acpm-mbox"; + reg =3D <0x17610000 0x1000>; + clocks =3D <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>; + clock-names =3D "pclk"; + interrupts =3D ; + #mbox-cells =3D <1>; + }; + }; --=20 2.47.0.338.g60cca15819-goog From nobody Thu Dec 18 00:09:36 2025 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD27622578E for ; Thu, 5 Dec 2024 17:41:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733420506; cv=none; b=AoL03wMCnAkRdHoCp5sLO5nBeLs8d3LCNpbLkH6moN53VbkxdAtMky4I+43CsnsIC6gh8zLjVir6ffsxal4hSB84a9/9YaenMVN3FfbAn7M5ZDUDPzf3xyVDlGFxjYW7JxMtR3dh/DJ46j46I7lISWduAKsVZmBGkMsvhgumxhk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733420506; c=relaxed/simple; bh=BN8uQMRb85s772lE/MD9ObRCqzPRTvim4Eyu5bHJlkQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JIiiBmaDmIfAVpBHaHlQAH8qsWmpaTYqKAO2PzyHjpTV9fDWj80LHb0TTQas45AJ536iiDedl/XzTu+wBxglxzqsPaBmDfVpi5gp4cUxtb/19K3wwAr1rjrEQgDJ4igdBuvyis8HFlRRNRakTMbXKquvyPd58vrPfgsCMuwjOd4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=eYmP5Ydo; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="eYmP5Ydo" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-434a742481aso11829455e9.3 for ; Thu, 05 Dec 2024 09:41:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733420502; x=1734025302; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Wo6TX+bBHYFp5yEtuTvKYoGV7nlrucX5ZnLEJPkTV/E=; b=eYmP5YdownWMSJN5UzkdRAnTIUkv6OXxdZvA+E5yodMQPWNNEef854mJKmkHB4vdXl d9pfUlioKn6+uwELdcNg764EG5atUrErnfsAOwjY+pZuQ92u1Sg9y5d3q19smONLY4Az XHKderQ16BqgfcQyRT0+cP+UxCRbBNAj5MtMxgF6RKL3GYr7qj70qmwVuYwQl6NYiV10 n7CVmIPipwneJa4cH97XjdbWHbn89CJj/4VpJq1i4wVKgnzlbr9yt5hOwTIX2AibfFCS lppKNsByJT/deeTPM6Ka/LylW2u/iK5hG3gT1K3YCYgvKmSJzZcd241F8yOlRwfe872d YvRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733420502; x=1734025302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wo6TX+bBHYFp5yEtuTvKYoGV7nlrucX5ZnLEJPkTV/E=; b=uc/eiKOmSpp+QXdMmSCaVY+fe4CzbcBdg9iTLXlfRug571p6M2/o87pnnw94/+8Boz LMPyMFjbFOvDKbhvt9STw0jEyA+MpSPYCF0iYvSe2oMJggVCuqW7KW17I0U4Mqdkmyyv nDT1gl3mc5evU/CxU2RuDoCco0/gQ5FmKW8M1oL0w6tS5j/vhQw27GV3XAu8GHqMXgxQ 51Z2gaivqxIHnvEAwRh94VXYcEdY55NvD3T4TJAFEP1slBcwdZPE0/Lr/r/iUnTvVCN2 54TEZHOtFVWs+TUAwQuliAYxmJehHeDcrfsYcaLO1ayyGB8Q1/PYdcd3dH9w7g01OuGP Wtow== X-Gm-Message-State: AOJu0YyBCdcLoR8QeF4fBDUtNeTzlgoQWzr1EUWhIp9vu59KHjTQ6sgT hxFNd9LQ0+CfhCdzAmaHOM8XNly58nbaRHK1qEibbznKBBkHs5Kc3m/FBa73OyY= X-Gm-Gg: ASbGncsa99Lb1wS4waq9cu2tlIEG9JPmhVzAwo0PsGnZD/QfDwqI0WahS7Aq0kEJNoo cFxsa6VclektyItMdHkexxlcI5EIP9rR20BajU+xJiSZH4dE5bb08NlNhxQnuDMXSJNhJpg0fJe YOs249o/MkMJLW6YqyOrUdHYj2KacsUb05tVZsnPZtepLjizV3EquD4VtiIGUzH4LoXTS4hM1Ib +qEeBuejdYfyhQ5lni1onZ3msyxyZ5K3HPyJ1GNUmyHjBTDlHEZtRWQLpKvpWzSY1Bv8KoH156z baM1vXzXVz6DmOZmoKsjzBY9JK4vo8Fh X-Google-Smtp-Source: AGHT+IHb0o9dq8kY11HSiBExfA3eNeePmx2xXippa5MoXXeosok09IJCvD/BXrBGF6Agc4uVGD4lVQ== X-Received: by 2002:a05:600c:358f:b0:42c:de2f:da27 with SMTP id 5b1f17b1804b1-434ddeadeeemr1546605e9.2.1733420502047; Thu, 05 Dec 2024 09:41:42 -0800 (PST) Received: from ta2.c.googlers.com.com (32.134.38.34.bc.googleusercontent.com. [34.38.134.32]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434da0d6961sm30318525e9.12.2024.12.05.09.41.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Dec 2024 09:41:41 -0800 (PST) From: Tudor Ambarus To: jassisinghbrar@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, peter.griffin@linaro.org, Tudor Ambarus Subject: [PATCH v3 2/3] mailbox: add samsung exynos driver Date: Thu, 5 Dec 2024 17:41:36 +0000 Message-ID: <20241205174137.190545-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.47.0.338.g60cca15819-goog In-Reply-To: <20241205174137.190545-1-tudor.ambarus@linaro.org> References: <20241205174137.190545-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The samsung exynos mailbox controller has 16 flag bits for hardware interrupt generation and a shared register for passing mailbox messages. When the controller is used by the ACPM protocol the shared register is ignored and the mailbox controller acts as a doorbell. The controller just raises the interrupt to APM after the ACPM protocol has written the message to SRAM. Add support for the samsung exynos mailbox controller. Signed-off-by: Tudor Ambarus --- drivers/mailbox/Kconfig | 11 +++ drivers/mailbox/Makefile | 2 + drivers/mailbox/exynos-mailbox.c | 143 +++++++++++++++++++++++++++++++ 3 files changed, 156 insertions(+) create mode 100644 drivers/mailbox/exynos-mailbox.c diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 8ecba7fb999e..44b808c4d97f 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -36,6 +36,17 @@ config ARM_MHU_V3 that provides different means of transports: supported extensions will be discovered and possibly managed at probe-time. =20 +config EXYNOS_MBOX + tristate "Exynos Mailbox" + depends on ARCH_EXYNOS || COMPILE_TEST + help + Say Y here if you want to build the Samsung Exynos Mailbox controller + driver. The controller has 16 flag bits for hardware interrupt + generation and a shared register for passing mailbox messages. + When the controller is used by the ACPM protocol the shared register + is ignored and the mailbox controller acts as a doorbell that raises + the interrupt to the ACPM firmware. + config IMX_MBOX tristate "i.MX Mailbox" depends on ARCH_MXC || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 5f4f5b0ce2cc..86192b5c7c32 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -11,6 +11,8 @@ obj-$(CONFIG_ARM_MHU_V2) +=3D arm_mhuv2.o =20 obj-$(CONFIG_ARM_MHU_V3) +=3D arm_mhuv3.o =20 +obj-$(CONFIG_EXYNOS_MBOX) +=3D exynos-mailbox.o + obj-$(CONFIG_IMX_MBOX) +=3D imx-mailbox.o =20 obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) +=3D armada-37xx-rwtm-mailbox.o diff --git a/drivers/mailbox/exynos-mailbox.c b/drivers/mailbox/exynos-mail= box.c new file mode 100644 index 000000000000..6d4e9b3106b2 --- /dev/null +++ b/drivers/mailbox/exynos-mailbox.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2024 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EXYNOS_MBOX_MCUCTRL 0x0 /* Mailbox Control Register */ +#define EXYNOS_MBOX_INTCR0 0x24 /* Interrupt Clear Register 0 */ +#define EXYNOS_MBOX_INTMR0 0x28 /* Interrupt Mask Register 0 */ +#define EXYNOS_MBOX_INTSR0 0x2c /* Interrupt Status Register 0 */ +#define EXYNOS_MBOX_INTMSR0 0x30 /* Interrupt Mask Status Register 0 */ +#define EXYNOS_MBOX_INTGR1 0x40 /* Interrupt Generation Register 1 */ +#define EXYNOS_MBOX_INTMR1 0x48 /* Interrupt Mask Register 1 */ +#define EXYNOS_MBOX_INTSR1 0x4c /* Interrupt Status Register 1 */ +#define EXYNOS_MBOX_INTMSR1 0x50 /* Interrupt Mask Status Register 1 */ + +#define EXYNOS_MBOX_INTMR0_MASK GENMASK(15, 0) +#define EXYNOS_MBOX_INTGR1_MASK GENMASK(15, 0) + +#define EXYNOS_MBOX_CHAN_COUNT HWEIGHT32(EXYNOS_MBOX_INTGR1_MASK) + +/** + * struct exynos_mbox - driver's private data. + * @regs: mailbox registers base address. + * @mbox: pointer to the mailbox controller. + * @dev: pointer to the mailbox device. + * @pclk: pointer to the mailbox peripheral clock. + */ +struct exynos_mbox { + void __iomem *regs; + struct mbox_controller *mbox; + struct device *dev; + struct clk *pclk; +}; + +static int exynos_mbox_chan_index(struct mbox_chan *chan) +{ + struct mbox_controller *mbox =3D chan->mbox; + int i; + + for (i =3D 0; i < mbox->num_chans; i++) + if (chan =3D=3D &mbox->chans[i]) + return i; + return -EINVAL; +} + +static int exynos_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct exynos_mbox *exynos_mbox =3D dev_get_drvdata(chan->mbox->dev); + int index; + + index =3D exynos_mbox_chan_index(chan); + if (index < 0) + return index; + + writel_relaxed(BIT(index), exynos_mbox->regs + EXYNOS_MBOX_INTGR1); + + return 0; +} + +static const struct mbox_chan_ops exynos_mbox_chan_ops =3D { + .send_data =3D exynos_mbox_send_data, +}; + +static const struct of_device_id exynos_mbox_match[] =3D { + { .compatible =3D "google,gs101-acpm-mbox" }, + {}, +}; +MODULE_DEVICE_TABLE(of, exynos_mbox_match); + +static int exynos_mbox_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct exynos_mbox *exynos_mbox; + struct mbox_controller *mbox; + struct mbox_chan *chans; + int i; + + exynos_mbox =3D devm_kzalloc(dev, sizeof(*exynos_mbox), GFP_KERNEL); + if (!exynos_mbox) + return -ENOMEM; + + mbox =3D devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + chans =3D devm_kcalloc(dev, EXYNOS_MBOX_CHAN_COUNT, sizeof(*chans), + GFP_KERNEL); + if (!chans) + return -ENOMEM; + + exynos_mbox->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(exynos_mbox->regs)) + return PTR_ERR(exynos_mbox->regs); + + exynos_mbox->pclk =3D devm_clk_get_enabled(dev, "pclk"); + if (IS_ERR(exynos_mbox->pclk)) + return dev_err_probe(dev, PTR_ERR(exynos_mbox->pclk), + "Failed to enable clock.\n"); + + mbox->num_chans =3D EXYNOS_MBOX_CHAN_COUNT; + mbox->chans =3D chans; + mbox->dev =3D dev; + mbox->ops =3D &exynos_mbox_chan_ops; + + for (i =3D 0; i < EXYNOS_MBOX_CHAN_COUNT; i++) + chans[i].mbox =3D mbox; + + exynos_mbox->dev =3D dev; + exynos_mbox->mbox =3D mbox; + + platform_set_drvdata(pdev, exynos_mbox); + + /* Mask out all interrupts. We support just polling channels for now. */ + writel_relaxed(EXYNOS_MBOX_INTMR0_MASK, + exynos_mbox->regs + EXYNOS_MBOX_INTMR0); + + return devm_mbox_controller_register(dev, mbox); +} + +static struct platform_driver exynos_mbox_driver =3D { + .probe =3D exynos_mbox_probe, + .driver =3D { + .name =3D "exynos-acpm-mbox", + .of_match_table =3D of_match_ptr(exynos_mbox_match), + }, +}; +module_platform_driver(exynos_mbox_driver); + +MODULE_AUTHOR("Tudor Ambarus "); +MODULE_DESCRIPTION("Exynos mailbox driver"); +MODULE_LICENSE("GPL"); --=20 2.47.0.338.g60cca15819-goog From nobody Thu Dec 18 00:09:36 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69BCA226EFF for ; Thu, 5 Dec 2024 17:41:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733420506; cv=none; b=CUyrPM9pg8y+nR/UbaTkQIAyX/1kh7cBkXMhJQnECves4kYT7azGD6osGa9jb/N5JGNQIpiwsVJ/65EulBRaumRz4YOo9rpMiOq7srsxbXInMbWn4WslvIXWwvtYJuss+HIJwwBh8ooXaK5gtazW29oFyQAGTnvjbRnjuDRPBoU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733420506; c=relaxed/simple; bh=xXPiygVHodTqiKWiUOsE0uULVZtvJJ1/Xa366WcUIss=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eAH57PSLLK/NwS6xPRZb8fO8DZNhHt/3LMF5N2UtaP1dwSDKiEyo0Odeh+1VNL8eKjEfISqbDaYXylJ4uTEIBNvM0SLVGoxUeIIV1YIllIiMkPWFwL5wW8bigNKkcx6G+8BbyhnMOoMOCw0WwAS6xyq53imyMC+OhX5PJnCLACc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=hoCyBSCU; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hoCyBSCU" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-4349fb56260so8531625e9.3 for ; Thu, 05 Dec 2024 09:41:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733420503; x=1734025303; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jKhrlzK7pKMmsPY9TXNGvHHUZJEtDgIZ1kDt6TVOg0Y=; b=hoCyBSCUaa7B5i+frE52rQ8fgIzcpSk8Koqxe5fuGzIXJBy1emI+qFfO+8l3dS4i1A HeJSYgZ/RP8ibDf4Qrjn+8tQ3IKCc92UQqk1XwMGT5KBcXt2n7fL/txkL4Y8+xDi2825 hi5ElMVngRN9O8TgOEq+S68vSSchHUiwO/Mry9A6q4+ztnki3sl7o2e3t6g4dQnPEokG XrxfAkxpzxaycP5G3bD9pUqYAXJDVYW5Jsf4XzXuZt9/vYFEBwdak42HVeu7q/TRRquE /zJ+hxLR9ZzVmQX2J0zdB2Tk1CqwZuZ5eOMW6h1lKGWCzFrwQa8l8d3Txl/xYAhVyguU uB5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733420503; x=1734025303; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jKhrlzK7pKMmsPY9TXNGvHHUZJEtDgIZ1kDt6TVOg0Y=; b=BCCFwDeKLrdg233jXy0GgiZaQydY3eZ1+qJW4/FCp5BQugr+j5OTlTLwLjSTsKdxEu d6c1jYkOp5HzgK/jHfg0NsigaNmUJ2wQf1uwUAdsfMIq9bsLfCHCkHF4KQsT88HBnlya U76fG95jSP9lDEqBMqF89i8T6qpy16gvRDzgc0W6ZuJrrksk2l+EHrUPu19R/hSlJDgO 5Wa2NJHqAbEW6OGGBGCLzhHdjAZ7NbxfrlJZ82EWRmyqnuFH1nDIZGSFKbK3ClMrXLpE xkU71gAf9ahIGkoGMEl+fSOhhKxXb0VxB9EpLpGejFynS34wo4TB7nnSAtX9gsVA6FRo 5kIw== X-Gm-Message-State: AOJu0Yw3xbXodhoLdXK9az/IuHTUG5bJozT/MtGC174aOgzjtlyYVvbw WFgzfuAnocq4n6xabz21UqDTw3zx2qaIm+Nk3Flgj2EVhg1Ev7JBadnhoO/doRw= X-Gm-Gg: ASbGncu+SmJPVzZTmGd5stnqbiHFl8V22qdUykcmG02xRKTCxZKf8wkSduVhkxQSb9S FDNIAxbtlHFNi+W6Y6e2rmN80v9UxiUlVQsVVZPeWUujC5TN5JBGn2rwrGivtCF0KVctYaMWjnJ Ru2gfxiC90loBx4pV9POvwVZ0HkT9Rmu05Ttn3knYpVmCkJpmMcEYt7PSkPN6g413WqAGurI8i4 Y+e8ikY+0v1+HGDrnQCZyYKYno4NWOSoP0ydJEzmGrkJp0uaQK4Kt/z+J99rqGfvyARmDOTdWWD 3LOvDp40+aVxb76Q9f6dnYrPs8gNjQkw X-Google-Smtp-Source: AGHT+IETTIMwCAt1THUCSfAIoi1qf9ZFSIPgjGWfgvAXtjPszoHVRLgp6w2ts+qYW08bZrcEVzFXEQ== X-Received: by 2002:a05:600c:350a:b0:434:a7e3:db66 with SMTP id 5b1f17b1804b1-434ddecfe72mr1375775e9.26.1733420502746; Thu, 05 Dec 2024 09:41:42 -0800 (PST) Received: from ta2.c.googlers.com.com (32.134.38.34.bc.googleusercontent.com. [34.38.134.32]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434da0d6961sm30318525e9.12.2024.12.05.09.41.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Dec 2024 09:41:42 -0800 (PST) From: Tudor Ambarus To: jassisinghbrar@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, peter.griffin@linaro.org, Tudor Ambarus Subject: [PATCH v3 3/3] MAINTAINERS: add entry for samsung exynos mailbox driver Date: Thu, 5 Dec 2024 17:41:37 +0000 Message-ID: <20241205174137.190545-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.47.0.338.g60cca15819-goog In-Reply-To: <20241205174137.190545-1-tudor.ambarus@linaro.org> References: <20241205174137.190545-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add entry for the samsung exynos mailbox driver. Signed-off-by: Tudor Ambarus --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1e930c7a58b1..41a29d1d6e4d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3023,6 +3023,7 @@ F: drivers/*/*s3c24* F: drivers/*/*s3c64xx* F: drivers/*/*s5pv210* F: drivers/clocksource/samsung_pwm_timer.c +F: drivers/mailbox/exynos-mailbox.c F: drivers/memory/samsung/ F: drivers/pwm/pwm-samsung.c F: drivers/soc/samsung/ @@ -20712,6 +20713,14 @@ F: arch/arm64/boot/dts/exynos/exynos850* F: drivers/clk/samsung/clk-exynos850.c F: include/dt-bindings/clock/exynos850.h =20 +SAMSUNG EXYNOS MAILBOX DRIVER +M: Tudor Ambarus +L: linux-kernel@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/mailbox/samsung,exynos.yaml +F: drivers/mailbox/exynos-mailbox.c + SAMSUNG EXYNOS PSEUDO RANDOM NUMBER GENERATOR (RNG) DRIVER M: Krzysztof Kozlowski L: linux-crypto@vger.kernel.org --=20 2.47.0.338.g60cca15819-goog