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Thu, 05 Dec 2024 03:20:12 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com ([2001:b07:6474:ebbf:61a1:9bc8:52c6:3c2d]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa625eedcd0sm77505266b.87.2024.12.05.03.20.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Dec 2024 03:20:11 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v5 20/20] clk: imx8mn: support spread spectrum clock generation Date: Thu, 5 Dec 2024 12:17:55 +0100 Message-ID: <20241205111939.1796244-21-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241205111939.1796244-1-dario.binacchi@amarulasolutions.com> References: <20241205111939.1796244-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-imx8mn.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 588cebce6c9d..c61368e724f7 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -306,6 +306,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; void __iomem *base; + struct imx_pll14xx_ssc ssc_conf; int ret; =20 base =3D devm_platform_ioremap_resource(pdev, 0); @@ -338,9 +339,21 @@ static int imx8mn_clocks_probe(struct platform_device = *pdev) hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SY= S_PLL3_REF_SEL); =20 hws[IMX8MN_AUDIO_PLL1] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_AUDIO_PL= L1); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll1", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL1], &ssc_conf); + hws[IMX8MN_AUDIO_PLL2] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_AUDIO_PL= L2); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll2", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL2], &ssc_conf); + hws[IMX8MN_VIDEO_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_VIDEO_PLL= ); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "video_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_VIDEO_PLL], &ssc_conf); + hws[IMX8MN_DRAM_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_DRAM_PLL); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "dram_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_DRAM_PLL], &ssc_conf); + hws[IMX8MN_GPU_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_GPU_PLL); hws[IMX8MN_M7_ALT_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_M7_ALT_P= LL); hws[IMX8MN_ARM_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_ARM_PLL); --=20 2.43.0