From nobody Thu Dec 18 08:17:01 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFF231DAC81; Thu, 5 Dec 2024 10:51:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733395867; cv=none; b=A/CH9JwkkLR51U4K48MxYBByJo1LfXVi4b/pX8+yTai5mTGcu9YyHKsbZtqQ/pBlOKv7KLVmk0J6l87mjY+RtGA1GHY5wn52FORALbvlkm3oOEaEfSkYFYgZmyT2GPlsCe80K4XpXw7/EvoKkUHS/Q7Nk2+eps+0syl/P8xdqTQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733395867; c=relaxed/simple; bh=T1pU/ZNurOOJOF6gXMC/hxxVq6AHIC4AFrnNYuQI4sM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oHL6B8Elyey+YJX9dz5B3muLNxV2ODwVRgc2ZCeaWVGHXIkDc+uHkR7jLkaV2bHibXNgoU/x9wm5dTl5yQlXvA6O1UW4jOKFEixIpSjrEpfmPexkgjMwFA7F1kpUFRtXtsZ2M1k1wmAXpp2SyIKDcNCTc/lanzz/dvCanOfADn8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Kcg7KMJb; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Kcg7KMJb" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 4B5AonFC1747659 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 5 Dec 2024 04:50:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1733395849; bh=VxBfAidCZEpZfBvPJ7kpXgJ70sPB6hVOSGyHqW1x/Zo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Kcg7KMJb6dL89WRcBzF7/wTLAV7RkjSYi91u7pbT22PV+Ca0s2rfI0p3DgjL7d1I2 LIYb6jXGII054DjUgydrwGX7hEQHIUK1g1mUVuEPEzJK88oaKsiDQRFKN3yEEaq3a3 vvvSHUdm6WUu5Wh8GGcT/mGeFTKacbBvctX9fqEA= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4B5Aonnf022871; Thu, 5 Dec 2024 04:50:49 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 5 Dec 2024 04:50:49 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 5 Dec 2024 04:50:49 -0600 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.81]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4B5AofJr110686; Thu, 5 Dec 2024 04:50:46 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v4 1/4] arm64: dts: ti: Makefile: Fix typo "k3-j7200-evm-pcie1-ep.dtbo" Date: Thu, 5 Dec 2024 16:20:33 +0530 Message-ID: <20241205105041.749576-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241205105041.749576-1-s-vadapalli@ti.com> References: <20241205105041.749576-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The list of "dtbs" should contain the resultant "dtb" formed by applying the "dtbo" overlay on the base "dtb", rather than the "dtbo" itself. Hence, change "k3-j7200-evm-pcie1-ep.dtbo" to "k3-j7200-evm-pcie1-ep.dtb" in the list of "dtbs". Fixes: f43ec89bbc83 ("arm64: dts: ti: k3-j7200-evm: Add overlay for PCIE1 E= ndpoint Mode") Signed-off-by: Siddharth Vadapalli --- This patch has been newly introduced in this series. arch/arm64/boot/dts/ti/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index f71360f14f23..379bfa4425d4 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -230,7 +230,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ - k3-j7200-evm-pcie1-ep.dtbo \ + k3-j7200-evm-pcie1-ep.dtb \ k3-j721e-common-proc-board-infotainment.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ --=20 2.43.0 From nobody Thu Dec 18 08:17:01 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8CD11DD87C; Thu, 5 Dec 2024 10:51:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733395869; cv=none; b=sVDyYs6qpaP/hrnyznsyVWZ7jim/S7YFZFZ1euiZtDfph4LfP33yHf+L1Cto56nNcjhoACl/zDn259WThCED12tsiEcgG1SJ4FnFmhFAAFdDXFHX6QUvPda0q4VW4R3ThpYk6GSWkIXFqc+8zTHZ4oOv0RnLNJiPbSJUqUelKe0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733395869; c=relaxed/simple; bh=ARvnduVUYcy8RNNDTsHKz6NOUlGXZwr1ILNb0Ft9KWg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=To7Cseeb6h9ee7qiHrI5J4g5uzsTc1qMSGvYhB6NAzh17UHNCMx3hNpt2eEKde3A7Tx08t+ppVuqICnBbydsiZir8bUyeYs1lsD9/y2UafPRRBpoRbblILllsbCdy6+S8B2Y5ROlDQxVliQxXu+egMVtH4ZlAHyTnM9/0caVvhk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=WuQwMi9G; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="WuQwMi9G" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 4B5Aor6C1935941 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 5 Dec 2024 04:50:53 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1733395853; bh=BkpVXwWuotXxa9vkpl5KFFoSmocApd4ODUbu3hO56t8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=WuQwMi9G2tn9bHE8rmNKRlohI35zYJBdgnuxWADNJyMYAqGCwgvFm1pTOF4wna6J+ Hy9gEf8VVKfZa8QAqh6G/JiUr5Y/qSEdtyLwTGvLTRdyHtlktMobxc1FyBYwcSNPxK xlgxTKFDniWW2vueirR2l7BBLWs63gZS3o50xE5M= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 4B5AorlF093394 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Dec 2024 04:50:53 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 5 Dec 2024 04:50:52 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 5 Dec 2024 04:50:52 -0600 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.81]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4B5AofJs110686; Thu, 5 Dec 2024 04:50:49 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v4 2/4] arm64: dts: ti: k3-j721e-evm: Add overlay for PCIE1 Endpoint Mode Date: Thu, 5 Dec 2024 16:20:34 +0530 Message-ID: <20241205105041.749576-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241205105041.749576-1-s-vadapalli@ti.com> References: <20241205105041.749576-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add overlay to enable the PCIE1 instance of PCIe on J721E-EVM in Endpoint mode of operation. Additionally, in order to support both PCIE0 and PCIE1 in Endpoint Mode of operation, enable applying device-tree overlays on "k3-j721e-evm-pcie0-ep.dtb", thereby allowing the overlay for PCIE1 in Endpoint mode to be applied on the aforementioned DTB. Signed-off-by: Siddharth Vadapalli --- v3: https://lore.kernel.org/r/20241010100933.2492806-1-s-vadapalli@ti.com/ Changes since v3: - Rebased on next-20241204. v2: https://lore.kernel.org/r/20240222065733.1213434-1-s-vadapalli@ti.com/ Changes since v2: - Rebased patch on next-20241010. - Moved vendor specific property "ti,syscon-pcie-ctrl" to the end of the node. v1: https://lore.kernel.org/r/20240220105006.1056824-1-s-vadapalli@ti.com/ Changes since v1: - Created a new overlay for PCIE1 based on Andrew's suggestion at: https://lore.kernel.org/r/415ee6d4-fe26-4582-80f3-9b503d308fdf@ti.com/ - Updated Makefile to allow applying overlay on "k3-j721e-evm-pcie0-ep.dtb" arch/arm64/boot/dts/ti/Makefile | 5 ++ .../boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso | 53 +++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 379bfa4425d4..03bacbc589ee 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -107,6 +107,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-common-proc-board-i= nfotainment.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-gesi-exp-board.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-pcie0-ep.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-sk-csi2-dual-imx219.dtbo =20 @@ -200,6 +201,8 @@ k3-j721e-common-proc-board-infotainment-dtbs :=3D k3-j7= 21e-common-proc-board.dtb \ k3-j721e-common-proc-board-infotainment.dtbo k3-j721e-evm-pcie0-ep-dtbs :=3D k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo +k3-j721e-evm-pcie1-ep-dtbs :=3D k3-j721e-common-proc-board.dtb \ + k3-j721e-evm-pcie1-ep.dtbo k3-j721e-sk-csi2-dual-imx219-dtbs :=3D k3-j721e-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-board.dtb \ @@ -233,6 +236,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j7200-evm-pcie1-ep.dtb \ k3-j721e-common-proc-board-infotainment.dtb \ k3-j721e-evm-pcie0-ep.dtb \ + k3-j721e-evm-pcie1-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ k3-j784s4-evm-pcie0-pcie1-ep.dtb \ @@ -255,6 +259,7 @@ DTC_FLAGS_k3-am68-sk-base-board +=3D -@ DTC_FLAGS_k3-am69-sk +=3D -@ DTC_FLAGS_k3-j7200-common-proc-board +=3D -@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ +DTC_FLAGS_k3-j721e-evm-pcie0-ep +=3D -@ DTC_FLAGS_k3-j721e-sk +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ DTC_FLAGS_k3-j784s4-evm +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso b/arch/arm64= /boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso new file mode 100644 index 000000000000..a8cccdcf3e3b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with t= he + * J7 common processor board. + * + * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXC= PXEVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie1_rc { + status =3D "disabled"; +}; + +&cbass_main { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic500>; + + pcie1_ep: pcie-ep@2910000 { + compatible =3D "ti,j721e-pcie-ep"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + max-link-speed =3D <3>; + num-lanes =3D <2>; + power-domains =3D <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 240 1>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys =3D <&serdes1_pcie_link>; + phy-names =3D "pcie-phy"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>; + }; +}; --=20 2.43.0 From nobody Thu Dec 18 08:17:01 2025 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4A241D8DEE; Thu, 5 Dec 2024 10:51:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733395865; cv=none; b=M+NG6URTMP8yTv72YK1eEvSDJ/8Q7FGqUONcgZPm9ZyVCMG1f3Kfvwoy4dJ4yCbZ5W1LCc4m9+TDBTHA4kLePsdlRL2vfqXuV/WYHVHUa00b9Uad7L8LxYIq2yVnLlKqMI8VIWyQyCSpmb2RpuBhEWOWCn9kp1Kf/qWE6ZEBZtQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733395865; c=relaxed/simple; bh=o3ieSBuLIUvoCNqdC9u1DajH4Bo9TuXAc2/LRKL/FXQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iyjzDpQyrs6ou42GMnYNXLpIIRYOi1Rty38xN8p11XQOaucti1eGNS3SaLCGvMIgfugd3eZIDI9UhxjZshkiLTZxNzT9cIhRM3pNscbwMvMWa6rdPChw7rndfHRsf2ChqOhLQLRuzjbSG6tFUw2DcJ+bPGVtu57S3VWao8CIsEU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=s3MhXlHK; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="s3MhXlHK" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 4B5Aousl109477; Thu, 5 Dec 2024 04:50:56 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1733395856; bh=kJh7mGflOyZtSXF8dli4DDtwZI6kgrjEhoAo/ThCcW0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=s3MhXlHKnw5MJbAJCC+A6AIL6ougHA2SvcNtxVXe1hBlYqrPeB246YiqqqAmpPBj9 Eh7J5Q5L+gZHdVRZMU8fQ1Akc5pQlXfGMTXvq47GIq0lYZbObECEQgcm+0OC7maJxB X5j7PitQvj/0/VNgmNdp4XB039gzxyZahnnv0Xnw= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4B5Aouo1022898; Thu, 5 Dec 2024 04:50:56 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 5 Dec 2024 04:50:55 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 5 Dec 2024 04:50:55 -0600 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.81]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4B5AofJt110686; Thu, 5 Dec 2024 04:50:52 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v4 3/4] arm64: dts: ti: k3-am68-sk-base-board: Add overlay for PCIE1 Endpoint Mode Date: Thu, 5 Dec 2024 16:20:35 +0530 Message-ID: <20241205105041.749576-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241205105041.749576-1-s-vadapalli@ti.com> References: <20241205105041.749576-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add overlay to enable the PCIE1 instance of PCIe on AM68-SK-Base-Board in Endpoint mode of operation. PCIE1 on AM68-SK-Base-Board supports x2 Lane operation unlike its counterpart on J721S2-EVM which supports x1 Lane. Signed-off-by: Siddharth Vadapalli --- This patch has been newly introduced in this series. arch/arm64/boot/dts/ti/Makefile | 4 ++ .../ti/k3-am68-sk-base-board-pcie1-ep.dtso | 53 +++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.d= tso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 03bacbc589ee..04438f7136b8 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -113,6 +113,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-sk-csi2-dual-imx219= .dtbo =20 # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-sk-base-board.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-sk-base-board-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-common-proc-board.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-gesi-exp-board.dtbo k3-j721s2-evm-dtbs :=3D k3-j721s2-common-proc-board.dtb k3-j721s2-evm-gesi= -exp-board.dtbo @@ -193,6 +194,8 @@ k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo k3-am68-sk-base-board-csi2-dual-imx219-dtbs :=3D k3-am68-sk-base-board.dtb= \ k3-j721e-sk-csi2-dual-imx219.dtbo +k3-am68-sk-base-board-pcie1-ep-dtbs :=3D k3-am68-sk-base-board.dtb \ + k3-am68-sk-base-board-pcie1-ep.dtbo k3-am69-sk-csi2-dual-imx219-dtbs :=3D k3-am69-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j7200-evm-pcie1-ep-dtbs :=3D k3-j7200-common-proc-board.dtb \ @@ -232,6 +235,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ + k3-am68-sk-base-board-pcie1-ep.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ k3-j7200-evm-pcie1-ep.dtb \ k3-j721e-common-proc-board-infotainment.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso b/a= rch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso new file mode 100644 index 000000000000..455736e378cc --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with t= he + * AM68-SK board. + * + * AM68-SK Board Product Link: https://www.ti.com/tool/SK-AM68 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie1_rc { + status =3D "disabled"; +}; + +&cbass_main { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic500>; + + pcie1_ep: pcie-ep@2910000 { + compatible =3D "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + max-link-speed =3D <3>; + num-lanes =3D <2>; + power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 276 41>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys =3D <&serdes0_pcie_link>; + phy-names =3D "pcie-phy"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>; + }; +}; --=20 2.43.0 From nobody Thu Dec 18 08:17:01 2025 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9597B1DC1AB; Thu, 5 Dec 2024 10:51:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733395868; cv=none; b=IGisEE8CRe/GSplZ1aap4p1iBSb4QqxJn440r6p+qeHNbD3nyuJ9tSn0N6jo/AZiakw4n2lLqmcHbqbETyG77ixnr92A/g1nBhu+zN+fDl/4FKambKtq6Un1ZHZckysObzfolh7ThsWuEMAGpWcS5RJso4MtMODRC3Ud/2gALNo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733395868; c=relaxed/simple; bh=6AbsjSdianUyMbqF6fSEDjfYPCVgMtOCDY/e6aUkIPw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gsx1LThw/jOCG9Vpsw7/aBz+ZQhVXKVT4vuowjtGMiEVGv81GMTFmu22Ore8A/fnaABk5pKlV993N2cvGwkBozwezHjVTJoDvpPowHkShWhcmeJxfuBmleYKZSO8lQlqxNoHO9tbhjHopR+adCIJJo1mgMBHiXJCzu8uzB+xdTo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=c+C1wYAq; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="c+C1wYAq" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 4B5AoxYW109484; Thu, 5 Dec 2024 04:50:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1733395859; bh=9pjo2xI2NoMV+ws/SdQvbE1uUrLIcffRmbIgnflplOI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=c+C1wYAqvEmWXBmLgMQjzUYK7TGxlL2zeMdtfnI6edTrfhKJOvs4H+HrYdPA1ILEF EtQmIsX7ut+ezOZ++JcWp7xBI4RPOJxnZacqd/LGWYjSlamnihByYQ1pEugFuNUHFd iI5uVINjdv3f8zmrt2ZohuuuLVCfhF6gWfobGQrI= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 4B5AoxW5021313 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Dec 2024 04:50:59 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 5 Dec 2024 04:50:59 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 5 Dec 2024 04:50:59 -0600 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.81]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4B5AofJu110686; Thu, 5 Dec 2024 04:50:56 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v4 4/4] arm64: dts: ti: k3-am69-sk: Add overlay for PCIE0 Endpoint Mode Date: Thu, 5 Dec 2024 16:20:36 +0530 Message-ID: <20241205105041.749576-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241205105041.749576-1-s-vadapalli@ti.com> References: <20241205105041.749576-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add overlay to enable the PCIE0 instance of PCIe on AM69-SK in Endpoint mode of operation. Signed-off-by: Siddharth Vadapalli --- This patch has been newly introduced in this series. arch/arm64/boot/dts/ti/Makefile | 4 ++ .../boot/dts/ti/k3-am69-sk-pcie0-ep.dtso | 53 +++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 04438f7136b8..db5ae27467e7 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm.dtb =20 # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-pcie0-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo @@ -198,6 +199,8 @@ k3-am68-sk-base-board-pcie1-ep-dtbs :=3D k3-am68-sk-bas= e-board.dtb \ k3-am68-sk-base-board-pcie1-ep.dtbo k3-am69-sk-csi2-dual-imx219-dtbs :=3D k3-am69-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo +k3-am69-sk-pcie0-ep-dtbs :=3D k3-am69-sk.dtb \ + k3-am69-sk-pcie0-ep.dtbo k3-j7200-evm-pcie1-ep-dtbs :=3D k3-j7200-common-proc-board.dtb \ k3-j7200-evm-pcie1-ep.dtbo k3-j721e-common-proc-board-infotainment-dtbs :=3D k3-j721e-common-proc-boa= rd.dtb \ @@ -237,6 +240,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am68-sk-base-board-pcie1-ep.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ + k3-am69-sk-pcie0-ep.dtb \ k3-j7200-evm-pcie1-ep.dtb \ k3-j721e-common-proc-board-infotainment.dtb \ k3-j721e-evm-pcie0-ep.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso b/arch/arm64/b= oot/dts/ti/k3-am69-sk-pcie0-ep.dtso new file mode 100644 index 000000000000..9a5bcf282a9e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling PCIE0 instances of PCIe in Endpoint Configurati= on + * on AM69-SK. + * + * AM69-SK Product Link: https://www.ti.com/tool/SK-AM69 + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie0_rc { + status =3D "disabled"; +}; + +&cbass_main { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic500>; + + pcie0_ep: pcie-ep@2900000 { + compatible =3D "ti,j784s4-pcie-ep"; + reg =3D <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 332 0>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys =3D <&serdes1_pcie_link>; + phy-names =3D "pcie-phy"; + ti,syscon-pcie-ctrl =3D <&pcie0_ctrl 0x0>; + }; +}; --=20 2.43.0