From nobody Thu Dec 18 08:12:57 2025 Received: from mail-m127218.xmail.ntesmail.com (mail-m127218.xmail.ntesmail.com [115.236.127.218]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D4A61DD87C; Thu, 5 Dec 2024 14:05:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.236.127.218 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733407544; cv=none; b=nc5DSLre+FJsbHQlqr5vAf6vwo+NuqRl4y72T5Nb55T5thh7+Mqvh4NnLm0+1ux56TY2oMCM7C0DerU+oCbowLnKN3qvhi7pBz8tuTqtwMA8pqJRJLE9TC+/EDUCd9t+8dw9FUG30BPtkw0uSAP/eZ5WjfOjWb7lCgkqouAH9fo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733407544; c=relaxed/simple; bh=ztKqQuU4KCjQJjdRSBdTN6sXF9Y/8SDDL4APxpqvSwY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Q0oRhNjhzLg+QKMUoTj+shQjqO4oWH8RxvNRu3cEb7UKWiXFXMjjgIIilnER+iOh9CSrG5heURkeHqL/jLVD+1xQz1MUvKhtlRZl3Zfy82+lI5TMK7xX3VlPkxQBBBt6dGOsEbkNsbGb8FgTy7bxdyrbVmuEfxvtEHzKGU/3eyI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=anhxgR45; arc=none smtp.client-ip=115.236.127.218 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="anhxgR45" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 4cf7c95c; Thu, 5 Dec 2024 18:36:28 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Bjorn Helgaas , Conor Dooley , Krzysztof Kozlowski , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Shawn Lin , Simon Xue , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 1/6] dt-bindings: PCI: dwc: rockchip: Add rk3576 support Date: Thu, 5 Dec 2024 18:36:18 +0800 Message-Id: <20241205103623.878181-2-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241205103623.878181-1-kever.yang@rock-chips.com> References: <20241205103623.878181-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQ0hIGVZDGB4eGU5DThlCTB1WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a9396647c2a03afkunm4cf7c95c X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MRw6Qjo*KzIYMw0JHyMVCxgs Qg0aCRxVSlVKTEhISEJPQkNCT05MVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFMTEs3Bg++ DKIM-Signature: a=rsa-sha256; b=anhxgR45JOFGpKYa1kzJdcLz3u+TUdMFwNCxoA87+DdTw61fMspve3iNy1DjZNhpoUElFzHHaz82zHL/Z7AnKOKMpXZMAl5h37qDmi3Tli1Onw+YUAyoEGzB16SWA9y9CMV9CqPGeRf/zwOMOWkE2rdkuziEzOT1ib+2lh0C/Ic=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=HjmVk9gKLzWJyLcAvjRtiVX8Ir6tmlI7JsF/W31nlu4=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" rk3576 is using the same controller as rk3568. Signed-off-by: Kever Yang Acked-by: Conor Dooley Reviewed-by: Heiko Stuebner --- Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/= Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 550d8a684af3..5328ccad7130 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -26,6 +26,7 @@ properties: - const: rockchip,rk3568-pcie - items: - enum: + - rockchip,rk3576-pcie - rockchip,rk3588-pcie - const: rockchip,rk3568-pcie =20 --=20 2.25.1 From nobody Thu Dec 18 08:12:57 2025 Received: from mail-m49202.qiye.163.com (mail-m49202.qiye.163.com [45.254.49.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F9811D5AD4; Thu, 5 Dec 2024 10:36:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="V7FxV3IW" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 4cf7c967; Thu, 5 Dec 2024 18:36:29 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Conor Dooley , Detlev Casanova , Elaine Zhang , Finley Xiao , Krzysztof Kozlowski , Liang Chen , Rob Herring , Yifeng Zhao , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] dts: arm64: rockchip: Add rk3576 naneng combphy nodes Date: Thu, 5 Dec 2024 18:36:19 +0800 Message-Id: <20241205103623.878181-3-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241205103623.878181-1-kever.yang@rock-chips.com> References: <20241205103623.878181-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGkMeH1ZOQkpMSRhIQxhCGkpWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a939664827203afkunm4cf7c967 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Ogg6HAw5LjIfQg0RHy5JCxkd Hx5PCzdVSlVKTEhISEJPQkJLQk1JVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFJS0pLNwY+ DKIM-Signature: a=rsa-sha256; b=V7FxV3IWdqlMRwcrHv/JZXj4IxrNmMzuj8ZcM4AszMNfJgsMw2Opm2AqMxrkCI0yA3gXdga2/A53QjBUXQ8LicrvTNrkEM9I7iqrcpTy9Buz12pbzVQZ/6VbFDl4OTDXbMLbUzcbcH8fa9oJvHJF7rgxmNbY1vvzKMNbQVYbtDI=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=67jtnZdAqgZmsIdKecCH4vXI2Gu7dBBbAbO28nvPUW0=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" rk3576 has two naneng combo phy, - combophy0 is used for one of pcie and sata; - combophy is used for one of pcie, sata and usb3; Signed-off-by: Kever Yang --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index 436232ffe4d1..8938ec7c3bb4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1587,6 +1587,42 @@ uart11: serial@2afd0000 { status =3D "disabled"; }; =20 + combphy0_ps: phy@2b050000 { + compatible =3D "rockchip,rk3576-naneng-combphy"; + reg =3D <0x0 0x2b050000 0x0 0x100>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_REF_PCIE0_PHY>, + <&cru PCLK_PCIE2_COMBOPHY0>, + <&cru PCLK_PCIE0>; + clock-names =3D "refclk", "apbclk", "pipe_clk"; + assigned-clocks =3D <&cru CLK_REF_PCIE0_PHY>; + assigned-clock-rates =3D <100000000>; + resets =3D <&cru SRST_P_PCIE2_COMBOPHY0>, + <&cru SRST_PCIE0_PIPE_PHY>; + reset-names =3D "combphy-apb", "combphy"; + rockchip,pipe-grf =3D <&php_grf>; + rockchip,pipe-phy-grf =3D <&pipe_phy0_grf>; + status =3D "disabled"; + }; + + combphy1_psu: phy@2b060000 { + compatible =3D "rockchip,rk3576-naneng-combphy"; + reg =3D <0x0 0x2b060000 0x0 0x100>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_REF_PCIE1_PHY>, + <&cru PCLK_PCIE2_COMBOPHY1>, + <&cru PCLK_PCIE1>; + clock-names =3D "refclk", "apbclk", "pipe_clk"; + assigned-clocks =3D <&cru CLK_REF_PCIE1_PHY>; + assigned-clock-rates =3D <100000000>; + resets =3D <&cru SRST_P_PCIE2_COMBOPHY1>, + <&cru SRST_PCIE1_PIPE_PHY>; + reset-names =3D "combphy-apb", "combphy"; + rockchip,pipe-grf =3D <&php_grf>; + rockchip,pipe-phy-grf =3D <&pipe_phy1_grf>; + status =3D "disabled"; + }; + sram: sram@3ff88000 { compatible =3D "mmio-sram"; reg =3D <0x0 0x3ff88000 0x0 0x78000>; --=20 2.25.1 From nobody Thu Dec 18 08:12:57 2025 Received: from mail-m11871.qiye.163.com (mail-m11871.qiye.163.com [115.236.118.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00281219A83; Thu, 5 Dec 2024 12:58:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.236.118.71 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733403543; cv=none; b=ssGg8wdFGetWo7sziFRluxjzGI2zo+nYHk4Pa1QN7bcNROL6wAMsDgDItDU8iNKP8Rx5pmqgyKpzANGJVKHx4FkTzlFzfMhYWgZSIS1n7a3cNKBNw53BnFPwmKXabRLpyes6VgFtRd/eEfkwc4BjYvrXOpSURvr+78QFSpb2QVc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733403543; c=relaxed/simple; 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Thu, 5 Dec 2024 18:36:31 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Conor Dooley , Detlev Casanova , Elaine Zhang , Finley Xiao , Krzysztof Kozlowski , Liang Chen , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] dts: arm64: rockchip: Add rk3576 pcie nodes Date: Thu, 5 Dec 2024 18:36:20 +0800 Message-Id: <20241205103623.878181-4-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241205103623.878181-1-kever.yang@rock-chips.com> References: <20241205103623.878181-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQ0pKSFZMTE1JTUtOGBpLHUtWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a939664885503afkunm4cf7c96e X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6OVE6Txw*KjIvMw0OTCxPCxkv FxZPFB9VSlVKTEhISEJPQkJJT0lMVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFPQktCNwY+ DKIM-Signature: a=rsa-sha256; b=LQ3Q+qn60/AGQS3EAHD+WipqNSolNfA08BN5ZnVmYZNpJXptOAZfbqhhNJzM2p0ALfsyj9XliK+w2/0tI9AffDFJK55Js4U2f3jlzfvKmINAbxWzAnQ2RgqzkK5X+0MDRnJOU8Pzt2XQK7+UqOT10ScZqAHfhvogBlVnlkb6NH8=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=nOjqWSTi8dqRWSxylXoTbFPFNKc68E/UXp6mVZs9+qY=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" rk3576 has two pcie controller, both are pcie2x1 used with naneng-combphy. Signed-off-by: Kever Yang --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 111 +++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index 8938ec7c3bb4..888af56530e8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1016,6 +1016,117 @@ qos_npu_m1ro: qos@27f22100 { reg =3D <0x0 0x27f22100 0x0 0x20>; }; =20 + pcie0: pcie@2a200000 { + compatible =3D "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + bus-range =3D <0x0 0xf>; + clocks =3D <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, + <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, + <&cru CLK_PCIE0_AUX>; + + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "msi", "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + linux,pci-domain =3D <0>; + num-ib-windows =3D <8>; + num-viewport =3D <8>; + num-ob-windows =3D <2>; + max-link-speed =3D <2>; + num-lanes =3D <1>; + phys =3D <&combphy0_ps PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3576_PD_PHP>; + ranges =3D <0x00000800 0x0 0x20000000 0x0 0x20000000 0x0 0x00100000 + 0x81000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 + 0x82000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 + 0x83000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; + reg =3D <0x0 0x2a200000 0x0 0x00010000>, + <0x0 0x22000000 0x0 0x00400000>, + <0x0 0x20000000 0x0 0x00100000>; + reg-names =3D "apb", "dbi", "config"; + resets =3D <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names =3D "pipe", "p_pcie0"; + #address-cells =3D <3>; + #size-cells =3D <2>; + status =3D "disabled"; + + pcie0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + + pcie1: pcie@2a210000 { + compatible =3D "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x20 0x2f>; + clocks =3D <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, + <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, + <&cru CLK_PCIE1_AUX>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "msi", "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + linux,pci-domain =3D <0>; + num-ib-windows =3D <8>; + num-viewport =3D <8>; + num-ob-windows =3D <2>; + max-link-speed =3D <2>; + num-lanes =3D <1>; + phys =3D <&combphy1_psu PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3576_PD_SUBPHP>; + ranges =3D <0x00000800 0x0 0x21000000 0x0 0x21000000 0x0 0x00100000 + 0x81000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 + 0x82000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 + 0x83000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; + reg =3D <0x0 0x2a210000 0x0 0x00010000>, + <0x0 0x22400000 0x0 0x00400000>, + <0x0 0x21000000 0x0 0x00100000>; + reg-names =3D "apb", "dbi", "config"; + resets =3D <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names =3D "pipe", "p_pcie1"; + status =3D "disabled"; + + pcie1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + gmac0: ethernet@2a220000 { compatible =3D "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; reg =3D <0x0 0x2a220000 0x0 0x10000>; --=20 2.25.1 From nobody Thu Dec 18 08:12:57 2025 Received: from mail-m1283.netease.com (mail-m1283.netease.com [103.209.128.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5542919FA7C; Thu, 5 Dec 2024 20:46:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.209.128.3 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="S5upHDpT" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 4cf7c977; Thu, 5 Dec 2024 18:36:32 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Andy Yan , Chris Morgan , Conor Dooley , Dragan Simic , Jonas Karlman , Krzysztof Kozlowski , Rob Herring , Tim Lunn , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] dt-bindings: arm: rockchip: Sort for rk3568 evb Date: Thu, 5 Dec 2024 18:36:21 +0800 Message-Id: <20241205103623.878181-5-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241205103623.878181-1-kever.yang@rock-chips.com> References: <20241205103623.878181-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGkIeGlZNQ0IYGklLQ0tNTx1WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a9396648e1403afkunm4cf7c977 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MyI6GSo4TzIePw1LHywBCykR Ak5PCwhVSlVKTEhISEJPQkJIQ05OVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFKTU1NNwY+ DKIM-Signature: a=rsa-sha256; b=S5upHDpTU/ytg2ZlCKDCMoQAetXPJF6TcZAkkGFif//dAvtIVarzK+2j5cZq6PpLKQqi/FjIdoNsG4wWrGLegMzmzmsAb3oldnH3ZE+IsnkWfcfcLW7ljNI4jTTFwy/McjhqR5FJB6Jiv/2yLjfkw4xR9z1dTUsngrZHrUwdn4Q=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=PfQq9WN+stZDbpqU1A9I4SjMJ3Y//2WoaZdCqaDns9Q=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" The info for rk3568 should before rk3588. Signed-off-by: Kever Yang Acked-by: Conor Dooley --- .../devicetree/bindings/arm/rockchip.yaml | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 753199a12923..45ee4bf7c80c 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1006,6 +1006,16 @@ properties: - const: rockchip,rk3399-sapphire-excavator - const: rockchip,rk3399 =20 + - description: Rockchip RK3566 BOX Evaluation Demo board + items: + - const: rockchip,rk3566-box-demo + - const: rockchip,rk3566 + + - description: Rockchip RK3568 Evaluation board + items: + - const: rockchip,rk3568-evb1-v10 + - const: rockchip,rk3568 + - description: Rockchip RK3588 Evaluation board items: - const: rockchip,rk3588-evb1-v10 @@ -1099,16 +1109,6 @@ properties: - const: zkmagic,a95x-z2 - const: rockchip,rk3318 =20 - - description: Rockchip RK3566 BOX Evaluation Demo board - items: - - const: rockchip,rk3566-box-demo - - const: rockchip,rk3566 - - - description: Rockchip RK3568 Evaluation board - items: - - const: rockchip,rk3568-evb1-v10 - - const: rockchip,rk3568 - - description: Sinovoip RK3308 Banana Pi P2 Pro items: - const: sinovoip,rk3308-bpi-p2pro --=20 2.25.1 From nobody Thu Dec 18 08:12:57 2025 Received: from mail-m12796.qiye.163.com (mail-m12796.qiye.163.com [115.236.127.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC74F218ACA; Thu, 5 Dec 2024 12:58:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.236.127.96 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733403542; cv=none; b=OSMG8A50eaR3AZmojf3EhB2LVqeQgmro3YJvoHehD8diwDMmL+VaG6m6BAq8zonyUF6oHtJvVqllfzp6AHcTowf9EL/0MZdCoKIqJnOx8xapNWzKHlECuP8Uews+gYSlSO36/x1HrItebMT/G4fnomuDyb2i8a+zvQpAOv2/G7E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733403542; c=relaxed/simple; bh=sDabB6yRsc/ZhrL31a5xwV72EldOXfsBu6FBgKi9BuI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SYgyEolytz4/TOsvCpJlbDN76wwt1WGaNNi+IqLouNDhZBjJGpuZhsRmsH+1r+9Tbe2gek/GqEvG21a8IPhIUbYWeWmhAMKrZAK3AfN4ZPNLRAs5hXUCpp2NJMQdrXixaZZu2/zt8waVvNNxYoIXk0k+tnIp3A9wzH5Nf5/RAI8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=TgWTzXUW; arc=none smtp.client-ip=115.236.127.96 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="TgWTzXUW" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 4cf7c984; Thu, 5 Dec 2024 18:36:34 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Andy Yan , Chris Morgan , Conor Dooley , Dragan Simic , Jonas Karlman , Krzysztof Kozlowski , Rob Herring , Tim Lunn , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] dt-bindings: arm: rockchip: Add rk3576 evb1 board Date: Thu, 5 Dec 2024 18:36:22 +0800 Message-Id: <20241205103623.878181-6-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241205103623.878181-1-kever.yang@rock-chips.com> References: <20241205103623.878181-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQkwZSlYZSkgZHh1LHU4dTEJWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a93966493a703afkunm4cf7c984 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MQw6Cjo5NDIhCQ1PHyMvCxov Q0oaFElVSlVKTEhISEJPQkJOT09MVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFCSks3Bg++ DKIM-Signature: a=rsa-sha256; b=TgWTzXUWw2q2NR1exdJuZumgkZ5NCMH3DmjXnsIeD1vSiO+bRplQxnzbj4Xye0Ab0ww/JQx6xD8H/IovZDX17PhM21YM+wj7UDiELScbGeZ7oOOJ6QZKQVPdsnBjKrIoiw8wYWMKeg3YZq4S+Ww0JqXctphCF4VqS1/sDzGQuRM=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=NGkIEb4D9Pp+P1b6BLNVuyfPuE9svwhu6wtxLA9nH2s=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add device tree documentation for rk3576-evb1-v10. Signed-off-by: Kever Yang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 45ee4bf7c80c..b2681a45867b 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1016,6 +1016,11 @@ properties: - const: rockchip,rk3568-evb1-v10 - const: rockchip,rk3568 =20 + - description: Rockchip RK3576 Evaluation board + items: + - const: rockchip,rk3576-evb1-v10 + - const: rockchip,rk3576 + - description: Rockchip RK3588 Evaluation board items: - const: rockchip,rk3588-evb1-v10 --=20 2.25.1 From nobody Thu Dec 18 08:12:57 2025 Received: from ec2-44-216-146-169.compute-1.amazonaws.com (ec2-44-216-146-169.compute-1.amazonaws.com [44.216.146.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5A0421C164; Thu, 5 Dec 2024 16:19:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=44.216.146.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733415578; cv=none; b=WvWjOz3JLUsdUdjJ7TxdpghqTh2TqG1qyJ37jbTs4qN4p7UsCRw8C/C312Qo2K1cJEmtgYxayHYFJlhLnEC/dFENLMlO9hOD32es3cYqn9ca1J7aUvkzBHYKpq8uyxrKh8AelBF/eTYb2xbShzQ0XkB6LyEDnlNmiy7ypUJw4jY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733415578; c=relaxed/simple; bh=4lSwR6c5slD4UXI1AX9+doiZhNZ+ORzF+au/Stx3v/c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nZqFb6pyUDYAT+RUtVcFF/NrdLPv6fPTzuePNBSA73VDW7M+/IjzLC7rMFK0fVPiNQRf7B8x3hkDq/RM9T9TAsCMLCUiIFna+tF488Cdt+DdZpuHG4GlB5OGWIDcp13wbr0Fu0Dpu1N+pRKuNQj3rCcJsNlIdHOf9qtyS/yJYL4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=aoRSsbi1; arc=none smtp.client-ip=44.216.146.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="aoRSsbi1" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 4cf7c98a; Thu, 5 Dec 2024 18:36:35 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Kever Yang , Liang Chen , Alexey Charkov , Andy Yan , Chris Morgan , Conor Dooley , Detlev Casanova , Dragan Simic , FUKAUMI Naoki , Jonas Karlman , Krzysztof Kozlowski , Michael Riesch , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] arm64: dts: rockchip: Add rk3576 evb1 board Date: Thu, 5 Dec 2024 18:36:23 +0800 Message-Id: <20241205103623.878181-7-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241205103623.878181-1-kever.yang@rock-chips.com> References: <20241205103623.878181-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGkxPTlZLQkpDSxgYHhlMSR1WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a93966499e103afkunm4cf7c98a X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Mz46CAw4GjIfTg1ONSxICw8q PgxPCTxVSlVKTEhISEJPQkJMSE5DVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFKQktDTTcG DKIM-Signature: a=rsa-sha256; b=aoRSsbi1yzQ1bXaf03O68yN42GlR5XzoCeeow0VH/urn/nIddi1+k5g2F1ESjfXaJsfNc7t2xDe3veCXTD6tS0XAE++xg64zd9psk8GdHzTSp3qiF0TTs2i+np/y2XgUGT6BBStl8fXPgaVvbRWwBBgnQ9xL4OzNASmqN9XfUMI=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=ditLlhTjkjNRCcixBuOKOrzvGYf+/31GG3U3s4Axasw=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" RK3576 EVB1 board features: - Rockchip RK3576 - PMIC: RK806-2x2pcs+DiscretePower - RAM: LPDDR4/4x 2pcsx 32bit - ROM: eMMC5.1 + UFS - LAN x 2 - HDMI TX - SD card slot - PCIe2 slot Add support for pmic, eMMC, SD-card, ADC-KEY, PCIE and GMAC. NOTE: The board has a mux design for PCIe slot and USB3 host, and default state is switch to USB3, need to switch to PCIe side to enable the PCIe slot. Signed-off-by: Liang Chen Signed-off-by: Kever Yang --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3576-evb1-v10.dts | 699 ++++++++++++++++++ 2 files changed, 700 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 86cc418a2255..2e683d7eab58 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5.= dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-display-vz.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-io-expander.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-armsom-sige5.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-armsom-sige7.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-armsom-w3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-coolpi-cm5-evb.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/= boot/dts/rockchip/rk3576-evb1-v10.dts new file mode 100644 index 000000000000..2b18bc1a4b72 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -0,0 +1,699 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3576.dtsi" + +/ { + model =3D "Rockchip RK3576 EVB V10 Board"; + compatible =3D "rockchip,rk3576-evb1-v10", "rockchip,rk3576"; + + aliases { + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + }; + + chosen: chosen { + stdout-path =3D "serial0:1500000n8"; + }; + + adc_keys: adc-keys { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 1>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + vol-up-key { + label =3D "volume up"; + linux,code =3D ; + press-threshold-microvolt =3D <17000>; + }; + + vol-down-key { + label =3D "volume down"; + linux,code =3D ; + press-threshold-microvolt =3D <417000>; + }; + + menu-key { + label =3D "menu"; + linux,code =3D ; + press-threshold-microvolt =3D <890000>; + }; + + back-key { + label =3D "back"; + linux,code =3D ; + press-threshold-microvolt =3D <1235000>; + }; + }; + + leds: leds { + compatible =3D "gpio-leds"; + work_led: work { + gpios =3D <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc_sys: regulator-vcc5v0-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_device: regulator-vcc5v0-device { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + vin-supply =3D <&vcc_sys>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc_sys>; + }; + + vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_rtc_s5"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_sys>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v8_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_1v8_s3>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_3v3_s3>; + }; + + vcc_ufs_s0: regulator-vcc-ufs-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_ufs_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_sys>; + }; + + vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc1v8_ufs_vccq2_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_1v8_s3>; + }; + + vcc1v2_ufs_vccq_s0: regulator-vcc1v2-ufs-vccq-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc1v2_ufs_vccq_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + vin-supply =3D <&vcc_sys>; + }; + + vcc3v3_lcd_n: regulator-vcc3v3-lcd0-n { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio =3D <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc_3v3_s0>; + }; + + vcc3v3_pcie0: regulator-vcc3v3-pcie0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + gpios =3D <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <5000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc5v0_device>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_host_pwren>; + }; + + vbus5v0_typec: regulator-vbus5v0-typec { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbus5v0_typec"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc5v0_device>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_otg0_pwren>; + }; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big_s0>; +}; + +&combphy1_psu { + status =3D "okay"; +}; + +&gmac0 { + phy-mode =3D "rgmii-rxid"; + clock_in_out =3D "output"; + + snps,reset-gpio =3D <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us =3D <0 20000 100000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + + tx_delay =3D <0x21>; + + phy-handle =3D <&rgmii_phy0>; + status =3D "okay"; +}; + +&gmac1 { + phy-mode =3D "rgmii-rxid"; + clock_in_out =3D "output"; + + snps,reset-gpio =3D <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us =3D <0 20000 100000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <ð1m0_miim + ð1m0_tx_bus2 + ð1m0_rx_bus2 + ð1m0_rgmii_clk + ð1m0_rgmii_bus + ðm0_clk1_25m_out>; + + tx_delay =3D <0x20>; + + phy-handle =3D <&rgmii_phy1>; + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; + + rk806: pmic@23 { + compatible =3D "rockchip,rk806"; + reg =3D <0x23>; + + interrupt-parent =3D <&gpio0>; + interrupts =3D <6 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + system-power-controller; + + + vcc1-supply =3D <&vcc_sys>; + vcc2-supply =3D <&vcc_sys>; + vcc3-supply =3D <&vcc_sys>; + vcc4-supply =3D <&vcc_sys>; + vcc5-supply =3D <&vcc_sys>; + vcc6-supply =3D <&vcc_sys>; + vcc7-supply =3D <&vcc_sys>; + vcc8-supply =3D <&vcc_sys>; + vcc9-supply =3D <&vcc_sys>; + vcc10-supply =3D <&vcc_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc_sys>; + + gpio-controller; + #gpio-cells =3D <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun1"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun1"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun3"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun5"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun1"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun3"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun5"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt =3D <850000>; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_big_s0"; + regulator-enable-ramp-delay =3D <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_npu_s0"; + regulator-enable-ramp-delay =3D <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt =3D <850000>; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-init-microvolt =3D <750000>; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_gpu_s0"; + regulator-enable-ramp-delay =3D <400>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt =3D <750000>; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <800000>; + regulator-name =3D "vdd_logic_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pldo2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-boot-on; + regulator-min-microvolt =3D <837500>; + regulator-max-microvolt =3D <837500>; + regulator-name =3D "vdda0v75_hdmi_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdda_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + clocks =3D <&cru REFCLKO25M_GMAC0_OUT>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + clocks =3D <&cru REFCLKO25M_GMAC1_OUT>; + }; +}; + +&pinctrl { + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins =3D <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg0_pwren: usb-otg0-pwren { + rockchip,pins =3D <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdmmc { + max-frequency =3D <200000000>; + no-sdio; + no-mmc; + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&pcie1 { + reset-gpios =3D <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie0>; + status =3D "okay"; +}; + +&saradc { + status =3D "okay"; + vref-supply =3D <&vcca_1v8_s0>; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.25.1