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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6260888casm53371766b.133.2024.12.04.23.33.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 23:33:13 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 05 Dec 2024 07:33:12 +0000 Subject: [PATCH v3 1/8] dt-bindings: phy: samsung,usb3-drd-phy: add blank lines between DT properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241205-gs101-phy-lanes-orientation-phy-v3-1-32f721bed219@linaro.org> References: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> In-Reply-To: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar Cc: Peter Griffin , Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 In [1], Rob pointed out that we should really be separating properties with blank lines in between, which is universal style. Only where properties are booleans, empty lines are not required. Do so. Link: https://lore.kernel.org/all/20240711212359.GA3023490-robh@kernel.org/= [1] Reviewed-by: Peter Griffin Acked-by: Rob Herring (Arm) Signed-off-by: Andr=C3=A9 Draszik --- v3: * update subject line (Rob) * collect tags v2: * collect tags --- .../devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 15 +++++++++++= ++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yam= l b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 16321cdd4919..1f8b35917b11 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -83,14 +83,19 @@ properties: =20 pll-supply: description: Power supply for the USB PLL. + dvdd-usb20-supply: description: DVDD power supply for the USB 2.0 phy. + vddh-usb20-supply: description: VDDh power supply for the USB 2.0 phy. + vdd33-usb20-supply: description: 3.3V power supply for the USB 2.0 phy. + vdda-usbdp-supply: description: VDDa power supply for the USB DP phy. + vddh-usbdp-supply: description: VDDh power supply for the USB DP phy. =20 @@ -117,6 +122,7 @@ allOf: - description: Gate of control interface AXI clock - description: Gate of control interface APB clock - description: Gate of SCL APB clock + clock-names: items: - const: phy @@ -124,10 +130,13 @@ allOf: - const: ctrl_aclk - const: ctrl_pclk - const: scl_pclk + reg: minItems: 3 + reg-names: minItems: 3 + required: - reg-names - pll-supply @@ -149,6 +158,7 @@ allOf: clocks: minItems: 5 maxItems: 5 + clock-names: items: - const: phy @@ -156,8 +166,10 @@ allOf: - const: phy_utmi - const: phy_pipe - const: itp + reg: maxItems: 1 + reg-names: maxItems: 1 =20 @@ -174,12 +186,15 @@ allOf: clocks: minItems: 2 maxItems: 2 + clock-names: items: - const: phy - const: ref + reg: maxItems: 1 + reg-names: maxItems: 1 =20 --=20 2.47.0.338.g60cca15819-goog From nobody Thu Dec 18 08:06:22 2025 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E2DE1B218C for ; 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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6260888casm53371766b.133.2024.12.04.23.33.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 23:33:14 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 05 Dec 2024 07:33:13 +0000 Subject: [PATCH v3 2/8] dt-bindings: phy: samsung,usb3-drd-phy: gs101: require Type-C properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241205-gs101-phy-lanes-orientation-phy-v3-2-32f721bed219@linaro.org> References: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> In-Reply-To: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar Cc: Peter Griffin , Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 orientation-switch is the standard declaration to inform the Type-C mux layer that a remote-endpoint is capable of processing orientation change messages. The USB PHY on gs101 needs to be configured based on the orientation of the connector. For that the DTS needs a link between the phy's port and a TCPCi, and we'll need to inform the phy driver that it should handle the orientation (register a handler). Update the schema to enforce that by requiring the orientation-switch and port properties on gs101 (only). We disallow orientation-switch on all other supported platforms, since other versions of this phy (or its system integration) don't currently support or even need it. Even though this new required gs101 property is an ABI break, the intention for the driver is to behave as before if it's missing (meaning for gs101 it will work in SS mode in one orientation only). Other platforms are not affected. Reviewed-by: Peter Griffin Signed-off-by: Andr=C3=A9 Draszik --- v3: * update as per Rob's suggestion (I hope :-) v2: * squash original patches #2 and #3 * actually disallow orientation-switch on !gs101 (not just optional) (Conor) * update commit message to clarify that the intention for the driver is to work with old and new DTS (Conor) * collect tags foo --- Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yam= l b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 1f8b35917b11..27295acbba76 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -114,6 +114,8 @@ allOf: contains: const: google,gs101-usb31drd-phy then: + $ref: /schemas/usb/usb-switch.yaml# + properties: clocks: items: @@ -139,6 +141,8 @@ allOf: =20 required: - reg-names + - orientation-switch + - port - pll-supply - dvdd-usb20-supply - vddh-usb20-supply @@ -198,7 +202,7 @@ allOf: reg-names: maxItems: 1 =20 -additionalProperties: false +unevaluatedProperties: false =20 examples: - | --=20 2.47.0.338.g60cca15819-goog From nobody Thu Dec 18 08:06:22 2025 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D846B1B3920 for ; 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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6260888casm53371766b.133.2024.12.04.23.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 23:33:14 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 05 Dec 2024 07:33:14 +0000 Subject: [PATCH v3 3/8] phy: exynos5-usbdrd: convert to dev_err_probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241205-gs101-phy-lanes-orientation-phy-v3-3-32f721bed219@linaro.org> References: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> In-Reply-To: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar Cc: Peter Griffin , Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Krzysztof Kozlowski X-Mailer: b4 0.13.0 dev_err_probe() exists to simplify code. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Peter Griffin Signed-off-by: Andr=C3=A9 Draszik --- v2: * collect tags --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index c421b495eb0f..ceae4b47cece 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -1725,10 +1725,9 @@ static int exynos5_usbdrd_phy_probe(struct platform_= device *pdev) =20 reg_pmu =3D syscon_regmap_lookup_by_phandle(dev->of_node, "samsung,pmu-syscon"); - if (IS_ERR(reg_pmu)) { - dev_err(dev, "Failed to lookup PMU regmap\n"); - return PTR_ERR(reg_pmu); - } + if (IS_ERR(reg_pmu)) + return dev_err_probe(dev, PTR_ERR(reg_pmu), + "Failed to lookup PMU regmap\n"); =20 /* * Exynos5420 SoC has multiple channels for USB 3.0 PHY, with @@ -1759,10 +1758,9 @@ static int exynos5_usbdrd_phy_probe(struct platform_= device *pdev) for (i =3D 0; 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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6260888casm53371766b.133.2024.12.04.23.33.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 23:33:15 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 05 Dec 2024 07:33:15 +0000 Subject: [PATCH v3 4/8] phy: exynos5-usbdrd: fix EDS distribution tuning (gs101) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241205-gs101-phy-lanes-orientation-phy-v3-4-32f721bed219@linaro.org> References: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> In-Reply-To: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar Cc: Peter Griffin , Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 This code's intention is to configure lane0 and lane2 tunings, but for lane2 there is a typo and it ends up tuning something else. Fix the typo, as it doesn't appear to make sense to apply different tunings for lane0 vs lane2. The same typo appears to exist in the bootloader, hence we restore the original value in the typo'd registers as well. This can be removed once / if the bootloader is updated. Note that this is incorrect in the downstream driver as well - the values had been copied from there. Reviewed-by: Peter Griffin Tested-by: Peter Griffin Signed-off-by: Andr=C3=A9 Draszik --- v2: * collect tags --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index ceae4b47cece..2a724d362c2d 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -1510,8 +1510,11 @@ static const struct exynos5_usbdrd_phy_tuning gs101_= tunes_pipe3_preinit[] =3D { PHY_TUNING_ENTRY_PMA(0x09e0, -1, 0x00), PHY_TUNING_ENTRY_PMA(0x09e4, -1, 0x36), PHY_TUNING_ENTRY_PMA(0x1e7c, -1, 0x06), - PHY_TUNING_ENTRY_PMA(0x1e90, -1, 0x00), - PHY_TUNING_ENTRY_PMA(0x1e94, -1, 0x36), + PHY_TUNING_ENTRY_PMA(0x19e0, -1, 0x00), + PHY_TUNING_ENTRY_PMA(0x19e4, -1, 0x36), + /* fix bootloader bug */ + PHY_TUNING_ENTRY_PMA(0x1e90, -1, 0x02), + PHY_TUNING_ENTRY_PMA(0x1e94, -1, 0x0b), /* improve LVCC */ PHY_TUNING_ENTRY_PMA(0x08f0, -1, 0x30), PHY_TUNING_ENTRY_PMA(0x18f0, -1, 0x30), --=20 2.47.0.338.g60cca15819-goog From nobody Thu Dec 18 08:06:22 2025 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA6191B6CF0 for ; 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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6260888casm53371766b.133.2024.12.04.23.33.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 23:33:15 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 05 Dec 2024 07:33:16 +0000 Subject: [PATCH v3 5/8] phy: exynos5-usbdrd: gs101: ensure power is gated to SS phy in phy_exit() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241205-gs101-phy-lanes-orientation-phy-v3-5-32f721bed219@linaro.org> References: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> In-Reply-To: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar Cc: Peter Griffin , Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , stable@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.13.0 We currently don't gate the power to the SS phy in phy_exit(). Shuffle the code slightly to ensure the power is gated to the SS phy as well. Fixes: 32267c29bc7d ("phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo = phy (HS & SS)") CC: stable@vger.kernel.org # 6.11+ Reviewed-by: Krzysztof Kozlowski Reviewed-by: Peter Griffin Signed-off-by: Andr=C3=A9 Draszik --- v2: * add cc-stable and fixes tags (Krzysztof) * collect tags --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index 2a724d362c2d..c1ce6fdeef31 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -1296,14 +1296,17 @@ static int exynos5_usbdrd_gs101_phy_exit(struct phy= *phy) struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); int ret; =20 + if (inst->phy_cfg->id =3D=3D EXYNOS5_DRDPHY_UTMI) { + ret =3D exynos850_usbdrd_phy_exit(phy); + if (ret) + return ret; + } + + exynos5_usbdrd_phy_isol(inst, true); + if (inst->phy_cfg->id !=3D EXYNOS5_DRDPHY_UTMI) return 0; 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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6260888casm53371766b.133.2024.12.04.23.33.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 23:33:16 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 05 Dec 2024 07:33:17 +0000 Subject: [PATCH v3 6/8] phy: exynos5-usbdrd: gs101: configure SS lanes based on orientation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241205-gs101-phy-lanes-orientation-phy-v3-6-32f721bed219@linaro.org> References: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> In-Reply-To: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar Cc: Peter Griffin , Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 USB SS lanes need to be configured based on the connector orientation - at most two lanes will be in use for USB (and the remaining two for alternate modes like DP). For the USB link to come up in SS, the lane configuration registers have to be programmed accordingly. While we still need a way to be notified of the actual connector orientation and then reprogram the registers accordingly (at the moment the configuration happens just once during phy_init() and never again), we can prepare the code doing the configuration to take the orientation into account. Do so. Note: the mutex is needed to synchronize this with the upcoming connector orientation callback. Reviewed-by: Peter Griffin Tested-by: Peter Griffin Signed-off-by: Andr=C3=A9 Draszik --- v2: * collect tags * replace #include typec_mux.h with typec.h, and move the former into next patch (Peter) * commit message typo (Peter) --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 72 ++++++++++++++++++++++------= ---- 1 file changed, 51 insertions(+), 21 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index c1ce6fdeef31..206483c7ca55 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -23,6 +23,7 @@ #include #include #include +#include =20 /* Exynos USB PHY registers */ #define EXYNOS5_FSEL_9MHZ6 0x0 @@ -209,6 +210,10 @@ =20 #define EXYNOS9_PMA_USBDP_CMN_REG00B8 0x02e0 #define CMN_REG00B8_LANE_MUX_SEL_DP GENMASK(3, 0) +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE3 BIT(3) +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE2 BIT(2) +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE1 BIT(1) +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE0 BIT(0) =20 #define EXYNOS9_PMA_USBDP_CMN_REG01C0 0x0700 #define CMN_REG01C0_ANA_LCPLL_LOCK_DONE BIT(7) @@ -383,11 +388,13 @@ struct exynos5_usbdrd_phy_drvdata { * @clks: clocks for register access * @core_clks: core clocks for phy (ref, pipe3, utmi+, ITP, etc. as requir= ed) * @drv_data: pointer to SoC level driver data structure + * @phy_mutex: mutex protecting phy_init/exit & TCPC callbacks * @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY * instances each with its 'phy' and 'phy_cfg'. * @extrefclk: frequency select settings when using 'separate * reference clocks' for SS and HS operations * @regulators: regulators for phy + * @orientation: TypeC connector orientation - normal or flipped */ struct exynos5_usbdrd_phy { struct device *dev; @@ -397,6 +404,7 @@ struct exynos5_usbdrd_phy { struct clk_bulk_data *clks; struct clk_bulk_data *core_clks; const struct exynos5_usbdrd_phy_drvdata *drv_data; + struct mutex phy_mutex; struct phy_usb_instance { struct phy *phy; u32 index; @@ -406,6 +414,8 @@ struct exynos5_usbdrd_phy { } phys[EXYNOS5_DRDPHYS_NUM]; u32 extrefclk; struct regulator_bulk_data *regulators; + + enum typec_orientation orientation; }; =20 static inline @@ -647,22 +657,38 @@ exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel(struct ex= ynos5_usbdrd_phy *phy_drd) /* lane configuration: USB on all lanes */ reg =3D readl(regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8); reg &=3D ~CMN_REG00B8_LANE_MUX_SEL_DP; - writel(reg, regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8); - /* - * FIXME: below code supports one connector orientation only. It needs - * updating once we can receive connector events. + * USB on lanes 0 & 1 in normal mode, or 2 & 3 if reversed, DP on the + * other ones. */ + reg |=3D FIELD_PREP(CMN_REG00B8_LANE_MUX_SEL_DP, + ((phy_drd->orientation =3D=3D TYPEC_ORIENTATION_NORMAL) + ? (CMN_REG00B8_LANE_MUX_SEL_DP_LANE3 + | CMN_REG00B8_LANE_MUX_SEL_DP_LANE2) + : (CMN_REG00B8_LANE_MUX_SEL_DP_LANE1 + | CMN_REG00B8_LANE_MUX_SEL_DP_LANE0))); + writel(reg, regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8); + /* override of TX receiver detector and comparator: lane 1 */ reg =3D readl(regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0413); - reg &=3D ~TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN; - reg &=3D ~TRSV_REG0413_OVRD_LN1_TX_RXD_EN; + if (phy_drd->orientation =3D=3D TYPEC_ORIENTATION_NORMAL) { + reg &=3D ~TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN; + reg &=3D ~TRSV_REG0413_OVRD_LN1_TX_RXD_EN; + } else { + reg |=3D TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN; + reg |=3D TRSV_REG0413_OVRD_LN1_TX_RXD_EN; + } writel(reg, regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0413); =20 /* lane 3 */ reg =3D readl(regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0813); - reg |=3D TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN; - reg |=3D TRSV_REG0813_OVRD_LN3_TX_RXD_EN; + if (phy_drd->orientation =3D=3D TYPEC_ORIENTATION_NORMAL) { + reg |=3D TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN; + reg |=3D TRSV_REG0813_OVRD_LN3_TX_RXD_EN; + } else { + reg &=3D ~TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN; + reg &=3D ~TRSV_REG0813_OVRD_LN3_TX_RXD_EN; + } writel(reg, regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0813); } =20 @@ -700,21 +726,18 @@ exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock(struct = exynos5_usbdrd_phy *phy_drd int err; =20 err =3D readl_poll_timeout( - phy_drd->reg_pma + EXYNOS9_PMA_USBDP_TRSV_REG03C3, - reg, (reg & locked) =3D=3D locked, sleep_us, timeout_us); - if (!err) - return; - - dev_err(phy_drd->dev, - "timed out waiting for CDR lock (l0): %#.8x, retrying\n", reg); - - /* based on cable orientation, this might be on the other phy port */ - err =3D readl_poll_timeout( - phy_drd->reg_pma + EXYNOS9_PMA_USBDP_TRSV_REG07C3, + /* lane depends on cable orientation */ + (phy_drd->reg_pma + + ((phy_drd->orientation =3D=3D TYPEC_ORIENTATION_NORMAL) + ? EXYNOS9_PMA_USBDP_TRSV_REG03C3 + : EXYNOS9_PMA_USBDP_TRSV_REG07C3)), reg, (reg & locked) =3D=3D locked, sleep_us, timeout_us); if (err) dev_err(phy_drd->dev, - "timed out waiting for CDR lock (l2): %#.8x\n", reg); + "timed out waiting for CDR(l%d) lock: %#.8x\n", + ((phy_drd->orientation =3D=3D TYPEC_ORIENTATION_NORMAL) + ? 0 + : 2), reg); } =20 static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) @@ -1184,7 +1207,8 @@ static int exynos850_usbdrd_phy_init(struct phy *phy) return ret; =20 /* UTMI or PIPE3 specific init */ - inst->phy_cfg->phy_init(phy_drd); + scoped_guard(mutex, &phy_drd->phy_mutex) + inst->phy_cfg->phy_init(phy_drd); =20 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); =20 @@ -1203,6 +1227,8 @@ static int exynos850_usbdrd_phy_exit(struct phy *phy) if (ret) return ret; =20 + guard(mutex)(&phy_drd->phy_mutex); + /* Set PHY clock and control HS PHY */ reg =3D readl(regs_base + EXYNOS850_DRD_UTMI); reg &=3D ~(UTMI_DP_PULLDOWN | UTMI_DM_PULLDOWN); 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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6260888casm53371766b.133.2024.12.04.23.33.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 23:33:16 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 05 Dec 2024 07:33:18 +0000 Subject: [PATCH v3 7/8] phy: exynos5-usbdrd: subscribe to orientation notifier if required Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241205-gs101-phy-lanes-orientation-phy-v3-7-32f721bed219@linaro.org> References: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> In-Reply-To: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar Cc: Peter Griffin , Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 gs101's SS phy needs to be configured differently based on the connector orientation, as the SS link can only be established if the mux is configured correctly. The code to handle programming of the mux is in place already, this commit now adds the missing pieces to subscribe to the Type-C orientation switch event. Note that for this all to work we rely on the USB controller re-initialising us. It should invoke our .exit() upon cable unplug, and during cable plug we'll receive the orientation event after which we expect our .init() to be called. Above reinitialisation happens if the DWC3 controller can enter runtime suspend automatically. For the DWC3 driver, this is an opt-in: echo auto > /sys/devices/.../11110000.usb/power/control Once done, things work as long as the UDC is not bound as otherwise it stays busy because it doesn't cancel / stop outstanding TRBs. For now we have to manually unbind the UDC in that case: echo "" > sys/kernel/config/usb_gadget/.../UDC Note that if the orientation-switch property is missing from the DT, the code will behave as before this commit (meaning for gs101 it will work in SS mode in one orientation only). Other platforms are not affected either way. Signed-off-by: Andr=C3=A9 Draszik --- v3: * drop init to -1 of phy_drd->orientation (Vinod) * avoid #ifdef and switch to normal conditional IS_ENABLED() for CONFIG_TYPEC v2: * move #include typec_mux.h from parent patch into this one (Peter) IS_ENABLED(CONFIG_TYPEC) --- drivers/phy/samsung/Kconfig | 1 + drivers/phy/samsung/phy-exynos5-usbdrd.c | 56 ++++++++++++++++++++++++++++= ++++ 2 files changed, 57 insertions(+) diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig index f10afa3d7ff5..fc7bd1088576 100644 --- a/drivers/phy/samsung/Kconfig +++ b/drivers/phy/samsung/Kconfig @@ -80,6 +80,7 @@ config PHY_EXYNOS5_USBDRD tristate "Exynos5 SoC series USB DRD PHY driver" depends on (ARCH_EXYNOS && OF) || COMPILE_TEST depends on HAS_IOMEM + depends on TYPEC || (TYPEC=3Dn && COMPILE_TEST) depends on USB_DWC3_EXYNOS select GENERIC_PHY select MFD_SYSCON diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index 206483c7ca55..6dcc3c80c1d2 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -24,6 +24,7 @@ #include #include #include +#include =20 /* Exynos USB PHY registers */ #define EXYNOS5_FSEL_9MHZ6 0x0 @@ -394,6 +395,7 @@ struct exynos5_usbdrd_phy_drvdata { * @extrefclk: frequency select settings when using 'separate * reference clocks' for SS and HS operations * @regulators: regulators for phy + * @sw: TypeC orientation switch handle * @orientation: TypeC connector orientation - normal or flipped */ struct exynos5_usbdrd_phy { @@ -415,6 +417,7 @@ struct exynos5_usbdrd_phy { u32 extrefclk; struct regulator_bulk_data *regulators; =20 + struct typec_switch_dev *sw; enum typec_orientation orientation; }; =20 @@ -1400,6 +1403,55 @@ static int exynos5_usbdrd_phy_clk_handle(struct exyn= os5_usbdrd_phy *phy_drd) return 0; } =20 +static int exynos5_usbdrd_orien_sw_set(struct typec_switch_dev *sw, + enum typec_orientation orientation) +{ + struct exynos5_usbdrd_phy *phy_drd =3D typec_switch_get_drvdata(sw); + + scoped_guard(mutex, &phy_drd->phy_mutex) + phy_drd->orientation =3D orientation; + + return 0; +} + +static void exynos5_usbdrd_orien_switch_unregister(void *data) +{ + struct exynos5_usbdrd_phy *phy_drd =3D data; + + typec_switch_unregister(phy_drd->sw); +} + +static int exynos5_usbdrd_setup_notifiers(struct exynos5_usbdrd_phy *phy_d= rd) +{ + int ret; + + if (!IS_ENABLED(CONFIG_TYPEC)) + return 0; + + if (device_property_present(phy_drd->dev, "orientation-switch")) { + struct typec_switch_desc sw_desc =3D { }; + + sw_desc.drvdata =3D phy_drd; + sw_desc.fwnode =3D dev_fwnode(phy_drd->dev); + sw_desc.set =3D exynos5_usbdrd_orien_sw_set; + + phy_drd->sw =3D typec_switch_register(phy_drd->dev, &sw_desc); + if (IS_ERR(phy_drd->sw)) + return dev_err_probe(phy_drd->dev, + PTR_ERR(phy_drd->sw), + "Failed to register TypeC orientation switch\n"); + + ret =3D devm_add_action_or_reset(phy_drd->dev, + exynos5_usbdrd_orien_switch_unregister, + phy_drd); + if (ret) + return dev_err_probe(phy_drd->dev, ret, + "Failed to register TypeC orientation devm action\n"); + } + + return 0; +} + static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] =3D { { .id =3D EXYNOS5_DRDPHY_UTMI, @@ -1789,6 +1841,10 @@ static int exynos5_usbdrd_phy_probe(struct platform_= device *pdev) if (ret) return dev_err_probe(dev, ret, "failed to get regulators\n"); =20 + ret =3D exynos5_usbdrd_setup_notifiers(phy_drd); + if (ret) + return ret; + dev_vdbg(dev, "Creating usbdrd_phy phy\n"); =20 for (i =3D 0; i < EXYNOS5_DRDPHYS_NUM; i++) { --=20 2.47.0.338.g60cca15819-goog From nobody Thu Dec 18 08:06:22 2025 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 878F81BC9EE for ; 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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6260888casm53371766b.133.2024.12.04.23.33.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 23:33:17 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 05 Dec 2024 07:33:19 +0000 Subject: [PATCH v3 8/8] phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241205-gs101-phy-lanes-orientation-phy-v3-8-32f721bed219@linaro.org> References: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> In-Reply-To: <20241205-gs101-phy-lanes-orientation-phy-v3-0-32f721bed219@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar Cc: Peter Griffin , Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 To make USB runtime suspend work when a UDC has been bound, the phy needs to inform the USBDRD controller (DWC3) that Vbus and bvalid are gone, so that it can in turn raise the respective gadget interrupt with event =3D=3D DWC3_DEVICE_EVENT_DISCONNECT, which will cause the USB stack to clean up, allowing DWC3 to enter runtime suspend. On e850 and gs101 this isn't working, as the respective signals are not directly connected, and instead this driver uses override bits in the PHY IP to set those signals. It currently forcefully sets them to 'on', so the above mentioned interrupt will not be raised, preventing runtime suspend. To detect that state, update this driver to act on the TCPC's orientation signal - when orientation =3D=3D NONE, Vbus is gone and we can clear the respective bits. Similarly, for other orientation values we re-enable them. This makes runtime suspend work on platforms with a TCPC (like Pixel6), while keeping compatibility with platforms without (e850-96). With runtime suspend working, USB-C cable orientation detection now also fully works on such platforms, and the link comes up as Superspeed as expected irrespective of the cable orientation and whether UDC / gadget are configured and active. Signed-off-by: Andr=C3=A9 Draszik --- v3: * update exynos5_usbdrd_orien_sw_set() to not test against previous orientation --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 50 +++++++++++++++++++++++++++-= ---- 1 file changed, 42 insertions(+), 8 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index 6dcc3c80c1d2..ae42e299ba42 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -1137,13 +1137,15 @@ static void exynos850_usbdrd_utmi_init(struct exyno= s5_usbdrd_phy *phy_drd) reg |=3D LINKCTRL_BUS_FILTER_BYPASS(0xf); writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); =20 - reg =3D readl(regs_base + EXYNOS850_DRD_UTMI); - reg |=3D UTMI_FORCE_BVALID | UTMI_FORCE_VBUSVALID; - writel(reg, regs_base + EXYNOS850_DRD_UTMI); - - reg =3D readl(regs_base + EXYNOS850_DRD_HSP); - reg |=3D HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL; - writel(reg, regs_base + EXYNOS850_DRD_HSP); + if (!phy_drd->sw) { + reg =3D readl(regs_base + EXYNOS850_DRD_UTMI); + reg |=3D UTMI_FORCE_BVALID | UTMI_FORCE_VBUSVALID; + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + reg =3D readl(regs_base + EXYNOS850_DRD_HSP); + reg |=3D HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL; + writel(reg, regs_base + EXYNOS850_DRD_HSP); + } =20 reg =3D readl(regs_base + EXYNOS850_DRD_SSPPLLCTL); reg &=3D ~SSPPLLCTL_FSEL; @@ -1407,9 +1409,41 @@ static int exynos5_usbdrd_orien_sw_set(struct typec_= switch_dev *sw, enum typec_orientation orientation) { struct exynos5_usbdrd_phy *phy_drd =3D typec_switch_get_drvdata(sw); + int ret; + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) { + dev_err(phy_drd->dev, "Failed to enable PHY clocks(s)\n"); + return ret; + } + + scoped_guard(mutex, &phy_drd->phy_mutex) { + void __iomem * const regs_base =3D phy_drd->reg_phy; + unsigned int reg; + + if (orientation =3D=3D TYPEC_ORIENTATION_NONE) { + reg =3D readl(regs_base + EXYNOS850_DRD_UTMI); + reg &=3D ~(UTMI_FORCE_VBUSVALID | UTMI_FORCE_BVALID); + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + reg =3D readl(regs_base + EXYNOS850_DRD_HSP); + reg |=3D HSP_VBUSVLDEXTSEL; + reg &=3D ~HSP_VBUSVLDEXT; + writel(reg, regs_base + EXYNOS850_DRD_HSP); + } else { + reg =3D readl(regs_base + EXYNOS850_DRD_UTMI); + reg |=3D UTMI_FORCE_VBUSVALID | UTMI_FORCE_BVALID; + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + reg =3D readl(regs_base + EXYNOS850_DRD_HSP); + reg |=3D HSP_VBUSVLDEXTSEL | HSP_VBUSVLDEXT; + writel(reg, regs_base + EXYNOS850_DRD_HSP); + } =20 - scoped_guard(mutex, &phy_drd->phy_mutex) phy_drd->orientation =3D orientation; + } + + clk_bulk_disable(phy_drd->drv_data->n_clks, phy_drd->clks); =20 return 0; } --=20 2.47.0.338.g60cca15819-goog