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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2024 11:52:12.2106 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df22c785-d39e-4755-abe5-08dd145a170b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DE.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7766 Content-Type: text/plain; charset="utf-8" Add AMD Versal2 MDB (Multimedia DMA Bridge) PCIe Root Port Bridge. Signed-off-by: Thippeswamy Havalige --- Changes in v2: ------------- - Modify patch subject. - Add pcie host bridge reference. - Modify filename as per compatible string. - Remove standard PCI properties. - Modify interrupt controller description. - Indentation Changes in v3: ------------- - Modified SLCR to lower case. - Add dwc schemas. - Remove common properties. - Move additionalProperties below properties. - Remove ranges property from required properties. - Drop blank line. - Modify pci@ to pcie@ --- .../bindings/pci/amd,versal2-mdb-host.yaml | 121 ++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amd,versal2-mdb-h= ost.yaml diff --git a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yam= l b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml new file mode 100644 index 000000000000..c319adeeee66 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/amd,versal2-mdb-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Versal2 MDB(Multimedia DMA Bridge) Host Controller + +maintainers: + - Thippeswamy Havalige + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: amd,versal2-mdb-host + + reg: + items: + - description: MDB PCIe controller 0 slcr + - description: configuration region + - description: data bus interface + - description: address translation unit register + + reg-names: + items: + - const: mdb_pcie_slcr + - const: config + - const: dbi + - const: atu + + ranges: + maxItems: 2 + + msi-map: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + interrupt-map: + maxItems: 4 + + "#interrupt-cells": + const: 1 + + interrupt-controller: + description: identifies the node as an interrupt controller + type: object + additionalProperties: false + properties: + interrupt-controller: true + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + required: + - interrupt-controller + - "#address-cells" + - "#interrupt-cells" + +required: + - reg + - reg-names + - interrupts + - interrupt-map + - interrupt-map-mask + - msi-map + - "#interrupt-cells" + - interrupt-controller + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + pcie@ed931000 { + compatible =3D "amd,versal2-mdb-host"; + reg =3D <0x0 0xed931000 0x0 0x2000>, + <0x1000 0x100000 0x0 0xff00000>, + <0x1000 0x0 0x0 0x100000>, + <0x0 0xed860000 0x0 0x2000>; + reg-names =3D "mdb_pcie_slcr", "config", "dbi", "atu"; + ranges =3D <0x2000000 0x00 0xa8000000 0x00 0xa8000000 0x00 0x1= 0000000>, + <0x43000000 0x1100 0x00 0x1100 0x00 0x00 0x1000000>; + interrupts =3D ; + interrupt-parent =3D <&gic>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + msi-map =3D <0x0 &gic_its 0x00 0x10000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + pcie_intc_0: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + }; --=20 2.34.1