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[93.124.60.94]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53e18b2df6csm455727e87.8.2024.12.04.03.15.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2024 03:15:03 -0800 (PST) From: bigunclemax@gmail.com To: Cc: bigunclemax@gmail.com, Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1] riscv: dts: thead: Fix TH1520 emmc and shdci clock rate Date: Wed, 4 Dec 2024 14:14:23 +0300 Message-ID: <20241204111424.263055-1-bigunclemax@gmail.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maksim Kiselev In accordance with LicheePi 4A BSP the clock that comes to emmc/sdhci is 198Mhz. But changing from fixed-clock to CLK_EMMC_SDIO leads to increasing input clock from 198Mhz to 792Mhz. Because the CLK_EMMC_SDIO is actually 792Mhz. Therefore calculation of output SDCLK is incorrect now. The mmc driver sets the divisor to 4 times larger than it should be and emmc/sd works 4 times slower. This can be confirmed with fio test: Sequential read of emmc with fixed 198Mz clock: READ: bw=3D289MiB/s (303MB/s) Sequential read with CLK_EMMC_SDIO clock: READ: bw=3D82.6MiB/s (86.6MB/s) Let's fix this issue by providing fixed-factor-clock that divides CLK_EMMC_SDIO by 4 for emmc/sd nodes. Fixes: 03a20182e1e0 ("riscv: dts: thead: change TH1520 mmc nodes to use clo= ck controller") Signed-off-by: Maksim Kiselev --- arch/riscv/boot/dts/thead/th1520.dtsi | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index acfe030e803a..6c20965cd10c 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -229,6 +229,14 @@ stmmac_axi_config: stmmac-axi-config { snps,blen =3D <0 0 64 32 0 0 0>; }; =20 + sdhci_clk: sdhci-clock { + compatible =3D "fixed-factor-clock"; + clocks =3D <&clk CLK_EMMC_SDIO>; + #clock-cells =3D <0>; + clock-div =3D <4>; + clock-mult =3D <1>; + }; + soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -328,7 +336,7 @@ emmc: mmc@ffe7080000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe7080000 0x0 0x10000>; interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&clk CLK_EMMC_SDIO>; + clocks =3D <&sdhci_clk>; clock-names =3D "core"; status =3D "disabled"; }; @@ -337,7 +345,7 @@ sdio0: mmc@ffe7090000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe7090000 0x0 0x10000>; interrupts =3D <64 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&clk CLK_EMMC_SDIO>; + clocks =3D <&sdhci_clk>; clock-names =3D "core"; status =3D "disabled"; }; @@ -346,7 +354,7 @@ sdio1: mmc@ffe70a0000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe70a0000 0x0 0x10000>; interrupts =3D <71 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&clk CLK_EMMC_SDIO>; + clocks =3D <&sdhci_clk>; clock-names =3D "core"; status =3D "disabled"; }; --=20 2.45.2