From nobody Thu Dec 18 21:32:32 2025 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34327194A59 for ; Wed, 4 Dec 2024 09:43:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733305407; cv=none; b=Nmsqwwp8AIEhaI1oIqtMSVVN/WDTK/wykov0UNqNoQ5jz0yiqfrVbu5hUZ6ftrMxqQxscqZDqy+s3xOtdPdhXpSzo+kOjShkjKKdQDOZW5VqDJChnXOq89r8law5l5+74OFBf4FYFaPGpgyyE9q3Nl7hDZ9ukdC3fdD2HCcAQmg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733305407; c=relaxed/simple; bh=BxsWLFTDzvrK6h8Rt5svMWe6Rj8IKm8AHjxYs6JKT6o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AerWpzOWgzAv/FdodVR4ejtoWPvD9TVV105BvmFGNJsAuG3A+D1TvhM8mWkwk5l32xuDNtoZK3fsdJlkOCIWwqBJDhh80hmSjShtJbrOvpMLG7im/A0crDNcmq+8bF2ukcFqU/3FREFEroxRYJcOo1DMqzzPwbDsRG8Is5uzF64= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=hTlu/ZXI; arc=none smtp.client-ip=217.70.183.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="hTlu/ZXI" Received: by mail.gandi.net (Postfix) with ESMTPSA id 0C32960006; Wed, 4 Dec 2024 09:43:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1733305403; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9cG2pXBBYPaIu412ONqK9p/NnPgxaT89+ifg4qGZl7k=; b=hTlu/ZXIJqSB50d6jE/LErzqwyvOBI+zqGwCFx+VITaUHY0PxU/2HMEGawJPqU3Q2p4JTr A3Hh0ggsavNOxBmi7mlnHDrsqHlIv/5ekKrbpvtc42plHiJtc2yMGlWazyLEXY0Y2o4eJM ic/qJoGaa++V5T+TGAhWELwo2FFmubbVEdhULxKqqLkpAATRh00CPa2CgfD8uuIdoOPknY XeSVea/tt/rgk6qZ+JxD0c4/Uu8/6LfyBGTZtYqOiEv9Co1+YOHh1WI8tDeU6zShwbmGFW l+LCbaPQXqoo7j4XK6+gwSuEaDWBa+cWySFXkUcxqFXe2Gd8wbRSpRsykZ+rlg== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v5 1/9] memory: ti-aemif: Store timings parameter in number of cycles - 1 Date: Wed, 4 Dec 2024 10:43:11 +0100 Message-ID: <20241204094319.1050826-2-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241204094319.1050826-1-bastien.curutchet@bootlin.com> References: <20241204094319.1050826-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" The CS configuration register expects timings to be expressed in 'number of cycles - 1' but they are stored in ns in the struct aemif_cs_data. So at init, the timings currently set are converted to ns by aemif_get_hw_params(), updated with values from the device-tree properties, and then converted back to 'number of cycles - 1' before being applied. Store the timings directly in 'number of cycles - 1' instead of nanoseconds. Perform the conversion from nanosecond during the device-tree parsing. Remove aemif_cycles_to_nsec() as it isn't used anymore. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 135 ++++++++++++++++++++++---------------- 1 file changed, 79 insertions(+), 56 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index d54dc3cfff73..f23a549b219b 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -82,26 +82,26 @@ /** * struct aemif_cs_data: structure to hold cs parameters * @cs: chip-select number - * @wstrobe: write strobe width, ns - * @rstrobe: read strobe width, ns - * @wsetup: write setup width, ns - * @whold: write hold width, ns - * @rsetup: read setup width, ns - * @rhold: read hold width, ns - * @ta: minimum turn around time, ns + * @wstrobe: write strobe width, number of cycles - 1 + * @rstrobe: read strobe width, number of cycles - 1 + * @wsetup: write setup width, number of cycles - 1 + * @whold: write hold width, number of cycles - 1 + * @rsetup: read setup width, number of cycles - 1 + * @rhold: read hold width, number of cycles - 1 + * @ta: minimum turn around time, number of cycles - 1 * @enable_ss: enable/disable select strobe mode * @enable_ew: enable/disable extended wait mode * @asize: width of the asynchronous device's data bus */ struct aemif_cs_data { u8 cs; - u16 wstrobe; - u16 rstrobe; - u8 wsetup; - u8 whold; - u8 rsetup; - u8 rhold; - u8 ta; + u32 wstrobe; + u32 rstrobe; + u32 wsetup; + u32 whold; + u32 rsetup; + u32 rhold; + u32 ta; u8 enable_ss; u8 enable_ew; u8 asize; @@ -175,26 +175,18 @@ static int aemif_config_abus(struct platform_device *= pdev, int csnum) struct aemif_device *aemif =3D platform_get_drvdata(pdev); struct aemif_cs_data *data =3D &aemif->cs_data[csnum]; int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; - unsigned long clk_rate =3D aemif->clk_rate; unsigned offset; u32 set, val; =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; =20 - ta =3D aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX); - rhold =3D aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX); - rstrobe =3D aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX); - rsetup =3D aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX); - whold =3D aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX); - wstrobe =3D aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX); - wsetup =3D aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX); - - if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 || - whold < 0 || wstrobe < 0 || wsetup < 0) { - dev_err(&pdev->dev, "%s: cannot get suitable timings\n", - __func__); - return -EINVAL; - } + ta =3D data->ta; + rhold =3D data->rhold; + rstrobe =3D data->rstrobe; + rsetup =3D data->rsetup; + whold =3D data->whold; + wstrobe =3D data->wstrobe; + wsetup =3D data->wsetup; =20 set =3D TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); @@ -213,11 +205,6 @@ static int aemif_config_abus(struct platform_device *p= dev, int csnum) return 0; } =20 -static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate) -{ - return ((val + 1) * NSEC_PER_MSEC) / clk_rate; -} - /** * aemif_get_hw_params - function to read hw register values * @pdev: platform device to read for @@ -231,19 +218,18 @@ static void aemif_get_hw_params(struct platform_devic= e *pdev, int csnum) { struct aemif_device *aemif =3D platform_get_drvdata(pdev); struct aemif_cs_data *data =3D &aemif->cs_data[csnum]; - unsigned long clk_rate =3D aemif->clk_rate; u32 val, offset; =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; val =3D readl(aemif->base + offset); =20 - data->ta =3D aemif_cycles_to_nsec(TA_VAL(val), clk_rate); - data->rhold =3D aemif_cycles_to_nsec(RHOLD_VAL(val), clk_rate); - data->rstrobe =3D aemif_cycles_to_nsec(RSTROBE_VAL(val), clk_rate); - data->rsetup =3D aemif_cycles_to_nsec(RSETUP_VAL(val), clk_rate); - data->whold =3D aemif_cycles_to_nsec(WHOLD_VAL(val), clk_rate); - data->wstrobe =3D aemif_cycles_to_nsec(WSTROBE_VAL(val), clk_rate); - data->wsetup =3D aemif_cycles_to_nsec(WSETUP_VAL(val), clk_rate); + data->ta =3D TA_VAL(val); + data->rhold =3D RHOLD_VAL(val); + data->rstrobe =3D RSTROBE_VAL(val); + data->rsetup =3D RSETUP_VAL(val); + data->whold =3D WHOLD_VAL(val); + data->wstrobe =3D WSTROBE_VAL(val); + data->wsetup =3D WSETUP_VAL(val); data->enable_ew =3D EW_VAL(val); data->enable_ss =3D SSTROBE_VAL(val); data->asize =3D val & ASIZE_MAX; @@ -261,7 +247,9 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, struct device_node *np) { struct aemif_device *aemif =3D platform_get_drvdata(pdev); + unsigned long clk_rate =3D aemif->clk_rate; struct aemif_cs_data *data; + int ret; u32 cs; u32 val; =20 @@ -287,26 +275,61 @@ static int of_aemif_parse_abus_config(struct platform= _device *pdev, aemif_get_hw_params(pdev, aemif->num_cs++); =20 /* override the values from device node */ - if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val)) - data->ta =3D val; + if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val)) { + ret =3D aemif_calc_rate(pdev, val, clk_rate, TA_MAX); + if (ret < 0) + return ret; =20 - if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val)) - data->rhold =3D val; + data->ta =3D ret; + } =20 - if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val)) - data->rstrobe =3D val; + if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val)) { + ret =3D aemif_calc_rate(pdev, val, clk_rate, RHOLD_MAX); + if (ret < 0) + return ret; =20 - if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val)) - data->rsetup =3D val; + data->rhold =3D ret; + } =20 - if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val)) - data->whold =3D val; + if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val)) { + ret =3D aemif_calc_rate(pdev, val, clk_rate, RSTROBE_MAX); + if (ret < 0) + return ret; =20 - if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val)) - data->wstrobe =3D val; + data->rstrobe =3D ret; + } =20 - if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val)) - data->wsetup =3D val; + if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val)) { + ret =3D aemif_calc_rate(pdev, val, clk_rate, RSETUP_MAX); + if (ret < 0) + return ret; + + data->rsetup =3D ret; + } + + if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val)) { + ret =3D aemif_calc_rate(pdev, val, clk_rate, WHOLD_MAX); + if (ret < 0) + return ret; + + data->whold =3D ret; + } + + if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val)) { + ret =3D aemif_calc_rate(pdev, val, clk_rate, WSTROBE_MAX); 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Wed, 4 Dec 2024 09:43:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1733305404; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NVdYJysLi5n1RUC9YCAebU4m2JnvzkI3+7eLaZOZoto=; b=YfC0a/iqtP4VitNKQCBacFOdIXuFnZvGCOcyKRHCZ8PBNoPmiQuSpaqchX3zQ6QFc0L1sj mmx4fN1QTv3INfgHsjtikiE5eplc9NOfV6BLLKLyITrDlB08LuGCouHMb+LTlxnDN7xMkE D3rb3S6Mb4cqIRMIoZV3yHEkktoDfVajTtUgo7+ub25uLBFuxo4ExutgyQfZJmCIOvpNnb 4siKZwd1gNOmeJq1Z5niaDN0VB47KDRx9aIa5QdFjfRn9S+BZGOuoy4h92nRb4sDS6ePL9 Za7oglhBuQyUr1E9BrhjxG04qyJ1K1FLtrPe2bVKoerkpSVVsZVI8R5pawVrtQ== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v5 2/9] memory: ti-aemif: Remove unnecessary local variables Date: Wed, 4 Dec 2024 10:43:12 +0100 Message-ID: <20241204094319.1050826-3-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241204094319.1050826-1-bastien.curutchet@bootlin.com> References: <20241204094319.1050826-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" CS timings are copied to local variables that are then used as is, without any modifications. Remove these unneeded local variables and deal directly with the timings stored in the struct aemif_cs_data. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index f23a549b219b..a0e1a6b53256 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -174,22 +174,14 @@ static int aemif_config_abus(struct platform_device *= pdev, int csnum) { struct aemif_device *aemif =3D platform_get_drvdata(pdev); struct aemif_cs_data *data =3D &aemif->cs_data[csnum]; - int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; unsigned offset; u32 set, val; =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; =20 - ta =3D data->ta; - rhold =3D data->rhold; - rstrobe =3D data->rstrobe; - rsetup =3D data->rsetup; - whold =3D data->whold; - wstrobe =3D data->wstrobe; - wsetup =3D data->wsetup; - - set =3D TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | - WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); + set =3D TA(data->ta) | + RHOLD(data->rhold) | RSTROBE(data->rstrobe) | RSETUP(data->rsetup) | + WHOLD(data->whold) | WSTROBE(data->wstrobe) | WSETUP(data->wsetup); =20 set |=3D (data->asize & ACR_ASIZE_MASK); if (data->enable_ew) --=20 2.47.0 From nobody Thu Dec 18 21:32:32 2025 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A24C91A9B5D for ; Wed, 4 Dec 2024 09:43:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733305408; cv=none; b=tbs6BKfQKZ+KjSjU0vui/ygXEzHfRSEShyCklCEpLMh9KwxpSt1yzYfGeWupMiu5dMLhCt7w8sXqnAHl4UuBwmn4Wvdb5rbQ3gFPIrnur6UCPrVP1u8sYF4oefOlbzuTn5TPMt+DUtX0/IbS0K2R9/3oKa3Qsa5ePkcZpV7Msf0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733305408; c=relaxed/simple; bh=yIpIw/yPRhOjS09EiAV0V6ZaBpcd4fwYqe81O6r4jQo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BdFacFSFOuN53JJChlrMH/xu+lTqXmcZlfSxd2bzbfgVkJifSEtpcjfAXyz9a6UVSNaWlduvT0MUd3WLZ3hCSr8Yn0zajYbXDIhX69dfeu2vtoc5rnqVZQQeeEGrR1qM06K4ev09FA4m28lBF0tcaruid05OCUvNfTfLFtPbVik= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=OgJ0OEh8; arc=none smtp.client-ip=217.70.183.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="OgJ0OEh8" Received: by mail.gandi.net (Postfix) with ESMTPSA id 55C016000E; Wed, 4 Dec 2024 09:43:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1733305404; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=L1dSLJh1SAr2vIT0aQ/N/d5yFBNgqA0SN9iaVBxJ+xc=; b=OgJ0OEh8TT0ynPArYFjdi8h19A0loT1wSX8taMnOcspK+yhepP4Tvx3hQP/enaBZPEy5+k D72w9HUkzUesJPkkry7zH147mZw+smiGbv+0rWfXhOyUPtn7DXS3p+5Ng4kB46QLk8Duh3 6KsSlDZU3qfLi7IoNSLXBPpFw79RaolKfc6wLwcgc2ItV+Z7/+ZTxGo7fq470m4wGJrEbM U4jqDYarhXXWQasGwC935PGTaqAD4S6j68YPqTPPf3aON85Mdx59zuVkMP0YheGq7YlAk1 FW5/+KCaji7nPFETh9KP7OKkKz6VwrMvP1BmzgK660ixyuXalLM/yILqbrBzuQ== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v5 3/9] memory: ti-aemif: Wrap CS timings into a struct Date: Wed, 4 Dec 2024 10:43:13 +0100 Message-ID: <20241204094319.1050826-4-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241204094319.1050826-1-bastien.curutchet@bootlin.com> References: <20241204094319.1050826-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" CS timings are store in the struct aemif_cs_data along with other CS parameters. It isn't convenient for exposing CS timings to other drivers without also exposing the other parameters. Wrap the CS timings in a new struct aemif_cs_timings to simplify their export in upcoming patches. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 57 ++++++++++++++++++++++----------------- 1 file changed, 33 insertions(+), 24 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index a0e1a6b53256..1d1b30112af5 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -80,8 +80,7 @@ ASIZE_MAX) =20 /** - * struct aemif_cs_data: structure to hold cs parameters - * @cs: chip-select number + * struct aemif_cs_timings: structure to hold CS timings * @wstrobe: write strobe width, number of cycles - 1 * @rstrobe: read strobe width, number of cycles - 1 * @wsetup: write setup width, number of cycles - 1 @@ -89,12 +88,8 @@ * @rsetup: read setup width, number of cycles - 1 * @rhold: read hold width, number of cycles - 1 * @ta: minimum turn around time, number of cycles - 1 - * @enable_ss: enable/disable select strobe mode - * @enable_ew: enable/disable extended wait mode - * @asize: width of the asynchronous device's data bus */ -struct aemif_cs_data { - u8 cs; +struct aemif_cs_timings { u32 wstrobe; u32 rstrobe; u32 wsetup; @@ -102,6 +97,19 @@ struct aemif_cs_data { u32 rsetup; u32 rhold; u32 ta; +}; + +/** + * struct aemif_cs_data: structure to hold CS parameters + * @timings: timings configuration + * @cs: chip-select number + * @enable_ss: enable/disable select strobe mode + * @enable_ew: enable/disable extended wait mode + * @asize: width of the asynchronous device's data bus + */ +struct aemif_cs_data { + struct aemif_cs_timings timings; + u8 cs; u8 enable_ss; u8 enable_ew; u8 asize; @@ -179,9 +187,10 @@ static int aemif_config_abus(struct platform_device *p= dev, int csnum) =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; =20 - set =3D TA(data->ta) | - RHOLD(data->rhold) | RSTROBE(data->rstrobe) | RSETUP(data->rsetup) | - WHOLD(data->whold) | WSTROBE(data->wstrobe) | WSETUP(data->wsetup); + set =3D TA(data->timings.ta) | + RHOLD(data->timings.rhold) | RSTROBE(data->timings.rstrobe) | + RSETUP(data->timings.rsetup) | WHOLD(data->timings.whold) | + WSTROBE(data->timings.wstrobe) | WSETUP(data->timings.wsetup); =20 set |=3D (data->asize & ACR_ASIZE_MASK); if (data->enable_ew) @@ -215,13 +224,13 @@ static void aemif_get_hw_params(struct platform_devic= e *pdev, int csnum) offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; val =3D readl(aemif->base + offset); =20 - data->ta =3D TA_VAL(val); - data->rhold =3D RHOLD_VAL(val); - data->rstrobe =3D RSTROBE_VAL(val); - data->rsetup =3D RSETUP_VAL(val); - data->whold =3D WHOLD_VAL(val); - data->wstrobe =3D WSTROBE_VAL(val); - data->wsetup =3D WSETUP_VAL(val); + data->timings.ta =3D TA_VAL(val); + data->timings.rhold =3D RHOLD_VAL(val); + data->timings.rstrobe =3D RSTROBE_VAL(val); + data->timings.rsetup =3D RSETUP_VAL(val); + data->timings.whold =3D WHOLD_VAL(val); + data->timings.wstrobe =3D WSTROBE_VAL(val); + data->timings.wsetup =3D WSETUP_VAL(val); data->enable_ew =3D EW_VAL(val); data->enable_ss =3D SSTROBE_VAL(val); data->asize =3D val & ASIZE_MAX; @@ -272,7 +281,7 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, if (ret < 0) return ret; =20 - data->ta =3D ret; + data->timings.ta =3D ret; } =20 if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val)) { @@ -280,7 +289,7 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, if (ret < 0) return ret; =20 - data->rhold =3D ret; + data->timings.rhold =3D ret; } =20 if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val)) { @@ -288,7 +297,7 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, if (ret < 0) return ret; =20 - data->rstrobe =3D ret; + data->timings.rstrobe =3D ret; } =20 if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val)) { @@ -296,7 +305,7 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, if (ret < 0) return ret; =20 - data->rsetup =3D ret; + data->timings.rsetup =3D ret; } =20 if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val)) { @@ -304,7 +313,7 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, if (ret < 0) return ret; =20 - data->whold =3D ret; + data->timings.whold =3D ret; } =20 if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val)) { @@ -312,7 +321,7 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, if (ret < 0) return ret; =20 - data->wstrobe =3D ret; + data->timings.wstrobe =3D ret; } =20 if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val)) { @@ -320,7 +329,7 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, if (ret < 0) return ret; =20 - data->wsetup =3D ret; + data->timings.wsetup =3D ret; } =20 if (!of_property_read_u32(np, "ti,cs-bus-width", &val)) --=20 2.47.0 From nobody Thu Dec 18 21:32:32 2025 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29C081AA1DF for ; Wed, 4 Dec 2024 09:43:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.195 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="LW/hS81r" Received: by mail.gandi.net (Postfix) with ESMTPSA id F0A516000D; Wed, 4 Dec 2024 09:43:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1733305405; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DLNmuyNTbzPAZ139Ma4EX78v29Ja1psgE6Q61skRI0g=; b=LW/hS81rrWVrxHLeqjPvjzr2pklCxlxGHd0UCipicJDkS/2hDINzkNeb9SFfjiPTk0T/kq kn6CO8dcyNI+e3xGMEnYYzVSJEUQtIMABi0aZWVQo7s05bxyjp1qMp0W2oKBu+XByBc8yO jJH4dY89VlN9qfJAiu+5o1qL9+EIT35ogDijhBMAfkEtX0SYA3zqSSUGPy/xtJDtWJ4dL1 ss+PF7gth4LbOWTjPjf8d4MDQBExaMkH+7FsuJp23ypX539/svrb017aOEMDC3gn+nuXb0 1xhi+8PKUFq1q9It/EnaesdY49wU9ZYENXzoSe2yHP+aXsC57a3i9RnqsBCnog== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v5 4/9] memory: ti-aemif: Create aemif_check_cs_timings() Date: Wed, 4 Dec 2024 10:43:14 +0100 Message-ID: <20241204094319.1050826-5-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241204094319.1050826-1-bastien.curutchet@bootlin.com> References: <20241204094319.1050826-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" aemif_calc_rate() checks the validity of a new computed timing against a 'max' value given as input. This isn't convenient if we want to check the CS timing configuration somewhere else in the code. Wrap the verification of all the chip select's timing configuration into a single function to ease its exportation in upcoming patches. Remove the validity check from aemif_calc_rate(). Also remove the no longer used 'max' input and change the return type to u32. Remove the check of the aemif_calc_rate()'s return value during device-tree parsing as aemif_calc_rate() can't fail anymore. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 111 ++++++++++++++++++-------------------- 1 file changed, 51 insertions(+), 60 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index 1d1b30112af5..ec770a2668e7 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -133,18 +133,48 @@ struct aemif_device { struct aemif_cs_data cs_data[NUM_CS]; }; =20 +/** + * aemif_check_cs_timings() - Check the validity of a CS timing configurat= ion. + * @timings: timings configuration + * + * @return: 0 if the timing configuration is valid, negative error number = otherwise. + */ +static int aemif_check_cs_timings(struct aemif_cs_timings *timings) +{ + if (timings->ta > TA_MAX) + return -EINVAL; + + if (timings->rhold > RHOLD_MAX) + return -EINVAL; + + if (timings->rstrobe > RSTROBE_MAX) + return -EINVAL; + + if (timings->rsetup > RSETUP_MAX) + return -EINVAL; + + if (timings->whold > WHOLD_MAX) + return -EINVAL; + + if (timings->wstrobe > WSTROBE_MAX) + return -EINVAL; + + if (timings->wsetup > WSETUP_MAX) + return -EINVAL; + + return 0; +} + /** * aemif_calc_rate - calculate timing data. * @pdev: platform device to calculate for * @wanted: The cycle time needed in nanoseconds. * @clk: The input clock rate in kHz. - * @max: The maximum divider value that can be programmed. * - * On success, returns the calculated timing value minus 1 for easy - * programming into AEMIF timing registers, else negative errno. + * @return: the calculated timing value minus 1 for easy + * programming into AEMIF timing registers. */ -static int aemif_calc_rate(struct platform_device *pdev, int wanted, - unsigned long clk, int max) +static u32 aemif_calc_rate(struct platform_device *pdev, int wanted, unsig= ned long clk) { int result; =20 @@ -157,10 +187,6 @@ static int aemif_calc_rate(struct platform_device *pde= v, int wanted, if (result < 0) result =3D 0; =20 - /* ... But configuring tighter timings is not an option. */ - else if (result > max) - result =3D -EINVAL; - return result; } =20 @@ -250,7 +276,6 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, struct aemif_device *aemif =3D platform_get_drvdata(pdev); unsigned long clk_rate =3D aemif->clk_rate; struct aemif_cs_data *data; - int ret; u32 cs; u32 val; =20 @@ -276,68 +301,34 @@ static int of_aemif_parse_abus_config(struct platform= _device *pdev, aemif_get_hw_params(pdev, aemif->num_cs++); =20 /* override the values from device node */ - if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val)) { - ret =3D aemif_calc_rate(pdev, val, clk_rate, TA_MAX); - if (ret < 0) - return ret; - - data->timings.ta =3D ret; - } + if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val)) + data->timings.ta =3D aemif_calc_rate(pdev, val, clk_rate); =20 - if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val)) { - ret =3D aemif_calc_rate(pdev, val, clk_rate, RHOLD_MAX); - if (ret < 0) - return ret; - - data->timings.rhold =3D ret; - } + if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val)) + data->timings.rhold =3D aemif_calc_rate(pdev, val, clk_rate); =20 - if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val)) { - ret =3D aemif_calc_rate(pdev, val, clk_rate, RSTROBE_MAX); - if (ret < 0) - return ret; + if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val)) + data->timings.rstrobe =3D aemif_calc_rate(pdev, val, clk_rate); =20 - data->timings.rstrobe =3D ret; - } + if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val)) + data->timings.rsetup =3D aemif_calc_rate(pdev, val, clk_rate); =20 - if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val)) { - ret =3D aemif_calc_rate(pdev, val, clk_rate, RSETUP_MAX); - if (ret < 0) - return ret; + if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val)) + data->timings.whold =3D aemif_calc_rate(pdev, val, clk_rate); =20 - data->timings.rsetup =3D ret; - } + if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val)) + data->timings.wstrobe =3D aemif_calc_rate(pdev, val, clk_rate); =20 - if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val)) { - ret =3D aemif_calc_rate(pdev, val, clk_rate, WHOLD_MAX); - if (ret < 0) - return ret; - - data->timings.whold =3D ret; - } - - if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val)) { - ret =3D aemif_calc_rate(pdev, val, clk_rate, WSTROBE_MAX); - if (ret < 0) - return ret; - - data->timings.wstrobe =3D ret; - } - - if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val)) { - ret =3D aemif_calc_rate(pdev, val, clk_rate, WSETUP_MAX); - if (ret < 0) - return ret; - - data->timings.wsetup =3D ret; - } + if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val)) + data->timings.wsetup =3D aemif_calc_rate(pdev, val, clk_rate); =20 if (!of_property_read_u32(np, "ti,cs-bus-width", &val)) if (val =3D=3D 16) data->asize =3D 1; data->enable_ew =3D of_property_read_bool(np, "ti,cs-extended-wait-mode"); data->enable_ss =3D of_property_read_bool(np, "ti,cs-select-strobe-mode"); - return 0; + + return aemif_check_cs_timings(&data->timings); } =20 static const struct of_device_id aemif_of_match[] =3D { --=20 2.47.0 From nobody Thu Dec 18 21:32:32 2025 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B29001AA78E for ; Wed, 4 Dec 2024 09:43:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733305409; cv=none; b=dJskFE52xXh4kpclt7wPROo62eC9WJMZVQ2A3fm1Hkj7fCH5BA+TfjUHlNBy0aiQtib305fdSuA6C0wLybSCH7pCAT3Q9hEWasrq+hDtS12dt7cp+hkNsVaSNCzYGx71bFaSz9lFB4AMSWfGcJAa9KmZ/YMcdMIp4fuBG0hoJSw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733305409; c=relaxed/simple; bh=k/sTWHD6MrxmBTSDhbLEQLDBKe7SNAl+sJ+HWfjzVBI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Kx/vvoniaXhguWDaZC18R9FYR4qLWV27sMDiZsY8wJj5aqZV7pAExJ1ntTr3Fa8NKejUioz7tS1Swa20GiNlHbPTQP5HmFrVVVjqTzRoLIOmofojLUgzNVe7y0yUI46IbubnnMAeaV+66djX4pn+xXFBxBCklSNnvnTn5+zx7pw= ARC-Authentication-Results: i=1; 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charset="utf-8" Create an aemif_set_cs_timings() function to isolate the setting of a chip select timing configuration and ease its exportation. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 65 +++++++++++++++++++++++++++++---------- 1 file changed, 49 insertions(+), 16 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index ec770a2668e7..83fb308a831b 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -69,15 +69,15 @@ #define ACR_SSTROBE_MASK BIT(31) #define ASIZE_16BIT 1 =20 -#define CONFIG_MASK (TA(TA_MAX) | \ - RHOLD(RHOLD_MAX) | \ - RSTROBE(RSTROBE_MAX) | \ - RSETUP(RSETUP_MAX) | \ - WHOLD(WHOLD_MAX) | \ - WSTROBE(WSTROBE_MAX) | \ - WSETUP(WSETUP_MAX) | \ - EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \ - ASIZE_MAX) +#define TIMINGS_MASK (TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE(WSTROBE_MAX) | \ + WSETUP(WSETUP_MAX)) + +#define CONFIG_MASK (EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | ASIZE_MAX) =20 /** * struct aemif_cs_timings: structure to hold CS timings @@ -165,6 +165,44 @@ static int aemif_check_cs_timings(struct aemif_cs_timi= ngs *timings) return 0; } =20 +/** + * aemif_set_cs_timings() - Set the timing configuration of a given chip s= elect. + * @aemif: aemif device to configure + * @cs: index of the chip select to configure + * @timings: timings configuration to set + * + * @return: 0 on success, else negative errno. + */ +static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct = aemif_cs_timings *timings) +{ + unsigned int offset; + u32 val, set; + int ret; + + if (!timings || !aemif) + return -EINVAL; + + if (cs > aemif->num_cs) + return -EINVAL; + + ret =3D aemif_check_cs_timings(timings); + if (ret) + return ret; + + set =3D TA(timings->ta) | RHOLD(timings->rhold) | RSTROBE(timings->rstrob= e) | + RSETUP(timings->rsetup) | WHOLD(timings->whold) | + WSTROBE(timings->wstrobe) | WSETUP(timings->wsetup); + + offset =3D A1CR_OFFSET + cs * 4; + + val =3D readl(aemif->base + offset); + val &=3D ~TIMINGS_MASK; + val |=3D set; + writel(val, aemif->base + offset); + + return 0; +} + /** * aemif_calc_rate - calculate timing data. * @pdev: platform device to calculate for @@ -213,12 +251,7 @@ static int aemif_config_abus(struct platform_device *p= dev, int csnum) =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; =20 - set =3D TA(data->timings.ta) | - RHOLD(data->timings.rhold) | RSTROBE(data->timings.rstrobe) | - RSETUP(data->timings.rsetup) | WHOLD(data->timings.whold) | - WSTROBE(data->timings.wstrobe) | WSETUP(data->timings.wsetup); - - set |=3D (data->asize & ACR_ASIZE_MASK); + set =3D (data->asize & ACR_ASIZE_MASK); if (data->enable_ew) set |=3D ACR_EW_MASK; if (data->enable_ss) @@ -229,7 +262,7 @@ static int aemif_config_abus(struct platform_device *pd= ev, int csnum) val |=3D set; writel(val, aemif->base + offset); =20 - return 0; + return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &data->ti= mings); } =20 /** --=20 2.47.0 From nobody Thu Dec 18 21:32:32 2025 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85E051ABED7 for ; Wed, 4 Dec 2024 09:43:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Export the aemif_set_cs_timing() and aemif_check_cs_timing() symbols so they can be used by other drivers Add a mutex to protect the CS configuration register from concurrent accesses between the AEMIF and its 'children'. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 35 ++++++++++++--------------------- include/linux/memory/ti-aemif.h | 32 ++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 22 deletions(-) create mode 100644 include/linux/memory/ti-aemif.h diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index 83fb308a831b..541fc8b8b640 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -13,7 +13,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -79,26 +81,6 @@ =20 #define CONFIG_MASK (EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | ASIZE_MAX) =20 -/** - * struct aemif_cs_timings: structure to hold CS timings - * @wstrobe: write strobe width, number of cycles - 1 - * @rstrobe: read strobe width, number of cycles - 1 - * @wsetup: write setup width, number of cycles - 1 - * @whold: write hold width, number of cycles - 1 - * @rsetup: read setup width, number of cycles - 1 - * @rhold: read hold width, number of cycles - 1 - * @ta: minimum turn around time, number of cycles - 1 - */ -struct aemif_cs_timings { - u32 wstrobe; - u32 rstrobe; - u32 wsetup; - u32 whold; - u32 rsetup; - u32 rhold; - u32 ta; -}; - /** * struct aemif_cs_data: structure to hold CS parameters * @timings: timings configuration @@ -123,6 +105,7 @@ struct aemif_cs_data { * @num_cs: number of assigned chip-selects * @cs_offset: start number of cs nodes * @cs_data: array of chip-select settings + * @config_cs_lock: lock used to access CS configuration */ struct aemif_device { void __iomem *base; @@ -131,6 +114,7 @@ struct aemif_device { u8 num_cs; int cs_offset; struct aemif_cs_data cs_data[NUM_CS]; + struct mutex config_cs_lock; }; =20 /** @@ -139,7 +123,7 @@ struct aemif_device { * * @return: 0 if the timing configuration is valid, negative error number = otherwise. */ -static int aemif_check_cs_timings(struct aemif_cs_timings *timings) +int aemif_check_cs_timings(struct aemif_cs_timings *timings) { if (timings->ta > TA_MAX) return -EINVAL; @@ -164,6 +148,7 @@ static int aemif_check_cs_timings(struct aemif_cs_timin= gs *timings) =20 return 0; } +EXPORT_SYMBOL_GPL(aemif_check_cs_timings); =20 /** * aemif_set_cs_timings() - Set the timing configuration of a given chip s= elect. @@ -173,7 +158,7 @@ static int aemif_check_cs_timings(struct aemif_cs_timin= gs *timings) * * @return: 0 on success, else negative errno. */ -static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct = aemif_cs_timings *timings) +int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_c= s_timings *timings) { unsigned int offset; u32 val, set; @@ -195,13 +180,16 @@ static int aemif_set_cs_timings(struct aemif_device *= aemif, u8 cs, struct aemif_ =20 offset =3D A1CR_OFFSET + cs * 4; =20 + mutex_lock(&aemif->config_cs_lock); val =3D readl(aemif->base + offset); val &=3D ~TIMINGS_MASK; val |=3D set; writel(val, aemif->base + offset); + mutex_unlock(&aemif->config_cs_lock); =20 return 0; } +EXPORT_SYMBOL_GPL(aemif_set_cs_timings); =20 /** * aemif_calc_rate - calculate timing data. @@ -257,10 +245,12 @@ static int aemif_config_abus(struct platform_device *= pdev, int csnum) if (data->enable_ss) set |=3D ACR_SSTROBE_MASK; =20 + mutex_lock(&aemif->config_cs_lock); val =3D readl(aemif->base + offset); val &=3D ~CONFIG_MASK; val |=3D set; writel(val, aemif->base + offset); + mutex_unlock(&aemif->config_cs_lock); =20 return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &data->ti= mings); } @@ -399,6 +389,7 @@ static int aemif_probe(struct platform_device *pdev) if (IS_ERR(aemif->base)) return PTR_ERR(aemif->base); =20 + mutex_init(&aemif->config_cs_lock); if (np) { /* * For every controller device node, there is a cs device node diff --git a/include/linux/memory/ti-aemif.h b/include/linux/memory/ti-aemi= f.h new file mode 100644 index 000000000000..da94a9d985e7 --- /dev/null +++ b/include/linux/memory/ti-aemif.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __MEMORY_TI_AEMIF_H +#define __MEMORY_TI_AEMIF_H + +/** + * struct aemif_cs_timings: structure to hold CS timing configuration + * values are expressed in number of clock cycles - 1 + * @ta: minimum turn around time + * @rhold: read hold width + * @rstrobe: read strobe width + * @rsetup: read setup width + * @whold: write hold width + * @wstrobe: write strobe width + * @wsetup: write setup width + */ +struct aemif_cs_timings { + u32 ta; + u32 rhold; + u32 rstrobe; + u32 rsetup; + u32 whold; + u32 wstrobe; + u32 wsetup; +}; + +struct aemif_device; + +int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_c= s_timings *timings); +int aemif_check_cs_timings(struct aemif_cs_timings *timings); + +#endif // __MEMORY_TI_AEMIF_H --=20 2.47.0 From nobody Thu Dec 18 21:32:32 2025 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EF201ADFE0 for ; Wed, 4 Dec 2024 09:43:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733305411; cv=none; b=CRbyaArWkhhtToRzbuJzB1iaSe8VaU+hUJeLltSh6GXrejwy4iTLZVVxC2W+6rlSxk16L+57pOZUj9TGAFhSiv4BYPicAQISBGCak1Y8G4LZv6nqp6h+ZNJMuLqG/KmxhTFKmVxf3F/dpD3O/ZBw5dJ4mkYDD8DqbVWTCNo1W24= ARC-Message-Signature: i=1; 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Wed, 4 Dec 2024 09:43:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1733305407; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=260i8Kmy1qIGGfd2CxjTGXG+BKpSWuDOsQ7KscW8IdI=; b=kZptWreGXWfIYhLsw1mifV2O4DHr2ImINI/QvW52d9yqtuRMY8mo1UQltde7eqx1VKldpA VeikL6Ft25b09kRNc62tbuIL+2BH2eZwBqHIxsB4Rdlr1yqQhbhDpQwYssgNx7pdvoQMF3 CT3O4lWOQP9YgfFSh8kUojp6syU7loH7wCO9+T+sJ0NkVQ/z1AXhOQwxzxFFGQGyfDq9ld Eh4TxFhoVYx3a0QXIu61DmF7Mm9/DpkiMUR2D8vu2xtvd0RYUA1NfZ5XwimHg6qb8taPnP VaxM7K7YrHDYHLovlbM0u1Iuj1N1mbDKlAD5B9MYl7w7S6EW2yM+rCwaEiYmTA== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet , kernel test robot Subject: [PATCH v5 7/9] mtd: rawnand: davinci: Always depends on TI_AEMIF Date: Wed, 4 Dec 2024 10:43:17 +0100 Message-ID: <20241204094319.1050826-8-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241204094319.1050826-1-bastien.curutchet@bootlin.com> References: <20241204094319.1050826-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" DAVINCI_NAND depends on TI_AEMIF only when ARCH_KEYSTONE is selected while the NAND controller is also always a part of the AEMIF controller on DaVinci SoCs. Set a dependency on TI_AEMIF regardless of the selected architecture. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202411020140.3wsKJOSB-lkp@int= el.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202411020957.X1T8T9ZR-lkp@int= el.com/ Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index d0aaccf72d78..bb61434347bd 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -279,8 +279,8 @@ config MTD_NAND_SH_FLCTL =20 config MTD_NAND_DAVINCI tristate "DaVinci/Keystone NAND controller" - depends on ARCH_DAVINCI || (ARCH_KEYSTONE && TI_AEMIF) || COMPILE_TEST - depends on HAS_IOMEM + depends on COMPILE_TEST || ARCH_DAVINCI || ARCH_KEYSTONE + depends on HAS_IOMEM && TI_AEMIF help Enable the driver for NAND flash chips on Texas Instruments DaVinci/Keystone processors. --=20 2.47.0 From nobody Thu Dec 18 21:32:32 2025 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D86121AF0A1 for ; Wed, 4 Dec 2024 09:43:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733305411; cv=none; b=uFb4wjG9KY3xVNPoxcd0bAsX9JeSJHB8IYPNi2fzfw4Za/ukfGaCcOd+4ODhpakxajE41JHaBDQU00App+sH7reWbyF6af6BKym7oQefgYlcmdWwgF2TItQhnzAteJfYP0tHmVZDfJUBRdYZbEbabyM1WglScNuuJVFQXnMJKkE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733305411; c=relaxed/simple; bh=FuIs2nZmk94nSFen7jMoWMn9dSSOLg8+Y2ZXltecJsA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c5gOuCJr8+zuoB1J5DFQJN/r0oG/CLz2gFzJJEmaatSd9LQlM4n1T8UKvGLqL86e5hBg5c3FHs/mouFQrFT2kpJe7LzZraSFUaWn+1uQvfTs21Mn97xiKvEKdlw7VTGc5TrZIPHoBb0fsh/rX/nCpJNnRlWtJMSr9kmuG6ETnuA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=k7RU2M2a; arc=none smtp.client-ip=217.70.183.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="k7RU2M2a" Received: by mail.gandi.net (Postfix) with ESMTPSA id BDDC560012; Wed, 4 Dec 2024 09:43:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1733305408; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jfK2554wMfYphGMsRYSv3huQZ+56kT14PfwFMk8+S5M=; b=k7RU2M2avmDkzpzAQZcQPVA9bpnzUDtCpZ2RorT3jiRrbwJh7KZ2iITbW1OmktsO4vTFNt +vpI2R2RrUuHqud7GU/3XXzdsBnS+FcyQoYzcDU/Zdcf4+Q/AJ9Htns5Lir+zMF+dtvfiF KP5hwM+cQWo3j2RnO4wzk360EwRzh1YDYkr4bIwnRtxStUFb4YM6rMj2I/ne+UrguuTro+ vRrDCjaF8Dv8gictgs6+h3Q4FgXIpkmTyN7bliUolDaZRaMKCz2PVfZLvf709V4KyvQnMA W5nKTWB7smQXmUcQIx/mysNVqBXZLhxQRLuNCjfRXp1roDJllIW1Ar7jMPEPmQ== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v5 8/9] mtd: rawnand: davinci: Add clock resource Date: Wed, 4 Dec 2024 10:43:18 +0100 Message-ID: <20241204094319.1050826-9-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241204094319.1050826-1-bastien.curutchet@bootlin.com> References: <20241204094319.1050826-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" NAND controller has a reference clock inherited from the AEMIF (cf. Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt) This clock isn't used yet by the driver. Add a struct clock in the struct davinci_nand_info so it can be used to compute timings. Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/davinci_nand.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 1f8354acfb50..4fb5c2623f5a 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -10,6 +10,7 @@ * Dirk Behme */ =20 +#include #include #include #include @@ -117,6 +118,8 @@ struct davinci_nand_info { uint32_t mask_cle; =20 uint32_t core_chipsel; + + struct clk *clk; }; =20 static DEFINE_SPINLOCK(davinci_nand_lock); @@ -822,6 +825,10 @@ static int nand_davinci_probe(struct platform_device *= pdev) return -EADDRNOTAVAIL; } =20 + info->clk =3D devm_clk_get_enabled(&pdev->dev, "aemif"); + if (IS_ERR(info->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), "failed to get cloc= k"); + info->pdev =3D pdev; info->base =3D base; info->vaddr =3D vaddr; --=20 2.47.0 From nobody Thu Dec 18 21:32:32 2025 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A32A1AF0DB for ; Wed, 4 Dec 2024 09:43:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733305412; cv=none; b=qWHgtc/PkWdCRUnoimdzuga4vigzqWHWj6nEQot3mzpSMxGIZH83GQijn6uos51lekn8LFYgbjrVJQ2eDjDvaIXP7CJpDo0PuXBmUY4qvlX/q7qcxWQmZlQqpKrY/njGnTQya8YqDRxta0uvTickGPuYXdPobnV/I4czkv6V2nQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733305412; c=relaxed/simple; bh=OwZHJITJWKF1GqDDdybsKjjC7vHVm5QA33jv8WUR7xU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rrVAkt/hXsS6lOZmJzpwjonu7t8YwXC3u2R/i23gssKVYFZehx5Dy6HY2hjQR77kJdd9y2oMUtSsOxb9XDTpPibnUVWqi25jtekgnp+U+v2/6CEK5IcSUWPqj+7g+Hj5MYDUDg+C6IQ2qn7XUcqYnZodKq8NHVt9ANSPtqIHy6s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=DzYtog0b; arc=none smtp.client-ip=217.70.183.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="DzYtog0b" Received: by mail.gandi.net (Postfix) with ESMTPSA id 64FF560015; Wed, 4 Dec 2024 09:43:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1733305409; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MxgwQZm4INWNx3/RR7QESwiQmqttZVbjI7EwJ1ZjPKA=; b=DzYtog0bueaVgZZ0doooO5zlK8cTc+Lsf0GBQ+Hx4VC24h9s0DGz1DFtDT8VFYqMHLLsMt 5aDhV0pMVYZ537JsFzaHeqizlffjXt6w76WEySENLV+Wf1LADuvxI2zig2ty9qFH0zomhV q4DWBY5dqRqQmek2grrmcd19D01qLXFcymKB85hN/KbN+BgtVN8+wgAlMTziOPsmXtwVGs PhC4FxN01/f1EYNUGolMjEBXVJydGRgmPt8jt18uR2AJpH+nDZON35pHCuMp1ny9xSqEbI 5xvMMuT2WNYR8qniJ07e24zuLAHyzGwegjbA4NTV2rPcqfSCj53eeaCIrX7QMw== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v5 9/9] mtd: rawnand: davinci: Implement setup_interface() operation Date: Wed, 4 Dec 2024 10:43:19 +0100 Message-ID: <20241204094319.1050826-10-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241204094319.1050826-1-bastien.curutchet@bootlin.com> References: <20241204094319.1050826-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com The setup_interface() operation isn't implemented. It forces the driver to use the ONFI mode 0, though it could use more optimal modes. Implement the setup_interface() operation. It uses the aemif_set_cs_timings() function from the AEMIF driver to update the chip select timings. The calculation of the register's contents is directly extracted from =C2=A720.3.2.3 of the DaVinci TRM [1] MAX_TH_PS and MAX_TSU_PS are the worst case timings based on the Keystone2 and DaVinci datasheets. [1] : https://www.ti.com/lit/ug/spruh77c/spruh77c.pdf Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/davinci_nand.c | 79 +++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 4fb5c2623f5a..2a1b3cd49415 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,9 @@ #define MASK_ALE 0x08 #define MASK_CLE 0x10 =20 +#define MAX_TSU_PS 3000 /* Input setup time in ps */ +#define MAX_TH_PS 1600 /* Input hold time in ps */ + struct davinci_nand_pdata { uint32_t mask_ale; uint32_t mask_cle; @@ -120,6 +124,7 @@ struct davinci_nand_info { uint32_t core_chipsel; =20 struct clk *clk; + struct aemif_device *aemif; }; =20 static DEFINE_SPINLOCK(davinci_nand_lock); @@ -767,9 +772,82 @@ static int davinci_nand_exec_op(struct nand_chip *chip, return 0; } =20 +#define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP((ps) / 1000, (period_ns))) + +static int davinci_nand_setup_interface(struct nand_chip *chip, int chipnr, + const struct nand_interface_config *conf) +{ + struct davinci_nand_info *info =3D to_davinci_nand(nand_to_mtd(chip)); + const struct nand_sdr_timings *sdr; + struct aemif_cs_timings timings; + s32 cfg, min, cyc_ns; + int ret; + + cyc_ns =3D 1000000000 / clk_get_rate(info->clk); + + sdr =3D nand_get_sdr_timings(conf); + if (IS_ERR(sdr)) + return PTR_ERR(sdr); + + cfg =3D TO_CYCLES(sdr->tCLR_min, cyc_ns) - 1; + timings.rsetup =3D cfg > 0 ? cfg : 0; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tREA_max + MAX_TSU_PS, cyc_ns), + TO_CYCLES(sdr->tRP_min, cyc_ns)) - 1; + timings.rstrobe =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tCEA_max + MAX_TSU_PS, cyc_ns) - 2; + while ((s32)(timings.rsetup + timings.rstrobe) < min) + timings.rstrobe++; + + cfg =3D TO_CYCLES((s32)(MAX_TH_PS - sdr->tCHZ_max), cyc_ns) - 1; + timings.rhold =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tRC_min, cyc_ns) - 3; + while ((s32)(timings.rsetup + timings.rstrobe + timings.rhold) < min) + timings.rhold++; + + cfg =3D TO_CYCLES((s32)(sdr->tRHZ_max - (timings.rhold + 1) * cyc_ns * 10= 00), cyc_ns); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCHZ_max, cyc_ns)) - 1; + timings.ta =3D cfg > 0 ? cfg : 0; + + cfg =3D TO_CYCLES(sdr->tWP_min, cyc_ns) - 1; + timings.wstrobe =3D cfg > 0 ? cfg : 0; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tCLS_min, cyc_ns), TO_CYCLES(sdr->tALS_= min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCS_min, cyc_ns)) - 1; + timings.wsetup =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tDS_min, cyc_ns) - 2; + while ((s32)(timings.wsetup + timings.wstrobe) < min) + timings.wstrobe++; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tCLH_min, cyc_ns), TO_CYCLES(sdr->tALH_= min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCH_min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tDH_min, cyc_ns)) - 1; + timings.whold =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tWC_min, cyc_ns) - 2; + while ((s32)(timings.wsetup + timings.wstrobe + timings.whold) < min) + timings.whold++; + + dev_dbg(&info->pdev->dev, "RSETUP %x RSTROBE %x RHOLD %x\n", + timings.rsetup, timings.rstrobe, timings.rhold); + dev_dbg(&info->pdev->dev, "TA %x\n", timings.ta); + dev_dbg(&info->pdev->dev, "WSETUP %x WSTROBE %x WHOLD %x\n", + timings.wsetup, timings.wstrobe, timings.whold); + + ret =3D aemif_check_cs_timings(&timings); + if (ret || chipnr =3D=3D NAND_DATA_IFACE_CHECK_ONLY) + return ret; + + return aemif_set_cs_timings(info->aemif, info->core_chipsel, &timings); +} + static const struct nand_controller_ops davinci_nand_controller_ops =3D { .attach_chip =3D davinci_nand_attach_chip, .exec_op =3D davinci_nand_exec_op, + .setup_interface =3D davinci_nand_setup_interface, }; =20 static int nand_davinci_probe(struct platform_device *pdev) @@ -832,6 +910,7 @@ static int nand_davinci_probe(struct platform_device *p= dev) info->pdev =3D pdev; info->base =3D base; info->vaddr =3D vaddr; + info->aemif =3D dev_get_drvdata(pdev->dev.parent); =20 mtd =3D nand_to_mtd(&info->chip); mtd->dev.parent =3D &pdev->dev; --=20 2.47.0