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Mon, 02 Dec 2024 21:07:17 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nick Chan , Krzysztof Kozlowski , Neal Gompa Subject: [PATCH v5 01/10] dt-bindings: arm: apple: apple,pmgr: Add A7-A11 compatibles Date: Tue, 3 Dec 2024 13:05:31 +0800 Message-ID: <20241203050640.109378-2-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241203050640.109378-1-towinchenmi@gmail.com> References: <20241203050640.109378-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The blocks found on Apple A7-A11 SoCs are compatible with the existing driver so add their per-SoC compatibles. Acked-by: Krzysztof Kozlowski Acked-by: Hector Martin Acked-by: Neal Gompa Signed-off-by: Nick Chan --- Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/= Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml index 673277a7a224..5001f4d5a0dc 100644 --- a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -22,6 +22,11 @@ properties: compatible: items: - enum: + - apple,s5l8960x-pmgr + - apple,t7000-pmgr + - apple,s8000-pmgr + - apple,t8010-pmgr + - apple,t8015-pmgr - apple,t8103-pmgr - apple,t8112-pmgr - apple,t6000-pmgr --=20 2.47.1 From nobody Wed Dec 4 19:08:45 2024 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D33218132A; 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Mon, 02 Dec 2024 21:07:20 -0800 (PST) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-21586d40afasm33242385ad.270.2024.12.02.21.07.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 21:07:20 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nick Chan , Krzysztof Kozlowski , Neal Gompa Subject: [PATCH v5 02/10] dt-bindings: arm: apple: apple,pmgr-pwrstate: Add A7-A11 compatibles Date: Tue, 3 Dec 2024 13:05:32 +0800 Message-ID: <20241203050640.109378-3-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241203050640.109378-1-towinchenmi@gmail.com> References: <20241203050640.109378-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The blocks found on Apple A7-A11 SoCs are compatible with the existing driver so add their per-SoC compatible. Acked-by: Krzysztof Kozlowski Acked-by: Hector Martin Acked-by: Neal Gompa Signed-off-by: Nick Chan --- .../devicetree/bindings/power/apple,pmgr-pwrstate.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.ya= ml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml index 59a6af735a21..6e9a670eaf56 100644 --- a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -31,6 +31,11 @@ properties: compatible: items: - enum: + - apple,s5l8960x-pmgr-pwrstate + - apple,t7000-pmgr-pwrstate + - apple,s8000-pmgr-pwrstate + - apple,t8010-pmgr-pwrstate + - apple,t8015-pmgr-pwrstate - apple,t8103-pmgr-pwrstate - apple,t8112-pmgr-pwrstate - apple,t6000-pmgr-pwrstate --=20 2.47.1 From nobody Wed Dec 4 19:08:45 2024 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E169E186E5F; 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Mon, 02 Dec 2024 21:07:23 -0800 (PST) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-21586d40afasm33242385ad.270.2024.12.02.21.07.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 21:07:22 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nick Chan , Neal Gompa Subject: [PATCH v5 03/10] arm64: dts: apple: s5l8960x: Add PMGR node Date: Tue, 3 Dec 2024 13:05:33 +0800 Message-ID: <20241203050640.109378-4-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241203050640.109378-1-towinchenmi@gmail.com> References: <20241203050640.109378-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the PMGR node and all known power state subnodes. Since there are a large number of them, put them in a separate file to include. Acked-by: Hector Martin Acked-by: Neal Gompa Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi | 4 + arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi | 4 + arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi | 4 + arch/arm64/boot/dts/apple/s5l8960x-pmgr.dtsi | 610 ++++++++++++++++++ arch/arm64/boot/dts/apple/s5l8960x.dtsi | 13 + 5 files changed, 635 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/s5l8960x-pmgr.dtsi diff --git a/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi b/arch/arm64/boot/d= ts/apple/s5l8960x-5s.dtsi index 0b16adf07f79..51c081923657 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi @@ -49,3 +49,7 @@ switch-mute { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0 &ps_mipi_dsi>; +}; diff --git a/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi b/arch/arm64/boot= /dts/apple/s5l8960x-air1.dtsi index 741c5a9f21dd..7d6e799c933a 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi @@ -49,3 +49,7 @@ switch-mute { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0 &ps_dp>; +}; diff --git a/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi b/arch/arm64/boo= t/dts/apple/s5l8960x-mini2.dtsi index b27ef5680626..2ba846db2266 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi @@ -49,3 +49,7 @@ switch-mute { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0 &ps_dp>; +}; diff --git a/arch/arm64/boot/dts/apple/s5l8960x-pmgr.dtsi b/arch/arm64/boot= /dts/apple/s5l8960x-pmgr.dtsi new file mode 100644 index 000000000000..da265f484307 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s5l8960x-pmgr.dtsi @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple S5L8960X "A7" SoC + * + * Copyright (c) 2024 Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@20000 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@20008 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_secuart0: power-controller@200f0 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x200f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "secuart0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_secuart1: power-controller@200f8 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x200f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "secuart1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_cpm: power-controller@20010 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpm"; + apple,always-on; /* Core device */ + }; + + ps_lio: power-controller@20018 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "lio"; + apple,always-on; /* Core device */ + }; + + ps_iomux: power-controller@20020 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20020 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "iomux"; + apple,always-on; /* Core device */ + }; + + ps_aic: power-controller@20028 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20028 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aic"; + apple,always-on; /* Core device */ + }; + + ps_debug: power-controller@20030 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20030 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "debug"; + }; + + ps_dwi: power-controller@20038 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20038 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dwi"; + }; + + ps_gpio: power-controller@20040 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20040 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gpio"; + }; + + ps_mca0: power-controller@20048 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20048 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca1: power-controller@20050 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20050 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca2: power-controller@20058 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20058 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca3: power-controller@20060 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20060 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca4: power-controller@20068 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20068 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_pwm0: power-controller@20070 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20070 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pwm0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c0: power-controller@20078 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20078 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c1: power-controller@20080 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20080 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c2: power-controller@20088 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20088 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c3: power-controller@20090 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20090 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi0: power-controller@20098 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20098 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi1: power-controller@200a0 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x200a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi2: power-controller@200a8 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x200a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi3: power-controller@200b0 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x200b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart0: power-controller@200b8 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x200b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart1: power-controller@200c0 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x200c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart2: power-controller@200c8 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x200c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart3: power-controller@200d0 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x200d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart4: power-controller@200d8 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x200d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart5: power-controller@200e0 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x200e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart5"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart6: power-controller@200e8 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x200e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart6"; + power-domains =3D <&ps_sio_p>; + }; + + ps_sio_p: power-controller@20110 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_p"; + }; + + ps_usb: power-controller@20158 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20158 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb"; + }; + + ps_usbctrl: power-controller@20160 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20160 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbctrl"; + power-domains =3D <&ps_usb>; + }; + + ps_usb2host0: power-controller@20170 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20170 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@20180 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20180 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host1"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_disp_busmux: power-controller@201a8 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp_busmux"; + }; + + ps_media: power-controller@201d8 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "media"; + }; + + ps_isp: power-controller@201d0 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp"; + }; + + ps_msr: power-controller@201e0 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "msr"; + power-domains =3D <&ps_media>; + }; + + ps_jpg: power-controller@201e8 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "jpg"; + power-domains =3D <&ps_media>; + }; + + ps_disp0: power-controller@201b0 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0"; + power-domains =3D <&ps_disp_busmux>; + }; + + ps_aes0: power-controller@20100 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aes0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_sio: power-controller@20108 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio"; + power-domains =3D <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@20118 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsic0_phy"; + power-domains =3D <&ps_usb2host0>; + }; + + ps_hsic1_phy: power-controller@20120 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsic1_phy"; + power-domains =3D <&ps_usb2host0>; + }; + + ps_hsic2_phy: power-controller@20128 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsic2_phy"; + power-domains =3D <&ps_usb2host1>; + }; + + ps_ispsens0: power-controller@20130 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ispsens0"; + }; + + ps_ispsens1: power-controller@20138 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20138 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ispsens1"; + }; + + ps_mcc: power-controller@20140 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20140 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mcc"; + apple,always-on; /* Core device */ + }; + + ps_mcu: power-controller@20148 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20148 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mcu"; + apple,always-on; /* Core device */ + }; + + ps_amp: power-controller@20150 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20150 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "amp"; + apple,always-on; /* Core device */ + }; + + ps_usb2host0_ohci: power-controller@20168 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20168 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0_ohci"; + power-domains =3D <&ps_usb2host0>; + }; + + ps_usb2host1_ohci: power-controller@20178 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20178 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host1_ohci"; + power-domains =3D <&ps_usb2host1>; + }; + + ps_usbotg: power-controller@20188 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20188 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbotg"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_smx: power-controller@20190 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20190 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@20198 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_cp: power-controller@201a0 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cp"; + apple,always-on; /* Core device */ + }; + + ps_mipi_dsi: power-controller@201b8 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mipi_dsi"; + power-domains =3D <&ps_disp_busmux>; + }; + + ps_dp: power-controller@201c0 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dp"; + power-domains =3D <&ps_disp0>; + }; + + ps_disp1: power-controller@201c8 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp1"; + power-domains =3D <&ps_disp_busmux>; + }; + + ps_vdec: power-controller@201f0 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "vdec"; + power-domains =3D <&ps_media>; + }; + + ps_venc: power-controller@201f8 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc"; + power-domains =3D <&ps_media>; + }; + + ps_ans: power-controller@20200 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20200 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ans"; + }; + + ps_ans_dll: power-controller@20208 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20208 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ans_dll"; + power-domains =3D <&ps_ans>; + }; + + ps_gfx: power-controller@20218 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20218 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gfx"; + }; + + ps_sep: power-controller@20268 { + compatible =3D "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20268 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sep"; + power-domains =3D <&ps_secuart1>, <&ps_secuart0>; + apple,always-on; /* Locked on */ + }; +}; diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/= apple/s5l8960x.dtsi index 0218ecac1d83..7705215fbdc7 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi @@ -62,9 +62,18 @@ serial0: serial@20a0a0000 { /* Use the bootloader-enabled clocks for now. */ clocks =3D <&clkref>, <&clkref>; clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart0>; status =3D "disabled"; }; =20 + pmgr: power-management@20e000000 { + compatible =3D "apple,s5l8960x-pmgr", "apple,pmgr", "syscon", "simple-m= fd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0xe000000 0 0x24000>; + }; + wdt: watchdog@20e027000 { compatible =3D "apple,s5l8960x-wdt", "apple,wdt"; reg =3D <0x2 0x0e027000 0x0 0x1000>; @@ -78,11 +87,13 @@ aic: interrupt-controller@20e100000 { reg =3D <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells =3D <3>; interrupt-controller; + power-domains =3D <&ps_aic>; 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Mon, 02 Dec 2024 21:07:25 -0800 (PST) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-21586d40afasm33242385ad.270.2024.12.02.21.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 21:07:25 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nick Chan , Neal Gompa Subject: [PATCH v5 04/10] arm64: dts: apple: t7000: Add PMGR node Date: Tue, 3 Dec 2024 13:05:34 +0800 Message-ID: <20241203050640.109378-5-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241203050640.109378-1-towinchenmi@gmail.com> References: <20241203050640.109378-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the PMGR node and all known power state subnodes. Since there are a large number of them, put them in a separate file to include. Acked-by: Hector Martin Acked-by: Neal Gompa Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t7000-6.dtsi | 4 + arch/arm64/boot/dts/apple/t7000-j42d.dts | 1 + arch/arm64/boot/dts/apple/t7000-mini4.dtsi | 4 + arch/arm64/boot/dts/apple/t7000-n102.dts | 4 + arch/arm64/boot/dts/apple/t7000-pmgr.dtsi | 641 +++++++++++++++++++++ arch/arm64/boot/dts/apple/t7000.dtsi | 14 + 6 files changed, 668 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t7000-pmgr.dtsi diff --git a/arch/arm64/boot/dts/apple/t7000-6.dtsi b/arch/arm64/boot/dts/a= pple/t7000-6.dtsi index f60ea4a4a387..77d74d6af1c4 100644 --- a/arch/arm64/boot/dts/apple/t7000-6.dtsi +++ b/arch/arm64/boot/dts/apple/t7000-6.dtsi @@ -48,3 +48,7 @@ switch-mute { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0 &ps_mipi_dsi>; +}; diff --git a/arch/arm64/boot/dts/apple/t7000-j42d.dts b/arch/arm64/boot/dts= /apple/t7000-j42d.dts index 2231db6a739d..4de5e6a3f230 100644 --- a/arch/arm64/boot/dts/apple/t7000-j42d.dts +++ b/arch/arm64/boot/dts/apple/t7000-j42d.dts @@ -20,6 +20,7 @@ chosen { framebuffer0: framebuffer@0 { compatible =3D "apple,simple-framebuffer", "simple-framebuffer"; reg =3D <0 0 0 0>; /* To be filled by loader */ + power-domains =3D <&ps_disp0 &ps_dp>; /* Format properties will be added by loader */ status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/apple/t7000-mini4.dtsi b/arch/arm64/boot/d= ts/apple/t7000-mini4.dtsi index c64ddc402fda..e5a9656045f2 100644 --- a/arch/arm64/boot/dts/apple/t7000-mini4.dtsi +++ b/arch/arm64/boot/dts/apple/t7000-mini4.dtsi @@ -49,3 +49,7 @@ switch-mute { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0 &ps_dp>; +}; diff --git a/arch/arm64/boot/dts/apple/t7000-n102.dts b/arch/arm64/boot/dts= /apple/t7000-n102.dts index 9c55d339ba4e..99eb8a2b8c73 100644 --- a/arch/arm64/boot/dts/apple/t7000-n102.dts +++ b/arch/arm64/boot/dts/apple/t7000-n102.dts @@ -46,3 +46,7 @@ button-volup { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0 &ps_mipi_dsi>; +}; diff --git a/arch/arm64/boot/dts/apple/t7000-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/t7000-pmgr.dtsi new file mode 100644 index 000000000000..5948fa7afffc --- /dev/null +++ b/arch/arm64/boot/dts/apple/t7000-pmgr.dtsi @@ -0,0 +1,641 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T7000 "A8" SoC + * + * Copyright (c) 2024, Nick Chan + */ +&pmgr { + ps_cpu0: power-controller@20000 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@20008 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@20040 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20040 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_p: power-controller@201f8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_p"; + }; + + ps_lio: power-controller@20100 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "lio"; + apple,always-on; /* Core device */ + }; + + ps_iomux: power-controller@20108 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "iomux"; + apple,always-on; /* Core device */ + }; + + ps_aic: power-controller@20110 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aic"; + apple,always-on; /* Core device */ + }; + + ps_debug: power-controller@20118 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "debug"; + }; + + ps_dwi: power-controller@20120 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dwi"; + }; + + ps_gpio: power-controller@20128 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gpio"; + }; + + ps_mca0: power-controller@20130 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca1: power-controller@20138 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20138 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca2: power-controller@20140 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20140 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca3: power-controller@20148 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20148 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca4: power-controller@20150 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20150 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_pwm0: power-controller@20158 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20158 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pwm0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c0: power-controller@20160 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20160 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c1: power-controller@20168 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20168 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c2: power-controller@20170 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20170 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c3: power-controller@20178 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20178 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi0: power-controller@20180 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20180 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi1: power-controller@20188 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20188 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi2: power-controller@20190 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20190 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi3: power-controller@20198 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart0: power-controller@201a0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart1: power-controller@201a8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart2: power-controller@201b0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart3: power-controller@201b8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart4: power-controller@201c0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart5: power-controller@201c8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart5"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart6: power-controller@201d0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart6"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart7: power-controller@201d8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart7"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart8: power-controller@201e0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart8"; + power-domains =3D <&ps_sio_p>; + }; + + ps_aes0: power-controller@201e8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aes0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_sio: power-controller@201f0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio"; + power-domains =3D <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_usb: power-controller@20248 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20248 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb"; + }; + + ps_usbctrl: power-controller@20250 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20250 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbctrl"; + power-domains =3D <&ps_usb>; + }; + + ps_usb2host0: power-controller@20258 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20258 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@20268 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20268 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host1"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb2host2: power-controller@20278 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20278 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host2"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_disp_busmux: power-controller@202a8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp_busmux"; + }; + + ps_media: power-controller@202d8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "media"; + }; + + ps_isp: power-controller@202d0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp"; + }; + + ps_msr: power-controller@202e0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "msr"; + power-domains =3D <&ps_media>; + }; + + ps_jpg: power-controller@202e8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "jpg"; + power-domains =3D <&ps_media>; + }; + + ps_disp0: power-controller@202b0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0"; + power-domains =3D <&ps_disp_busmux>; + }; + + ps_disp1: power-controller@202c8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp1"; + power-domains =3D <&ps_disp_busmux>; + }; + + ps_pcie_ref: power-controller@20220 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20220 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_ref"; + }; + + ps_hsic0_phy: power-controller@20200 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20200 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsic0_phy"; + power-domains =3D <&ps_usb2host1>; + }; + + ps_hsic1_phy: power-controller@20208 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20208 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsic1_phy"; + power-domains =3D <&ps_usb2host2>; + }; + + ps_ispsens0: power-controller@20210 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20210 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ispsens0"; + }; + + ps_ispsens1: power-controller@20218 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20218 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ispsens1"; + }; + + ps_mcc: power-controller@20230 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20230 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_mcu: power-controller@20238 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20238 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mcu"; + apple,always-on; /* Core device */ + }; + + ps_amp: power-controller@20240 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20240 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "amp"; + apple,always-on; /* Core device */ + }; + + ps_usb2host0_ohci: power-controller@20260 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0_ohci"; + power-domains =3D <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@20288 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20288 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbotg"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_smx: power-controller@20290 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20290 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smx"; + apple,always-on; /* Apple Fabric, critical block */ + }; + + ps_sf: power-controller@20298 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20298 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sf"; + apple,always-on; /* Apple Fabric, critical block */ + }; + + ps_cp: power-controller@202a0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cp"; + apple,always-on; /* Core device */ + }; + + ps_mipi_dsi: power-controller@202b8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mipi_dsi"; + power-domains =3D <&ps_disp_busmux>; + }; + + ps_dp: power-controller@202c0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dp"; + power-domains =3D <&ps_disp0>; + }; + + ps_vdec: power-controller@202f0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "vdec"; + power-domains =3D <&ps_media>; + }; + + ps_ans: power-controller@20318 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20318 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ans"; + }; + + ps_venc: power-controller@20300 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20300 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc"; + power-domains =3D <&ps_media>; + }; + + ps_pcie: power-controller@20308 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20308 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie"; + }; + + ps_pcie_aux: power-controller@20310 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20310 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_aux"; + }; + + ps_gfx: power-controller@20320 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20320 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gfx"; + }; + + ps_sep: power-controller@20400 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20400 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sep"; + apple,always-on; /* Locked on */ + }; + + ps_venc_pipe: power-controller@21000 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x21000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe"; + power-domains =3D <&ps_venc>; + }; + + ps_venc_me0: power-controller@21008 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x21008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me0"; + power-domains =3D <&ps_venc>; + }; + + ps_venc_me1: power-controller@21010 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x21010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me1"; + power-domains =3D <&ps_venc>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t7000.dtsi b/arch/arm64/boot/dts/app= le/t7000.dtsi index a7cc29e84c84..ed1e9a62ba05 100644 --- a/arch/arm64/boot/dts/apple/t7000.dtsi +++ b/arch/arm64/boot/dts/apple/t7000.dtsi @@ -62,6 +62,7 @@ serial0: serial@20a0c0000 { /* Use the bootloader-enabled clocks for now. */ clocks =3D <&clkref>, <&clkref>; clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart0>; status =3D "disabled"; }; =20 @@ -74,9 +75,18 @@ serial6: serial@20a0d8000 { /* Use the bootloader-enabled clocks for now. */ clocks =3D <&clkref>, <&clkref>; clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart6>; status =3D "disabled"; }; =20 + pmgr: power-management@20e000000 { + compatible =3D "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0xe000000 0 0x24000>; + }; + wdt: watchdog@20e027000 { compatible =3D "apple,t7000-wdt", "apple,wdt"; reg =3D <0x2 0x0e027000 0x0 0x1000>; @@ -90,11 +100,13 @@ aic: interrupt-controller@20e100000 { reg =3D <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells =3D <3>; interrupt-controller; + power-domains =3D <&ps_aic>; }; =20 pinctrl: pinctrl@20e300000 { compatible =3D "apple,t7000-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x0e300000 0x0 0x100000>; + power-domains =3D <&ps_gpio>; =20 gpio-controller; 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Mon, 02 Dec 2024 21:07:28 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nick Chan , Neal Gompa Subject: [PATCH v5 05/10] arm64: dts: apple: t7001: Add PMGR node Date: Tue, 3 Dec 2024 13:05:35 +0800 Message-ID: <20241203050640.109378-6-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241203050640.109378-1-towinchenmi@gmail.com> References: <20241203050640.109378-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the PMGR node and all known power state subnodes. Since there are a large number of them, put them in a separate file to include. Acked-by: Hector Martin Acked-by: Neal Gompa Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t7001-air2.dtsi | 1 + arch/arm64/boot/dts/apple/t7001-pmgr.dtsi | 650 ++++++++++++++++++++++ arch/arm64/boot/dts/apple/t7001.dtsi | 13 + 3 files changed, 664 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t7001-pmgr.dtsi diff --git a/arch/arm64/boot/dts/apple/t7001-air2.dtsi b/arch/arm64/boot/dt= s/apple/t7001-air2.dtsi index 19fabd425c52..e4ec8c1977de 100644 --- a/arch/arm64/boot/dts/apple/t7001-air2.dtsi +++ b/arch/arm64/boot/dts/apple/t7001-air2.dtsi @@ -20,6 +20,7 @@ chosen { framebuffer0: framebuffer@0 { compatible =3D "apple,simple-framebuffer", "simple-framebuffer"; reg =3D <0 0 0 0>; /* To be filled by loader */ + power-domains =3D <&ps_disp0 &ps_dp>; /* Format properties will be added by loader */ status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/apple/t7001-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/t7001-pmgr.dtsi new file mode 100644 index 000000000000..7321cfdcd189 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t7001-pmgr.dtsi @@ -0,0 +1,650 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T7001 "A8X" SoC + * + * Copyright (c) 2024, Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@20000 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@20008 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpu2: power-controller@20010 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu2"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@20040 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20040 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_p: power-controller@201f8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_p"; + }; + + ps_lio: power-controller@20100 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "lio"; + apple,always-on; /* Core device */ + }; + + ps_iomux: power-controller@20108 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "iomux"; + apple,always-on; /* Core device */ + }; + + ps_aic: power-controller@20110 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aic"; + apple,always-on; /* Core device */ + }; + + ps_debug: power-controller@20118 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "debug"; + }; + + ps_dwi: power-controller@20120 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dwi"; + }; + + ps_gpio: power-controller@20128 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gpio"; + }; + + ps_mca0: power-controller@20130 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca1: power-controller@20138 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20138 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca2: power-controller@20140 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20140 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca3: power-controller@20148 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20148 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca4: power-controller@20150 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20150 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_pwm0: power-controller@20158 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20158 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pwm0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c0: power-controller@20160 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20160 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c1: power-controller@20168 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20168 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c2: power-controller@20170 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20170 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c3: power-controller@20178 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20178 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi0: power-controller@20180 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20180 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi1: power-controller@20188 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20188 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi2: power-controller@20190 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20190 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi3: power-controller@20198 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart0: power-controller@201a0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart1: power-controller@201a8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart2: power-controller@201b0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart3: power-controller@201b8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart4: power-controller@201c0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart5: power-controller@201c8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart5"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart6: power-controller@201d0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart6"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart7: power-controller@201d8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart7"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart8: power-controller@201e0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart8"; + power-domains =3D <&ps_sio_p>; + }; + + ps_aes0: power-controller@201e8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aes0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_sio: power-controller@201f0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x201f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio"; + power-domains =3D <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_usb: power-controller@20248 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20248 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb"; + }; + + ps_usbctrl: power-controller@20250 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20250 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbctrl"; + power-domains =3D <&ps_usb>; + }; + + ps_usb2host0: power-controller@20258 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20258 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@20268 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20268 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host1"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb2host2: power-controller@20278 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20278 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host2"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_disp_busmux: power-controller@202a8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp_busmux"; + }; + + ps_disp1_busmux: power-controller@202c0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp1_busmux"; + }; + + ps_media: power-controller@202d8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "media"; + }; + + ps_isp: power-controller@202d0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp"; + }; + + ps_msr: power-controller@202e0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "msr"; + power-domains =3D <&ps_media>; + }; + + ps_jpg: power-controller@202e8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "jpg"; + power-domains =3D <&ps_media>; + }; + + ps_disp0: power-controller@202b0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0"; + power-domains =3D <&ps_disp_busmux>; + }; + + ps_disp1: power-controller@202c8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp1"; + power-domains =3D <&ps_disp1_busmux>; + }; + + ps_pcie_ref: power-controller@20220 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20220 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_ref"; + }; + + ps_hsic0_phy: power-controller@20200 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20200 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsic0_phy"; + power-domains =3D <&ps_usb2host1>; + }; + + ps_hsic1_phy: power-controller@20208 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20208 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsic1_phy"; + power-domains =3D <&ps_usb2host2>; + }; + + ps_ispsens0: power-controller@20210 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20210 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ispsens0"; + }; + + ps_ispsens1: power-controller@20218 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20218 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ispsens1"; + }; + + ps_mcc: power-controller@20230 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20230 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_mcu: power-controller@20238 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20238 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mcu"; + apple,always-on; /* Core device */ + }; + + ps_amp: power-controller@20240 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20240 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "amp"; + apple,always-on; /* Core device */ + }; + + ps_usb2host0_ohci: power-controller@20260 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0_ohci"; + power-domains =3D <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@20288 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20288 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbotg"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_smx: power-controller@20290 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20290 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@20298 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20298 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_cp: power-controller@202a0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cp"; + apple,always-on; /* Core device */ + }; + + ps_dp: power-controller@202b8 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dp"; + power-domains =3D <&ps_disp0>; + }; + + ps_vdec: power-controller@202f0 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x202f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "vdec"; + power-domains =3D <&ps_media>; + }; + + ps_ans: power-controller@20318 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20318 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ans"; + }; + + ps_venc: power-controller@20300 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20300 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc"; + power-domains =3D <&ps_media>; + }; + + ps_pcie: power-controller@20308 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20308 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie"; + }; + + ps_pcie_aux: power-controller@20310 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20310 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_aux"; + }; + + ps_gfx: power-controller@20320 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20320 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gfx"; + }; + + ps_sep: power-controller@20400 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x20400 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sep"; + apple,always-on; /* Locked on */ + }; + + ps_venc_pipe: power-controller@21000 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x21000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe"; + power-domains =3D <&ps_venc>; + }; + + ps_venc_me0: power-controller@21008 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x21008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me0"; + power-domains =3D <&ps_venc>; + }; + + ps_venc_me1: power-controller@21010 { + compatible =3D "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x21010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me1"; + power-domains =3D <&ps_venc>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/app= le/t7001.dtsi index a76e034c85e3..c471f57cca0e 100644 --- a/arch/arm64/boot/dts/apple/t7001.dtsi +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -72,9 +72,18 @@ serial0: serial@20a0c0000 { /* Use the bootloader-enabled clocks for now. */ clocks =3D <&clkref>, <&clkref>; clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart0>; status =3D "disabled"; }; =20 + pmgr: power-management@20e000000 { + compatible =3D "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0xe000000 0 0x24000>; + }; + wdt: watchdog@20e027000 { compatible =3D "apple,t7000-wdt", "apple,wdt"; reg =3D <0x2 0x0e027000 0x0 0x1000>; @@ -88,11 +97,13 @@ aic: interrupt-controller@20e100000 { reg =3D <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells =3D <3>; interrupt-controller; + power-domains =3D <&ps_aic>; }; =20 pinctrl: pinctrl@20e300000 { compatible =3D "apple,t7000-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x0e300000 0x0 0x100000>; + power-domains =3D <&ps_gpio>; =20 gpio-controller; #gpio-cells =3D <2>; @@ -121,3 +132,5 @@ timer { ; }; }; + +#include "t7001-pmgr.dtsi" --=20 2.47.1 From nobody Wed Dec 4 19:08:45 2024 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3ED94189F56; Tue, 3 Dec 2024 05:07:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733202455; cv=none; b=q0NOPlLB6HjXH5AaG1qWUhSuPlcerl/zJu6vT/vf5NOZOLyHsCnVRLnlmN+7b0+lckLUSPSM7UDk6mQYv0PBM2ndg+wx2/3ulGq0Z9mHL24zr9WqanBkfsR89xZe9mX8Zbw0LK6ElhWBzqcauIHU1F9cxawlvfEqnkJ9APixGh0= ARC-Message-Signature: i=1; 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Mon, 02 Dec 2024 21:07:32 -0800 (PST) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-21586d40afasm33242385ad.270.2024.12.02.21.07.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 21:07:31 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nick Chan , Neal Gompa Subject: [PATCH v5 06/10] arm64: dts: apple: s8000: Add PMGR nodes Date: Tue, 3 Dec 2024 13:05:36 +0800 Message-ID: <20241203050640.109378-7-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241203050640.109378-1-towinchenmi@gmail.com> References: <20241203050640.109378-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the two PMGR nodes and all known power state subnodes. Since there are a large number of them, put them in a separate file to include. Acked-by: Hector Martin Acked-by: Neal Gompa Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s8000-pmgr.dtsi | 757 +++++++++++++++++++++ arch/arm64/boot/dts/apple/s8000.dtsi | 22 + arch/arm64/boot/dts/apple/s800x-6s.dtsi | 4 + arch/arm64/boot/dts/apple/s800x-ipad5.dtsi | 4 + arch/arm64/boot/dts/apple/s800x-se.dtsi | 4 + 5 files changed, 791 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/s8000-pmgr.dtsi diff --git a/arch/arm64/boot/dts/apple/s8000-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/s8000-pmgr.dtsi new file mode 100644 index 000000000000..196b8e745a95 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8000-pmgr.dtsi @@ -0,0 +1,757 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple S8000/3 "A9" SoC + * + * Copyright (c) 2024 Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80040 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80150 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80150 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_busif"; + }; + + ps_sio_p: power-controller@80158 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80158 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_p"; + power-domains =3D <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gpio"; + }; + + ps_pms: power-controller@80120 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms"; + apple,always-on; /* Core device */ + }; + + ps_pcie_ref: power-controller@80148 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80148 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_ref"; + }; + + ps_mca0: power-controller@80168 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80168 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca1: power-controller@80170 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80170 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca2: power-controller@80178 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80178 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca3: power-controller@80180 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80180 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca4: power-controller@80188 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80188 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_pwm0: power-controller@80190 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80190 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pwm0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c0: power-controller@80198 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801a0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801a8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801b0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi0: power-controller@801b8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi1: power-controller@801c0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi2: power-controller@801c8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi3: power-controller@801d0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart0: power-controller@801d8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart1: power-controller@801e0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart2: power-controller@801e8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart3: power-controller@801f0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart4: power-controller@801f8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_sio: power-controller@80160 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80160 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio"; + power-domains =3D <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@80128 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsic0_phy"; + power-domains =3D <&ps_usb2host1>; + }; + + ps_hsic1_phy: power-controller@80130 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsic1_phy"; + power-domains =3D <&ps_usb2host2>; + }; + + ps_isp_sens0: power-controller@80138 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80138 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80140 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80140 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens1"; + }; + + ps_usb: power-controller@80250 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80250 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb"; + }; + + ps_usbctrl: power-controller@80258 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80258 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbctrl"; + power-domains =3D <&ps_usb>; + }; + + ps_usb2host0: power-controller@80260 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@80270 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80270 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host1"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb2host2: power-controller@80280 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80280 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host2"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_rtmux: power-controller@802a8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "rtmux"; + }; + + ps_media: power-controller@802d0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "media"; + }; + + ps_isp: power-controller@802c8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp"; + power-domains =3D <&ps_rtmux>; + }; + + ps_msr: power-controller@802e0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "msr"; + power-domains =3D <&ps_media>; + }; + + ps_jpg: power-controller@802d8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "jpg"; + power-domains =3D <&ps_media>; + }; + + ps_disp0: power-controller@802b0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0"; + power-domains =3D <&ps_rtmux>; + }; + + ps_pmp: power-controller@802e8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pmp"; + }; + + ps_pms_sram: power-controller@802f0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms_sram"; + }; + + ps_uart5: power-controller@80200 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80200 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart5"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart6: power-controller@80208 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80208 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart6"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart7: power-controller@80210 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80210 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart7"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart8: power-controller@80218 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80218 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart8"; + power-domains =3D <&ps_sio_p>; + }; + + ps_aes0: power-controller@80220 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80220 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aes0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mcc: power-controller@80228 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80228 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80230 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80230 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80238 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80238 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80240 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80240 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80248 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80248 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_usb2host0_ohci: power-controller@80268 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80268 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0_ohci"; + power-domains =3D <&ps_usb2host0>; + }; + + ps_usb2host1_ohci: power-controller@80278 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80278 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host1_ohci"; + power-domains =3D <&ps_usb2host1>; + }; + + ps_usb2host2_ohci: power-controller@80288 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80288 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host2_ohci"; + power-domains =3D <&ps_usb2host2>; + }; + + ps_usbotg: power-controller@80290 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80290 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbotg"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_smx: power-controller@80298 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80298 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802a0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mipi_dsi: power-controller@802b8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mipi_dsi"; + power-domains =3D <&ps_rtmux>; + }; + + ps_dp: power-controller@802c0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dp"; + power-domains =3D <&ps_disp0>; + }; + + ps_vdec: power-controller@802f8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "vdec"; + power-domains =3D <&ps_media>; + }; + + ps_venc: power-controller@80308 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80308 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc"; + power-domains =3D <&ps_media>; + }; + + ps_pcie: power-controller@80310 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80310 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie"; + }; + + ps_pcie_aux: power-controller@80318 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80318 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_aux"; + }; + + ps_pcie_link0: power-controller@80320 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80320 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_link0"; + power-domains =3D <&ps_pcie>; + }; + + ps_pcie_link1: power-controller@80328 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80328 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_link1"; + power-domains =3D <&ps_pcie>; + }; + + ps_pcie_link2: power-controller@80330 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80330 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_link2"; + power-domains =3D <&ps_pcie>; + }; + + ps_pcie_link3: power-controller@80338 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80338 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_link3"; + power-domains =3D <&ps_pcie>; + }; + + ps_gfx: power-controller@80340 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80340 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gfx"; + }; + + ps_sep: power-controller@80400 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80400 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sep"; + apple,always-on; /* Locked on */ + }; + + ps_venc_pipe: power-controller@88000 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe"; + power-domains =3D <&ps_venc>; + }; + + ps_venc_me0: power-controller@88008 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me0"; + }; + + ps_venc_me1: power-controller@88010 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop: power-controller@80000 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop"; + power-domains =3D <&ps_aop_busif &ps_aop_cpu &ps_aop_filter>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80008 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "debug"; + }; + + ps_aop_gpio: power-controller@80010 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_gpio"; + power-domains =3D <&ps_aop>; + }; + + ps_aop_cpu: power-controller@80040 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80040 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_cpu"; + }; + + ps_aop_filter: power-controller@80048 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80048 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_filter"; + }; + + ps_aop_busif: power-controller@80050 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80050 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_busif"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/s8000.dtsi b/arch/arm64/boot/dts/app= le/s8000.dtsi index 6e9046ea106c..84d6b4939ac4 100644 --- a/arch/arm64/boot/dts/apple/s8000.dtsi +++ b/arch/arm64/boot/dts/apple/s8000.dtsi @@ -61,19 +61,30 @@ serial0: serial@20a0c0000 { /* Use the bootloader-enabled clocks for now. */ clocks =3D <&clkref>, <&clkref>; clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart0>; status =3D "disabled"; }; =20 + pmgr: power-management@20e000000 { + compatible =3D "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0xe000000 0 0x8c000>; + }; + aic: interrupt-controller@20e100000 { compatible =3D "apple,s8000-aic", "apple,aic"; reg =3D <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells =3D <3>; interrupt-controller; + power-domains =3D <&ps_aic>; }; =20 pinctrl_ap: pinctrl@20f100000 { compatible =3D "apple,s8000-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x0f100000 0x0 0x100000>; + power-domains =3D <&ps_gpio>; =20 gpio-controller; #gpio-cells =3D <2>; @@ -95,6 +106,7 @@ pinctrl_ap: pinctrl@20f100000 { pinctrl_aop: pinctrl@2100f0000 { compatible =3D "apple,s8000-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x100f0000 0x0 0x100000>; + power-domains =3D <&ps_aop_gpio>; =20 gpio-controller; #gpio-cells =3D <2>; @@ -113,6 +125,14 @@ pinctrl_aop: pinctrl@2100f0000 { ; }; =20 + pmgr_mini: power-management@210200000 { + compatible =3D "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0x10200000 0 0x84000>; + }; + wdt: watchdog@2102b0000 { compatible =3D "apple,s8000-wdt", "apple,wdt"; reg =3D <0x2 0x102b0000 0x0 0x4000>; @@ -132,6 +152,8 @@ timer { }; }; =20 +#include "s8000-pmgr.dtsi" + /* * The A9 was made by two separate fabs on two different process * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made diff --git a/arch/arm64/boot/dts/apple/s800x-6s.dtsi b/arch/arm64/boot/dts/= apple/s800x-6s.dtsi index 49b04db310c6..1dcf80cc2920 100644 --- a/arch/arm64/boot/dts/apple/s800x-6s.dtsi +++ b/arch/arm64/boot/dts/apple/s800x-6s.dtsi @@ -47,3 +47,7 @@ switch-mute { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0 &ps_mipi_dsi>; +}; diff --git a/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi b/arch/arm64/boot/d= ts/apple/s800x-ipad5.dtsi index 32570ed3cdf0..c1701e81f0c1 100644 --- a/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi +++ b/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi @@ -41,3 +41,7 @@ button-volup { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0 &ps_dp>; +}; diff --git a/arch/arm64/boot/dts/apple/s800x-se.dtsi b/arch/arm64/boot/dts/= apple/s800x-se.dtsi index a1a5690e8371..deb7c7cc90f6 100644 --- a/arch/arm64/boot/dts/apple/s800x-se.dtsi +++ b/arch/arm64/boot/dts/apple/s800x-se.dtsi @@ -47,3 +47,7 @@ switch-mute { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0 &ps_mipi_dsi>; +}; --=20 2.47.1 From nobody Wed Dec 4 19:08:45 2024 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAF7918B463; Tue, 3 Dec 2024 05:07:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733202458; cv=none; b=BpmLHcykucz9IuzMhKpsCdpo8aBKGOeB9G39LDdiCNkbnJ0/FY7h1QOy7bOtr0ya/z9MaOZJH2e6qXxFqNY3N0RdyXjUp3AUaT+SaWN8eaUt6BjBBtxbLiSmT5uk+gF/AyStJ5TD0KIXNfni85W7qxYf8D8+BbjXQQ4bjV+JOYM= ARC-Message-Signature: i=1; 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Mon, 02 Dec 2024 21:07:35 -0800 (PST) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-21586d40afasm33242385ad.270.2024.12.02.21.07.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 21:07:34 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nick Chan , Neal Gompa Subject: [PATCH v5 07/10] arm64: dts: apple: s8001: Add PMGR nodes Date: Tue, 3 Dec 2024 13:05:37 +0800 Message-ID: <20241203050640.109378-8-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241203050640.109378-1-towinchenmi@gmail.com> References: <20241203050640.109378-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the two PMGR nodes and all known power state subnodes. Since there are a large number of them, put them in a separate file to include. Acked-by: Hector Martin Acked-by: Neal Gompa Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s8001-common.dtsi | 1 + .../arm64/boot/dts/apple/s8001-j98a-j99a.dtsi | 26 + arch/arm64/boot/dts/apple/s8001-j98a.dts | 1 + arch/arm64/boot/dts/apple/s8001-j99a.dts | 1 + arch/arm64/boot/dts/apple/s8001-pmgr.dtsi | 822 ++++++++++++++++++ arch/arm64/boot/dts/apple/s8001.dtsi | 22 + 6 files changed, 873 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi create mode 100644 arch/arm64/boot/dts/apple/s8001-pmgr.dtsi diff --git a/arch/arm64/boot/dts/apple/s8001-common.dtsi b/arch/arm64/boot/= dts/apple/s8001-common.dtsi index e94d0e77653a..91b06e113894 100644 --- a/arch/arm64/boot/dts/apple/s8001-common.dtsi +++ b/arch/arm64/boot/dts/apple/s8001-common.dtsi @@ -24,6 +24,7 @@ chosen { framebuffer0: framebuffer@0 { compatible =3D "apple,simple-framebuffer", "simple-framebuffer"; reg =3D <0 0 0 0>; /* To be filled by loader */ + power-domains =3D <&ps_disp0 &ps_dp0>; /* Format properties will be added by loader */ status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi b/arch/arm64/bo= ot/dts/apple/s8001-j98a-j99a.dtsi new file mode 100644 index 000000000000..e66a4c1c138f --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPad Pro (12.9-inch) + * + * This file contains parts common to iPad Pro (12.9-inch). + * + * target-type: J98a, J99a + * + * Copyright (c) 2024, Nick Chan + */ + +&ps_dcs4 { + apple,always-on; /* LPDDR4 interface */ +}; + +&ps_dcs5 { + apple,always-on; /* LPDDR4 interface */ +}; + +&ps_dcs6 { + apple,always-on; /* LPDDR4 interface */ +}; + +&ps_dcs7 { + apple,always-on; /* LPDDR4 interface */ +}; diff --git a/arch/arm64/boot/dts/apple/s8001-j98a.dts b/arch/arm64/boot/dts= /apple/s8001-j98a.dts index 6d6b841e7ab0..162eca05c2d9 100644 --- a/arch/arm64/boot/dts/apple/s8001-j98a.dts +++ b/arch/arm64/boot/dts/apple/s8001-j98a.dts @@ -7,6 +7,7 @@ /dts-v1/; =20 #include "s8001-pro.dtsi" +#include "s8001-j98a-j99a.dtsi" =20 / { compatible =3D "apple,j98a", "apple,s8001", "apple,arm-platform"; diff --git a/arch/arm64/boot/dts/apple/s8001-j99a.dts b/arch/arm64/boot/dts= /apple/s8001-j99a.dts index d20194b1cae7..7b765820c69e 100644 --- a/arch/arm64/boot/dts/apple/s8001-j99a.dts +++ b/arch/arm64/boot/dts/apple/s8001-j99a.dts @@ -7,6 +7,7 @@ /dts-v1/; =20 #include "s8001-pro.dtsi" +#include "s8001-j98a-j99a.dtsi" =20 / { compatible =3D "apple,j99a", "apple,s8001", "apple,arm-platform"; diff --git a/arch/arm64/boot/dts/apple/s8001-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/s8001-pmgr.dtsi new file mode 100644 index 000000000000..859ab77ae92b --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8001-pmgr.dtsi @@ -0,0 +1,822 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple S8001 "A9X" SoC + * + * Copyright (c) 2024 Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80040 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80148 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80148 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_busif"; + }; + + ps_sio_p: power-controller@80150 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80150 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_p"; + power-domains =3D <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gpio"; + }; + + ps_pcie_ref: power-controller@80140 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80140 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_ref"; + }; + + ps_mca0: power-controller@80160 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80160 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca1: power-controller@80168 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80168 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca2: power-controller@80170 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80170 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca3: power-controller@80178 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80178 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca4: power-controller@80180 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80180 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_pwm0: power-controller@80188 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80188 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pwm0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c0: power-controller@80190 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80190 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c1: power-controller@80198 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801a0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801a8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi0: power-controller@801b0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi1: power-controller@801b8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi2: power-controller@801c0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi3: power-controller@801c8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart0: power-controller@801d0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart1: power-controller@801d8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart2: power-controller@801e0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart3: power-controller@801e8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart4: power-controller@801f0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart5: power-controller@801f8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart5"; + power-domains =3D <&ps_sio_p>; + }; + + ps_sio: power-controller@80158 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80158 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio"; + power-domains =3D <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@80128 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsic0_phy"; + power-domains =3D <&ps_usb2host1>; + }; + + ps_isp_sens0: power-controller@80130 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80138 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80138 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens1"; + }; + + ps_pms: power-controller@80120 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms"; + apple,always-on; /* Core device */ + }; + + ps_usb: power-controller@80278 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80278 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb"; + }; + + ps_usbctrl: power-controller@80280 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80280 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbctrl"; + power-domains =3D <&ps_usb>; + }; + + ps_usb2host0: power-controller@80288 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80288 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@80298 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80298 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host1"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb2host2: power-controller@802a8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host2"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_rtmux: power-controller@802d0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "rtmux"; + apple,always-on; /* Core device */ + }; + + ps_disp1mux: power-controller@802e8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp1mux"; + }; + + ps_disp0: power-controller@802d8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0"; + power-domains =3D <&ps_rtmux>; + }; + + ps_disp1: power-controller@802f0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp1"; + power-domains =3D <&ps_disp1mux>; + }; + + ps_uart6: power-controller@80200 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80200 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart6"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart7: power-controller@80208 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80208 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart7"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart8: power-controller@80210 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80210 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart8"; + power-domains =3D <&ps_sio_p>; + }; + + ps_aes0: power-controller@80218 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80218 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aes0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mcc: power-controller@80230 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80230 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80238 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80238 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80240 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80240 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80248 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80248 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80250 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80250 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs4: power-controller@80258 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80258 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs4"; + }; + + ps_dcs5: power-controller@80260 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs5"; + }; + + ps_dcs6: power-controller@80268 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80268 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs6"; + }; + + ps_dcs7: power-controller@80270 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80270 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs7"; + }; + + ps_usb2host0_ohci: power-controller@80290 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80290 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0_ohci"; + power-domains =3D <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@802b8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbotg"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_smx: power-controller@802c0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802c8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_dp0: power-controller@802e0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dp0"; + power-domains =3D <&ps_disp0>; + }; + + ps_dp1: power-controller@802f8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dp1"; + power-domains =3D <&ps_disp1>; + }; + + ps_dpa0: power-controller@80220 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80220 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dpa0"; + }; + + ps_dpa1: power-controller@80228 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80228 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dpa1"; + }; + + ps_media: power-controller@80308 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80308 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "media"; + }; + + ps_isp: power-controller@80300 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80300 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp"; + power-domains =3D <&ps_rtmux>; + }; + + ps_msr: power-controller@80318 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80318 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "msr"; + power-domains =3D <&ps_media>; + }; + + ps_jpg: power-controller@80310 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80310 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "jpg"; + power-domains =3D <&ps_media>; + }; + + ps_venc: power-controller@80340 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80340 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc"; + power-domains =3D <&ps_media>; + }; + + ps_pcie: power-controller@80348 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80348 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie"; + }; + + ps_srs: power-controller@80390 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80390 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "srs"; + power-domains =3D <&ps_media>; + }; + + ps_pcie_aux: power-controller@80350 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80350 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_aux"; + }; + + ps_pcie_link0: power-controller@80358 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80358 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_link0"; + power-domains =3D <&ps_pcie>; + }; + + ps_pcie_link1: power-controller@80360 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80360 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_link1"; + power-domains =3D <&ps_pcie>; + }; + + ps_pcie_link2: power-controller@80368 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80368 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_link2"; + power-domains =3D <&ps_pcie>; + }; + + ps_pcie_link3: power-controller@80370 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80370 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_link3"; + power-domains =3D <&ps_pcie>; + }; + + ps_pcie_link4: power-controller@80378 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80378 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_link4"; + power-domains =3D <&ps_pcie>; + }; + + ps_pcie_link5: power-controller@80380 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80380 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_link5"; + power-domains =3D <&ps_pcie>; + }; + + ps_vdec: power-controller@80330 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80330 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "vdec"; + power-domains =3D <&ps_media>; + }; + + ps_gfx: power-controller@80388 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80388 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gfx"; + }; + + ps_pmp: power-controller@80320 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80320 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pmp"; + }; + + ps_pms_sram: power-controller@80328 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80328 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms_sram"; + }; + + ps_sep: power-controller@80400 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80400 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sep"; + apple,always-on; /* Locked on*/ + }; + + ps_venc_pipe: power-controller@88000 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe"; + power-domains =3D <&ps_venc>; + }; + + ps_venc_me0: power-controller@88008 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me0"; + }; + + ps_venc_me1: power-controller@88010 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop: power-controller@80000 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop"; + power-domains =3D <&ps_aop_cpu &ps_aop_filter &ps_aop_busif>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80008 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "debug"; + }; + + ps_aop_gpio: power-controller@80010 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_gpio"; + }; + + ps_aop_cpu: power-controller@80040 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80040 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_cpu"; + }; + + ps_aop_filter: power-controller@80048 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80048 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_filter"; + }; + + ps_aop_busif: power-controller@80050 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80050 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_busif"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/app= le/s8001.dtsi index 23ee3238844d..3963c6d8ca5e 100644 --- a/arch/arm64/boot/dts/apple/s8001.dtsi +++ b/arch/arm64/boot/dts/apple/s8001.dtsi @@ -61,19 +61,30 @@ serial0: serial@20a0c0000 { /* Use the bootloader-enabled clocks for now. */ clocks =3D <&clkref>, <&clkref>; clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart0>; status =3D "disabled"; }; =20 + pmgr: power-management@20e000000 { + compatible =3D "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0xe000000 0 0x8c000>; + }; + aic: interrupt-controller@20e100000 { compatible =3D "apple,s8000-aic", "apple,aic"; reg =3D <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells =3D <3>; interrupt-controller; + power-domains =3D <&ps_aic>; }; =20 pinctrl_ap: pinctrl@20f100000 { compatible =3D "apple,s8000-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x0f100000 0x0 0x100000>; + power-domains =3D <&ps_gpio>; =20 gpio-controller; #gpio-cells =3D <2>; @@ -95,6 +106,7 @@ pinctrl_ap: pinctrl@20f100000 { pinctrl_aop: pinctrl@2100f0000 { compatible =3D "apple,s8000-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x100f0000 0x0 0x100000>; + power-domains =3D <&ps_aop_gpio>; =20 gpio-controller; #gpio-cells =3D <2>; @@ -113,6 +125,14 @@ pinctrl_aop: pinctrl@2100f0000 { ; }; =20 + pmgr_mini: power-management@210200000 { + compatible =3D "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0x10200000 0 0x84000>; + }; + wdt: watchdog@2102b0000 { compatible =3D "apple,s8000-wdt", "apple,wdt"; reg =3D <0x2 0x102b0000 0x0 0x4000>; @@ -131,3 +151,5 @@ timer { ; }; }; + +#include "s8001-pmgr.dtsi" --=20 2.47.1 From nobody Wed Dec 4 19:08:45 2024 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92C9618FC91; Tue, 3 Dec 2024 05:07:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733202462; cv=none; b=tknZ1xidIqGVWQ10Rm0e6wI+2GnDSjAJ5eMBs8nCHwxyI2H2i6xchtSr+C1WGkkMRjsx4QO3N1EJRpEaMHxzNpJ3XCtw+kJnDx6Tq+HSyy3WBwsFCP9Ka9+jINZzj1srbeR0vEVcZP/UtdUh5WQzq4JetzQjgfPRQhbmSQwP5js= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733202462; c=relaxed/simple; bh=Tpt2z8w5KvnBZJl4letuo1pLsHJMR7WpKDLS/RbngFs=; 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Mon, 02 Dec 2024 21:07:38 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nick Chan , Neal Gompa Subject: [PATCH v5 08/10] arm64: dts: apple: t8010: Add PMGR nodes Date: Tue, 3 Dec 2024 13:05:38 +0800 Message-ID: <20241203050640.109378-9-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241203050640.109378-1-towinchenmi@gmail.com> References: <20241203050640.109378-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the two PMGR nodes and all known power state subnodes. Since there are a large number of them, put them in a separate file to include. Acked-by: Hector Martin Acked-by: Neal Gompa Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8010-7.dtsi | 4 + arch/arm64/boot/dts/apple/t8010-ipad6.dtsi | 4 + arch/arm64/boot/dts/apple/t8010-n112.dts | 4 + arch/arm64/boot/dts/apple/t8010-pmgr.dtsi | 772 +++++++++++++++++++++ arch/arm64/boot/dts/apple/t8010.dtsi | 22 + 5 files changed, 806 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t8010-pmgr.dtsi diff --git a/arch/arm64/boot/dts/apple/t8010-7.dtsi b/arch/arm64/boot/dts/a= pple/t8010-7.dtsi index 1332fd73f50f..91fae47d25d0 100644 --- a/arch/arm64/boot/dts/apple/t8010-7.dtsi +++ b/arch/arm64/boot/dts/apple/t8010-7.dtsi @@ -41,3 +41,7 @@ switch-mute { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0_fe &ps_disp0_be &ps_mipi_dsi>; +}; diff --git a/arch/arm64/boot/dts/apple/t8010-ipad6.dtsi b/arch/arm64/boot/d= ts/apple/t8010-ipad6.dtsi index 81696c6e302c..b83fe153763e 100644 --- a/arch/arm64/boot/dts/apple/t8010-ipad6.dtsi +++ b/arch/arm64/boot/dts/apple/t8010-ipad6.dtsi @@ -42,3 +42,7 @@ button-volup { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0_fe &ps_disp0_be &ps_dp>; +}; diff --git a/arch/arm64/boot/dts/apple/t8010-n112.dts b/arch/arm64/boot/dts= /apple/t8010-n112.dts index 6e71c3cb5d92..48fdbedf74da 100644 --- a/arch/arm64/boot/dts/apple/t8010-n112.dts +++ b/arch/arm64/boot/dts/apple/t8010-n112.dts @@ -45,3 +45,7 @@ button-volup { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0_fe &ps_disp0_be &ps_mipi_dsi>; +}; diff --git a/arch/arm64/boot/dts/apple/t8010-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/t8010-pmgr.dtsi new file mode 100644 index 000000000000..6d451088616a --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8010-pmgr.dtsi @@ -0,0 +1,772 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8010 "A10" SoC + * + * Copyright (c) 2024 Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80040 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80160 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80160 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_busif"; + }; + + ps_sio_p: power-controller@80168 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80168 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_p"; + power-domains =3D <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gpio"; + }; + + ps_pms: power-controller@80120 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms"; + apple,always-on; /* Core device */ + }; + + ps_pcie_ref: power-controller@80148 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80148 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_ref"; + }; + + ps_socuvd: power-controller@80150 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80150 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "socuvd"; + }; + + ps_mca0: power-controller@80178 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80178 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca1: power-controller@80180 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80180 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca2: power-controller@80188 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80188 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca3: power-controller@80190 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80190 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca4: power-controller@80198 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_pwm0: power-controller@801a0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pwm0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c0: power-controller@801a8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801b0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801b8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801c0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi0: power-controller@801c8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi1: power-controller@801d0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi2: power-controller@801d8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi3: power-controller@801e0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart0: power-controller@801e8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart1: power-controller@801f0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart2: power-controller@801f8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_sio: power-controller@80170 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80170 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio"; + power-domains =3D <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@80128 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsic0_phy"; + power-domains =3D <&ps_usb2host1>; + }; + + ps_isp_sens0: power-controller@80130 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80138 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80138 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens1"; + }; + + ps_isp_sens2: power-controller@80140 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80140 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens2"; + }; + + ps_usb: power-controller@80268 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80268 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb"; + }; + + ps_usbctrl: power-controller@80270 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80270 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbctrl"; + power-domains =3D <&ps_usb>; + }; + + ps_usb2host0: power-controller@80278 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80278 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@80288 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80288 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host1"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_rtmux: power-controller@802a8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "rtmux"; + }; + + ps_media: power-controller@802d8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "media"; + }; + + ps_isp_sys: power-controller@802d0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sys"; + power-domains =3D <&ps_rtmux>; + }; + + ps_msr: power-controller@802e8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "msr"; + power-domains =3D <&ps_media>; + }; + + ps_jpg: power-controller@802e0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "jpg"; + power-domains =3D <&ps_media>; + }; + + ps_disp0_fe: power-controller@802b0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_fe"; + power-domains =3D <&ps_rtmux>; + }; + + ps_disp0_be: power-controller@802b8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_be"; + power-domains =3D <&ps_disp0_fe>; + }; + + ps_pmp: power-controller@802f0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pmp"; + }; + + ps_pms_sram: power-controller@802f8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms_sram"; + }; + + ps_uart3: power-controller@80200 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80200 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart4: power-controller@80208 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80208 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart5: power-controller@80210 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80210 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart5"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart6: power-controller@80218 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80218 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart6"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart7: power-controller@80220 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80220 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart7"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart8: power-controller@80228 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80228 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart8"; + power-domains =3D <&ps_sio_p>; + }; + + ps_hfd0: power-controller@80238 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80238 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hfd0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mcc: power-controller@80240 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80240 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80248 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80248 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80250 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80250 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80258 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80258 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80260 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_usb2host0_ohci: power-controller@80280 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80280 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0_ohci"; + power-domains =3D <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@80290 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80290 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbotg"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_smx: power-controller@80298 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80298 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802a0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mipi_dsi: power-controller@802c0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mipi_dsi"; + power-domains =3D <&ps_disp0_be>; + }; + + ps_dp: power-controller@802c8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dp"; + power-domains =3D <&ps_disp0_be>; + }; + + ps_venc_sys: power-controller@80310 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80310 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_sys"; + power-domains =3D <&ps_media>; + }; + + ps_pcie: power-controller@80318 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80318 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie"; + }; + + ps_pcie_aux: power-controller@80320 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80320 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_aux"; + }; + + ps_vdec0: power-controller@80300 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80300 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "vdec0"; + power-domains =3D <&ps_media>; + }; + + ps_gfx: power-controller@80328 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80328 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gfx"; + }; + + ps_sep: power-controller@80400 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80400 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sep"; + apple,always-on; /* Locked on */ + }; + + ps_isp_rsts0: power-controller@84000 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_rsts0"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_rsts1: power-controller@84008 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_rsts1"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_vis: power-controller@84010 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_vis"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_be: power-controller@84018 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_be"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_pearl: power-controller@84020 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84020 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_pearl"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_dprx: power-controller@84028 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84028 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dprx"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_venc_pipe4: power-controller@88000 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe4"; + power-domains =3D <&ps_venc_sys>; + }; + + ps_venc_pipe5: power-controller@88008 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe5"; + power-domains =3D <&ps_venc_sys>; + }; + + ps_venc_me0: power-controller@88010 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me0"; + }; + + ps_venc_me1: power-controller@88018 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop: power-controller@80000 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop"; + power-domains =3D <&ps_aop_cpu &ps_aop_busif &ps_aop_filter>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80008 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "debug"; + }; + + ps_aop_gpio: power-controller@80010 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_gpio"; + }; + + ps_aop_cpu: power-controller@80048 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80048 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_cpu"; + }; + + ps_aop_filter: power-controller@80050 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80050 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_filter"; + }; + + ps_aop_busif: power-controller@80058 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80058 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_busif"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/app= le/t8010.dtsi index e3d6a8354103..ac1dda92f890 100644 --- a/arch/arm64/boot/dts/apple/t8010.dtsi +++ b/arch/arm64/boot/dts/apple/t8010.dtsi @@ -61,19 +61,30 @@ serial0: serial@20a0c0000 { /* Use the bootloader-enabled clocks for now. */ clocks =3D <&clkref>, <&clkref>; clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart0>; status =3D "disabled"; }; =20 + pmgr: power-management@20e000000 { + compatible =3D "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0xe000000 0 0x8c000>; + }; + aic: interrupt-controller@20e100000 { compatible =3D "apple,t8010-aic", "apple,aic"; reg =3D <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells =3D <3>; interrupt-controller; + power-domains =3D <&ps_aic>; }; =20 pinctrl_ap: pinctrl@20f100000 { compatible =3D "apple,t8010-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x0f100000 0x0 0x100000>; + power-domains =3D <&ps_gpio>; =20 gpio-controller; #gpio-cells =3D <2>; @@ -95,6 +106,7 @@ pinctrl_ap: pinctrl@20f100000 { pinctrl_aop: pinctrl@2100f0000 { compatible =3D "apple,t8010-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x100f0000 0x0 0x100000>; + power-domains =3D <&ps_aop_gpio>; =20 gpio-controller; #gpio-cells =3D <2>; @@ -113,6 +125,14 @@ pinctrl_aop: pinctrl@2100f0000 { ; }; =20 + pmgr_mini: power-management@210200000 { + compatible =3D "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0x10200000 0 0x84000>; + }; + wdt: watchdog@2102b0000 { compatible =3D "apple,t8010-wdt", "apple,wdt"; reg =3D <0x2 0x102b0000 0x0 0x4000>; @@ -131,3 +151,5 @@ timer { ; }; }; + +#include "t8010-pmgr.dtsi" --=20 2.47.1 From nobody Wed Dec 4 19:08:45 2024 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B903199FD3; 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Mon, 02 Dec 2024 21:07:42 -0800 (PST) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-21586d40afasm33242385ad.270.2024.12.02.21.07.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 21:07:42 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nick Chan , Neal Gompa Subject: [PATCH v5 09/10] arm64: dts: apple: t8011: Add PMGR nodes Date: Tue, 3 Dec 2024 13:05:39 +0800 Message-ID: <20241203050640.109378-10-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241203050640.109378-1-towinchenmi@gmail.com> References: <20241203050640.109378-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the two PMGR nodes and all known power state subnodes. Since there are a large number of them, put them in a separate file to include. Acked-by: Hector Martin Acked-by: Neal Gompa Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8011-common.dtsi | 1 + arch/arm64/boot/dts/apple/t8011-pmgr.dtsi | 806 ++++++++++++++++++++ arch/arm64/boot/dts/apple/t8011-pro2.dtsi | 8 + arch/arm64/boot/dts/apple/t8011.dtsi | 22 + 4 files changed, 837 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t8011-pmgr.dtsi diff --git a/arch/arm64/boot/dts/apple/t8011-common.dtsi b/arch/arm64/boot/= dts/apple/t8011-common.dtsi index 44a0d0ea2ee3..2010b56246f1 100644 --- a/arch/arm64/boot/dts/apple/t8011-common.dtsi +++ b/arch/arm64/boot/dts/apple/t8011-common.dtsi @@ -22,6 +22,7 @@ chosen { framebuffer0: framebuffer@0 { compatible =3D "apple,simple-framebuffer", "simple-framebuffer"; reg =3D <0 0 0 0>; /* To be filled by loader */ + power-domains =3D <&ps_disp0_fe &ps_disp0_be &ps_dp>; /* Format properties will be added by loader */ status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/apple/t8011-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/t8011-pmgr.dtsi new file mode 100644 index 000000000000..c44e3f9d7087 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8011-pmgr.dtsi @@ -0,0 +1,806 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8011 "A10X" SoC + * + * Copyright (c) 2024 Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpu2: power-controller@80010 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu2"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80040 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80158 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80158 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_busif"; + }; + + ps_sio_p: power-controller@80160 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80160 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_p"; + power-domains =3D <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gpio"; + }; + + ps_pms: power-controller@80120 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms"; + apple,always-on; /* Core device */ + }; + + ps_pcie_ref: power-controller@80148 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80148 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_ref"; + }; + + ps_mca0: power-controller@80170 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80170 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca1: power-controller@80178 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80178 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca2: power-controller@80180 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80180 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca3: power-controller@80188 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80188 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca4: power-controller@80190 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80190 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_pwm0: power-controller@80198 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pwm0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c0: power-controller@801a0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801a8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801b0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801b8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi0: power-controller@801c0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi1: power-controller@801c8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi2: power-controller@801d0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi3: power-controller@801d8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart0: power-controller@801e0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart1: power-controller@801e8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart2: power-controller@801f0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart3: power-controller@801f8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_sio: power-controller@80168 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80168 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio"; + power-domains =3D <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@80128 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsic0_phy"; + power-domains =3D <&ps_usb3host>; + }; + + ps_isp_sens0: power-controller@80130 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80138 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80138 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens1"; + }; + + ps_isp_sens2: power-controller@80140 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80140 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens2"; + }; + + ps_usb: power-controller@80288 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80288 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb"; + }; + + ps_usbctrl: power-controller@80290 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80290 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbctrl"; + power-domains =3D <&ps_usb>; + }; + + ps_usb2host: power-controller@80298 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80298 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb2dev: power-controller@802a0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2dev"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb3host: power-controller@802a8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb3host"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb3dev: power-controller@802b0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb3dev"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_media: power-controller@802e8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "media"; + }; + + ps_isp_sys: power-controller@802e0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sys"; + }; + + ps_msr: power-controller@802f8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "msr"; + power-domains =3D <&ps_media>; + }; + + ps_jpg: power-controller@802f0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "jpg"; + power-domains =3D <&ps_media>; + }; + + ps_disp0_fe: power-controller@802c8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_fe"; + }; + + ps_disp0_be: power-controller@802d0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_be"; + power-domains =3D <&ps_disp0_fe>; + }; + + ps_dpa: power-controller@80230 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80230 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dpa"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart4: power-controller@80200 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80200 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart5: power-controller@80208 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80208 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart5"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart6: power-controller@80210 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80210 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart6"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart7: power-controller@80218 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80218 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart7"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart8: power-controller@80220 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80220 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart8"; + power-domains =3D <&ps_sio_p>; + }; + + ps_hfd0: power-controller@80238 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80238 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hfd0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mcc: power-controller@80240 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80240 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80248 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80248 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80250 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80250 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80258 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80258 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80260 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs4: power-controller@80268 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80268 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs4"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs5: power-controller@80270 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80270 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs5"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs6: power-controller@80278 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80278 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs6"; + }; + + ps_dcs7: power-controller@80280 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80280 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs7"; + }; + + ps_smx: power-controller@802b8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802c0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_dp: power-controller@802d8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dp"; + power-domains =3D <&ps_disp0_be>; + }; + + ps_venc_sys: power-controller@80320 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80320 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_sys"; + power-domains =3D <&ps_media>; + }; + + ps_srs: power-controller@80390 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80390 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "srs"; + power-domains =3D <&ps_media>; + }; + + ps_pms_sram: power-controller@80308 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80308 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms_sram"; + }; + + ps_pmp: power-controller@80300 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80300 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pmp"; + }; + + ps_pcie: power-controller@80328 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80328 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie"; + }; + + ps_pcie_aux: power-controller@80330 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80330 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_aux"; + }; + + ps_vdec0: power-controller@80310 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80310 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "vdec0"; + power-domains =3D <&ps_media>; + }; + + ps_gfx: power-controller@80338 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80338 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gfx"; + }; + + ps_sep: power-controller@80400 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80400 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sep"; + apple,always-on; /* Locked on */ + }; + + ps_isp_rsts0: power-controller@84000 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_rsts0"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_rsts1: power-controller@84008 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_rsts1"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_vis: power-controller@84010 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_vis"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_be: power-controller@84018 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_be"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_pearl: power-controller@84020 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84020 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_pearl"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_dprx: power-controller@84028 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84028 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dprx"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_venc_pipe4: power-controller@88000 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe4"; + power-domains =3D <&ps_venc_sys>; + }; + + ps_venc_pipe5: power-controller@88008 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe5"; + power-domains =3D <&ps_venc_sys>; + }; + + ps_venc_me0: power-controller@88010 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me0"; + }; + + ps_venc_me1: power-controller@88018 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop: power-controller@80000 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop"; + power-domains =3D <&ps_aop_cpu &ps_aop_filter &ps_aop_busif>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80008 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "debug"; + }; + + ps_aop_gpio: power-controller@80010 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_gpio"; + }; + + ps_aop_cpu: power-controller@80048 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80048 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_cpu"; + }; + + ps_aop_filter: power-controller@80050 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80050 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_filter"; + }; + + ps_aop_busif: power-controller@80058 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80058 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_busif"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8011-pro2.dtsi b/arch/arm64/boot/dt= s/apple/t8011-pro2.dtsi index f4e707415003..5eaa0a73350f 100644 --- a/arch/arm64/boot/dts/apple/t8011-pro2.dtsi +++ b/arch/arm64/boot/dts/apple/t8011-pro2.dtsi @@ -40,3 +40,11 @@ button-volup { }; }; }; + +&ps_dcs6 { + apple,always-on; /* LPDDR4 interface */ +}; + +&ps_dcs7 { + apple,always-on; /* LPDDR4 interface */ +}; diff --git a/arch/arm64/boot/dts/apple/t8011.dtsi b/arch/arm64/boot/dts/app= le/t8011.dtsi index 6c4ed9dc4a50..b845fa6f6d64 100644 --- a/arch/arm64/boot/dts/apple/t8011.dtsi +++ b/arch/arm64/boot/dts/apple/t8011.dtsi @@ -69,19 +69,30 @@ serial0: serial@20a0c0000 { /* Use the bootloader-enabled clocks for now. */ clocks =3D <&clkref>, <&clkref>; clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart0>; status =3D "disabled"; }; =20 + pmgr: power-management@20e000000 { + compatible =3D "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0xe000000 0 0x8c000>; + }; + aic: interrupt-controller@20e100000 { compatible =3D "apple,t8010-aic", "apple,aic"; reg =3D <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells =3D <3>; interrupt-controller; + power-domains =3D <&ps_aic>; }; =20 pinctrl_ap: pinctrl@20f100000 { compatible =3D "apple,t8010-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x0f100000 0x0 0x100000>; + power-domains =3D <&ps_gpio>; =20 gpio-controller; #gpio-cells =3D <2>; @@ -103,6 +114,7 @@ pinctrl_ap: pinctrl@20f100000 { pinctrl_aop: pinctrl@2100f0000 { compatible =3D "apple,t8010-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x100f0000 0x0 0x100000>; + power-domains =3D <&ps_aop_gpio>; =20 gpio-controller; #gpio-cells =3D <2>; @@ -121,6 +133,14 @@ pinctrl_aop: pinctrl@2100f0000 { ; }; =20 + pmgr_mini: power-management@210200000 { + compatible =3D "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0x10200000 0 0x84000>; + }; + wdt: watchdog@2102b0000 { compatible =3D "apple,t8010-wdt", "apple,wdt"; reg =3D <0x2 0x102b0000 0x0 0x4000>; @@ -139,3 +159,5 @@ timer { ; }; }; + +#include "t8011-pmgr.dtsi" --=20 2.47.1 From nobody Wed Dec 4 19:08:45 2024 Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 570A21ABECA; Tue, 3 Dec 2024 05:07:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733202469; cv=none; b=Qz1FU0sO7YHVvIdNhvX03szxWmB3nQRbRZJrJQREtJvEiA8p1hkc27MWcpax27Xog0kcSOJrsqjYjm2NkRrW7Hz1Km4A1TMoIVTcPj05Lp87quokvRW1iFyY2SEBTtet9/L8B0q+TZWYHvrFNCb2GEx/TUsFcSLmnB8X+J6JO7M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733202469; c=relaxed/simple; bh=6FROvB0fBRejLQfYq9wwHODMFa+f9AKibQTs62foorQ=; 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Mon, 02 Dec 2024 21:07:45 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nick Chan , Neal Gompa Subject: [PATCH v5 10/10] arm64: dts: apple: t8015: Add PMGR nodes Date: Tue, 3 Dec 2024 13:05:40 +0800 Message-ID: <20241203050640.109378-11-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241203050640.109378-1-towinchenmi@gmail.com> References: <20241203050640.109378-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the two PMGR nodes and all known power state subnodes. Since there are a large number of them, put them in a separate file to include. Acked-by: Hector Martin Acked-by: Neal Gompa Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8015-common.dtsi | 1 + arch/arm64/boot/dts/apple/t8015-pmgr.dtsi | 931 ++++++++++++++++++++ arch/arm64/boot/dts/apple/t8015.dtsi | 21 + 3 files changed, 953 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t8015-pmgr.dtsi diff --git a/arch/arm64/boot/dts/apple/t8015-common.dtsi b/arch/arm64/boot/= dts/apple/t8015-common.dtsi index 69258a33ea50..498f58fb9715 100644 --- a/arch/arm64/boot/dts/apple/t8015-common.dtsi +++ b/arch/arm64/boot/dts/apple/t8015-common.dtsi @@ -24,6 +24,7 @@ chosen { framebuffer0: framebuffer@0 { compatible =3D "apple,simple-framebuffer", "simple-framebuffer"; reg =3D <0 0 0 0>; /* To be filled by loader */ + power-domains =3D <&ps_disp0_be &ps_mipi_dsi &ps_disp0_hilo &ps_disp0_p= pp>; /* Format properties will be added by loader */ status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/t8015-pmgr.dtsi new file mode 100644 index 000000000000..e238c2d2732f --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi @@ -0,0 +1,931 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8015 "A11" SoC + * + * Copyright (c) 2024, Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpu2: power-controller@80010 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu2"; + apple,always-on; /* Core device */ + }; + + ps_cpu3: power-controller@80018 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu3"; + apple,always-on; /* Core device */ + }; + + ps_cpu4: power-controller@80020 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80020 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu4"; + apple,always-on; /* Core device */ + }; + + ps_cpu5: power-controller@80028 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80028 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu5"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80040 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80158 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80158 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_busif"; + }; + + ps_sio_p: power-controller@80160 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80160 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_p"; + power-domains =3D <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gpio"; + }; + + ps_pms: power-controller@80120 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms"; + apple,always-on; /* Core device */ + }; + + ps_pcie_ref: power-controller@80148 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80148 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_ref"; + }; + + ps_mca0: power-controller@80170 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80170 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca1: power-controller@80178 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80178 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca2: power-controller@80180 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80180 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca3: power-controller@80188 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80188 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca4: power-controller@80190 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80190 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_pwm0: power-controller@801a0 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pwm0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c0: power-controller@801a8 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801b0 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801b8 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801c0 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi0: power-controller@801c8 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi1: power-controller@801d0 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi2: power-controller@801d8 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi3: power-controller@801e0 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart0: power-controller@801e8 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart1: power-controller@801f0 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart2: power-controller@801f8 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_sio: power-controller@80168 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80168 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio"; + power-domains =3D <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsicphy: power-controller@80128 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsicphy"; + power-domains =3D <&ps_usb2host1>; + }; + + ps_ispsens0: power-controller@80130 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ispsens0"; + }; + + ps_ispsens1: power-controller@80138 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80138 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ispsens1"; + }; + + ps_ispsens2: power-controller@80140 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80140 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ispsens2"; + }; + + ps_mca5: power-controller@80198 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca5"; + power-domains =3D <&ps_sio_p>; + }; + + ps_usb: power-controller@80270 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80270 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb"; + }; + + ps_usbctlreg: power-controller@80278 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80278 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbctlreg"; + power-domains =3D <&ps_usb>; + }; + + ps_usb2host0: power-controller@80280 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80280 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0"; + power-domains =3D <&ps_usbctlreg>; + }; + + ps_usb2host1: power-controller@80290 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80290 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host1"; + power-domains =3D <&ps_usbctlreg>; + }; + + ps_rtmux: power-controller@802b0 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "rtmux"; + }; + + ps_media: power-controller@802f0 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "media"; + }; + + ps_jpg: power-controller@802f8 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "jpg"; + power-domains =3D <&ps_media>; + }; + + ps_disp0_fe: power-controller@802b8 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_fe"; + power-domains =3D <&ps_rtmux>; + }; + + ps_disp0_be: power-controller@802c0 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_be"; + power-domains =3D <&ps_disp0_fe>; + }; + + ps_disp0_gp: power-controller@802c8 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_gp"; + power-domains =3D <&ps_disp0_be>; + status =3D "disabled"; + }; + + ps_uart3: power-controller@80200 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80200 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart4: power-controller@80208 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80208 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart5: power-controller@80210 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80210 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart5"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart6: power-controller@80218 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80218 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart6"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart7: power-controller@80220 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80220 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart7"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart8: power-controller@80228 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80228 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart8"; + power-domains =3D <&ps_sio_p>; + }; + + ps_hfd0: power-controller@80238 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80238 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hfd0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mcc: power-controller@80248 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80248 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80250 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80250 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs0"; + apple,always-on; /* LPDDR4X interface */ + }; + + ps_dcs1: power-controller@80258 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80258 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs1"; + apple,always-on; /* LPDDR4X interface */ + }; + + ps_dcs2: power-controller@80260 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs2"; + apple,always-on; /* LPDDR4X interface */ + }; + + ps_dcs3: power-controller@80268 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80268 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs3"; + apple,always-on; /* LPDDR4X interface */ + }; + + ps_usb2host0_ohci: power-controller@80288 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80288 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0_ohci"; + power-domains =3D <&ps_usb2host0>; + }; + + ps_usb2dev: power-controller@80298 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80298 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2dev"; + power-domains =3D <&ps_usbctlreg>; + }; + + ps_smx: power-controller@802a0 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802a8 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mipi_dsi: power-controller@802d8 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mipi_dsi"; + power-domains =3D <&ps_rtmux>; + }; + + ps_dp: power-controller@802e0 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dp"; + power-domains =3D <&ps_disp0_be>; + }; + + ps_dpa: power-controller@80230 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80230 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dpa"; + }; + + ps_disp0_be_2x: power-controller@802d0 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_be_2x"; + power-domains =3D <&ps_disp0_be>; + }; + + ps_isp_sys: power-controller@80350 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80350 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sys"; + power-domains =3D <&ps_rtmux>; + }; + + ps_msr: power-controller@80300 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80300 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "msr"; + power-domains =3D <&ps_media>; + }; + + ps_venc_sys: power-controller@80398 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80398 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_sys"; + power-domains =3D <&ps_media>; + }; + + ps_pmp: power-controller@80308 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80308 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pmp"; + }; + + ps_pms_sram: power-controller@80310 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80310 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms_sram"; + }; + + ps_pcie: power-controller@80318 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80318 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie"; + }; + + ps_pcie_aux: power-controller@80320 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80320 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_aux"; + }; + + ps_vdec0: power-controller@80388 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80388 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "vdec0"; + power-domains =3D <&ps_media>; + }; + + ps_gfx: power-controller@80338 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80338 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gfx"; + }; + + ps_ans2: power-controller@80328 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80328 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ans2"; + apple,always-on; + }; + + ps_pcie_direct: power-controller@80330 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80330 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_direct"; + apple,always-on; + }; + + ps_avd_sys: power-controller@803a8 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x803a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "avd_sys"; + power-domains =3D <&ps_media>; + }; + + ps_sep: power-controller@80400 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80400 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sep"; + apple,always-on; /* Locked on */ + }; + + ps_disp0_gp0: power-controller@80830 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80830 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_gp0"; + power-domains =3D <&ps_disp0_gp>; + status =3D "disabled"; + }; + + ps_disp0_gp1: power-controller@80838 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80838 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_gp1"; + status =3D "disabled"; + }; + + ps_disp0_ppp: power-controller@80840 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80840 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_ppp"; + }; + + ps_disp0_hilo: power-controller@80848 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80848 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_hilo"; + }; + + ps_isp_rsts0: power-controller@84000 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_rsts0"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_rsts1: power-controller@84008 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_rsts1"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_vis: power-controller@84010 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_vis"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_be: power-controller@84018 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_be"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_pearl: power-controller@84020 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84020 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_pearl"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_dprx: power-controller@84028 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84028 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dprx"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_cnv: power-controller@84030 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84030 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_cnv"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_venc_dma: power-controller@88000 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_dma"; + }; + + ps_venc_pipe4: power-controller@88010 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe4"; + }; + + ps_venc_pipe5: power-controller@88018 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe5"; + }; + + ps_venc_me0: power-controller@88020 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88020 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me0"; + }; + + ps_venc_me1: power-controller@88028 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88028 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop_base: power-controller@80008 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_base"; + power-domains =3D <&ps_aop_cpu &ps_aop_filter>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80050 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80050 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "debug"; + }; + + ps_aop_cpu: power-controller@80020 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80020 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_cpu"; + }; + + ps_aop_filter: power-controller@80000 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_filter"; + }; + + ps_spmi: power-controller@80058 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80058 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spmi"; + apple,always-on; /* System Power Management Interface */ + }; + + ps_smc_i2cm1: power-controller@800a8 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x800a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smc_i2cm1"; + }; + + ps_smc_fabric: power-controller@80030 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80030 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smc_fabric"; + }; + + ps_smc_cpu: power-controller@80140 { + compatible =3D "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80140 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smc_cpu"; + power-domains =3D <&ps_smc_fabric &ps_smc_i2cm1>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/app= le/t8015.dtsi index 8828d830e5be..fbff3a6c0ba4 100644 --- a/arch/arm64/boot/dts/apple/t8015.dtsi +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -119,6 +119,7 @@ serial0: serial@22e600000 { /* Use the bootloader-enabled clocks for now. */ clocks =3D <&clkref>, <&clkref>; clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart0>; status =3D "disabled"; }; =20 @@ -127,11 +128,21 @@ aic: interrupt-controller@232100000 { reg =3D <0x2 0x32100000 0x0 0x8000>; #interrupt-cells =3D <3>; interrupt-controller; + power-domains =3D <&ps_aic>; + }; + + pmgr: power-management@232000000 { + compatible =3D "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0x32000000 0 0x8c000>; }; =20 pinctrl_ap: pinctrl@233100000 { compatible =3D "apple,t8015-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x33100000 0x0 0x1000>; + power-domains =3D <&ps_gpio>; =20 gpio-controller; #gpio-cells =3D <2>; @@ -188,6 +199,14 @@ pinctrl_nub: pinctrl@2351f0000 { ; }; =20 + pmgr_mini: power-management@235200000 { + compatible =3D "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0x35200000 0 0x84000>; + }; + wdt: watchdog@2352b0000 { compatible =3D "apple,t8015-wdt", "apple,wdt"; reg =3D <0x2 0x352b0000 0x0 0x4000>; @@ -232,3 +251,5 @@ timer { ; }; }; + +#include "t8015-pmgr.dtsi" --=20 2.47.1