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Also, that means concatenation can be used when not mandated, contradicting the comment on the code. However, these cases can only happen if the SMMUv3 driver is changed to use ias !=3D oas for stage-2. This patch re-writes the code to use concatenation only if mandatory, fixing the missing case for level-1 and granule 16K with PA =3D 40 bits. Signed-off-by: Mostafa Saleh --- drivers/iommu/io-pgtable-arm.c | 45 +++++++++++++++++++++++++--------- 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index 6b9bb58a414f..0055876b3527 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -223,6 +223,33 @@ static inline int arm_lpae_max_entries(int i, struct a= rm_lpae_io_pgtable *data) return ptes_per_table - (i & (ptes_per_table - 1)); } =20 +/* + * Check if concatenated PGDs are mandatory according to Arm DDI0487 (K.a) + * 1) R_DXBSH: For 16KB, and 48-bit input size, use level 1 instead of 0. + * 2) R_SRKBC: After de-ciphering the table for PA size and valid initial = lookup + * a) 40 bits PA size with 4K: use level 1 instead of level 0 (2 tables = for ias =3D oas) + * b) 40 bits PA size with 16K: use level 2 instead of level 1 (16 table= s for ias =3D oas) + * c) 42 bits PA size with 4K: use level 1 instead of level 0 (8 tables = for ias =3D oas) + * d) 48 bits PA size with 16K: use level 1 instead of level 0 (2 tables= for ias =3D oas) + */ +static inline bool arm_lpae_concat_mandatory(struct arm_lpae_io_pgtable *d= ata) +{ + unsigned int ias =3D data->iop.cfg.ias; + unsigned int oas =3D data->iop.cfg.oas; + + /* Covers 1 and 2.d */ + if ((ARM_LPAE_GRANULE(data) =3D=3D SZ_16K) && (data->start_level =3D=3D 0= )) + return (oas =3D=3D 48) || (ias =3D 48); + + /* Covers 2.a and 2.c */ + if ((ARM_LPAE_GRANULE(data) =3D=3D SZ_4K) && (data->start_level =3D=3D 0)) + return (oas =3D=3D 40) || (oas =3D=3D 42); + + /* Case 2.b */ + return (ARM_LPAE_GRANULE(data) =3D=3D SZ_16K) && + (data->start_level =3D=3D 1) && (oas =3D=3D 40); +} + static bool selftest_running =3D false; =20 static dma_addr_t __arm_lpae_dma_addr(void *pages) @@ -1006,18 +1033,12 @@ arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg = *cfg, void *cookie) if (!data) return NULL; =20 - /* - * Concatenate PGDs at level 1 if possible in order to reduce - * the depth of the stage-2 walk. - */ - if (data->start_level =3D=3D 0) { - unsigned long pgd_pages; - - pgd_pages =3D ARM_LPAE_PGD_SIZE(data) / sizeof(arm_lpae_iopte); - if (pgd_pages <=3D ARM_LPAE_S2_MAX_CONCAT_PAGES) { - data->pgd_bits +=3D data->bits_per_level; - data->start_level++; - } + if (arm_lpae_concat_mandatory(data)) { + if (WARN_ON((ARM_LPAE_PGD_SIZE(data) / sizeof(arm_lpae_iopte)) > + ARM_LPAE_S2_MAX_CONCAT_PAGES)) + return NULL; + data->pgd_bits +=3D data->bits_per_level; + data->start_level++; } =20 /* VTCR */ --=20 2.47.0.338.g60cca15819-goog From nobody Sun Feb 8 04:11:14 2026 Received: from mail-wm1-f73.google.com (mail-wm1-f73.google.com [209.85.128.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A7492040A8 for ; Mon, 2 Dec 2024 14:06:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733148391; cv=none; b=kfjyHGplkSlApcDHV3Q7biYZaVW4w5WUZFyUPQm86JEd4GOB4hw1fGbAK4pWoc20MqOrJu8uH80FetS2BnNfguLMw2PTteP2xK7hoOlAXJyLke0yyUuYQklWFVVPmuSOgELbiNw+GGu/iPVZRrqHAVDU2ZQ4SMy1XodMQTND0Us= ARC-Message-Signature: i=1; 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Mon, 02 Dec 2024 06:06:28 -0800 (PST) Date: Mon, 2 Dec 2024 14:06:04 +0000 In-Reply-To: <20241202140604.422235-1-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241202140604.422235-1-smostafa@google.com> X-Mailer: git-send-email 2.47.0.338.g60cca15819-goog Message-ID: <20241202140604.422235-3-smostafa@google.com> Subject: [PATCH v2 2/2] iommu/io-pgtable-arm: Add coverage for different OAS in selftest From: Mostafa Saleh To: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, Mostafa Saleh Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Run selftests with different OAS values intead of hardcoding it to 48 bits. We always keep OAS >=3D IAS to make the config valid for stage-2. This can be further improved, if we split IAS/OAS configuration for stage-1 and stage-2 (to use input sizes compatible with VA_BITS as SMMUv3 does, or IAS > OAS which is valid for stage-1). However, that adds more complexity, and the current change improves coverage and makes it possible to test all concatenation cases. Signed-off-by: Mostafa Saleh --- drivers/iommu/io-pgtable-arm.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index 0055876b3527..62015fdd6c6a 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -1385,15 +1385,14 @@ static int __init arm_lpae_do_selftests(void) SZ_64K | SZ_512M, }; =20 - static const unsigned int ias[] __initconst =3D { + static const unsigned int address_size[] __initconst =3D { 32, 36, 40, 42, 44, 48, }; =20 - int i, j, pass =3D 0, fail =3D 0; + int i, j, k, pass =3D 0, fail =3D 0; struct device dev; struct io_pgtable_cfg cfg =3D { .tlb =3D &dummy_tlb_ops, - .oas =3D 48, .coherent_walk =3D true, .iommu_dev =3D &dev, }; @@ -1402,15 +1401,19 @@ static int __init arm_lpae_do_selftests(void) set_dev_node(&dev, NUMA_NO_NODE); =20 for (i =3D 0; i < ARRAY_SIZE(pgsize); ++i) { - for (j =3D 0; j < ARRAY_SIZE(ias); ++j) { - cfg.pgsize_bitmap =3D pgsize[i]; - cfg.ias =3D ias[j]; - pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u\n", - pgsize[i], ias[j]); - if (arm_lpae_run_tests(&cfg)) - fail++; - else - pass++; + for (j =3D 0; j < ARRAY_SIZE(address_size); ++j) { + /* Don't use ias > oas as it is not valid for stage-2. */ + for (k =3D 0; k <=3D j; ++k) { + cfg.pgsize_bitmap =3D pgsize[i]; + cfg.ias =3D address_size[k]; + cfg.oas =3D address_size[j]; + pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u OAS %u\n", + pgsize[i], cfg.ias, cfg.oas); + if (arm_lpae_run_tests(&cfg)) + fail++; + else + pass++; + } } } =20 --=20 2.47.0.338.g60cca15819-goog