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Mon, 02 Dec 2024 20:42:36 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B2KgZ1M019541 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 2 Dec 2024 20:42:35 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 12:42:34 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 12:41:58 -0800 Subject: [PATCH 1/3] drm/msm/dp: account for widebus in msm_dp_catalog_panel_tpg_enable() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241202-tpg-v1-1-0fd6b518b914@quicinc.com> References: <20241202-tpg-v1-0-0fd6b518b914@quicinc.com> In-Reply-To: <20241202-tpg-v1-0-0fd6b518b914@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Stephen Boyd , Kuogee Hsieh CC: , , , , "Jessica Zhang" , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Fixes: 757a2f36ab09 ("drm/msm/dp: enable widebus feature for display port") Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/dp/dp_catalog.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index b4c8856fb25d..05c8e1996f60 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -1011,9 +1011,21 @@ void msm_dp_catalog_panel_tpg_enable(struct msm_dp_c= atalog *msm_dp_catalog, u32 v_sync_width; u32 hsync_ctl; u32 display_hctl; + u32 h_sync_width; + u32 h_front_porch; + u32 h_back_porch; + u32 h_active; + + h_active =3D drm_mode->hdisplay; + h_back_porch =3D drm_mode->htotal - drm_mode->hsync_end; + h_sync_width =3D drm_mode->htotal - (drm_mode->hsync_start + h_back_porch= ); + h_front_porch =3D drm_mode->hsync_start - drm_mode->hdisplay; + + if (msm_dp_catalog->wide_bus_en) + h_active /=3D 2; =20 /* TPG config parameters*/ - hsync_period =3D drm_mode->htotal; + hsync_period =3D h_sync_width + h_back_porch + h_active + h_front_porch; vsync_period =3D drm_mode->vtotal; =20 display_v_start =3D ((drm_mode->vtotal - drm_mode->vsync_start) * --=20 2.34.1