From nobody Wed Dec 4 18:51:13 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 108D21DEFC1; Mon, 2 Dec 2024 20:42:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733172165; cv=none; b=PE4sRi+F8+L0T2t3hGl/FhgZ9k0d1CqjX4wpsr8HrkxTfkCoxRwYXymR9aSqZPYuELx1CKDa+J9ebcXvWKGdxY1AYjhNv1co0UEzJaAjzCeU/QlB6UCgDEa7wRHrsFo3xtYQs6nX/8cwNoV9J2w9i7Q7xPiQKp5fIwJ2HxnIF5I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733172165; c=relaxed/simple; bh=jn+N9zwIOsPHht+9CIjwP5bJju34BSnF8zN3S7G1imQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=kSivocxOjY+bjst/7vm7m82UVF14n3qK977D4d+qXPV/lSlI1QE744KWyrvfCBaKqHnBSKLgPQ6RMGzI0ajMSiPBBecwVhqHgso1alYnUcp3R+hB/YiwFb68Kk1Eef+looiVuZXIPF5EkRBiNiUiiORd5N2ZaEhJ6e+EnYnyhQc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=a9AA9Nqz; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="a9AA9Nqz" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B2IU6fV030649; Mon, 2 Dec 2024 20:42:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= GlLdvDlRzxdx5tP7v68vMBpASgo7Y0IjadtFWKOVMbM=; b=a9AA9NqzxjvZK59X y2/sFVlMka69A0u3rQZGQxVQ07eMCM8KZWo9RCJjF21vajyq5r6NJoYix2hTaoRc CgBPNpOxaiR2QBWMFc4LfaVCIJi8TxIV4oP3jMfBl7Dr09EUSDNap9Bi5u6djTn3 lj4n+ec8wCIzfhXMAoIoXX0s0zwkutHsnkX3V1JF6fgIxJx9XhY3nvsJWoKnLTQP As9S1OhNC27toy7SVTECzKsxXUJy2ZWjLX1MQS2+S7CwvDaTcJ+hB/B2zUN1yEce fj28MpzFe/hW4m6LK8nZ8ZrzJkNCBS7VFucdPvTXYXyAqdgBN4w1VaJtWKdMNcS1 fyHKpQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 437t1ge15w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 02 Dec 2024 20:42:36 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B2KgZ1M019541 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 2 Dec 2024 20:42:35 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 12:42:34 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 12:41:58 -0800 Subject: [PATCH 1/3] drm/msm/dp: account for widebus in msm_dp_catalog_panel_tpg_enable() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241202-tpg-v1-1-0fd6b518b914@quicinc.com> References: <20241202-tpg-v1-0-0fd6b518b914@quicinc.com> In-Reply-To: <20241202-tpg-v1-0-0fd6b518b914@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Stephen Boyd , Kuogee Hsieh CC: , , , , "Jessica Zhang" , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733172154; l=1329; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; bh=jn+N9zwIOsPHht+9CIjwP5bJju34BSnF8zN3S7G1imQ=; b=3cKObY/EEQ7Wt+Pxq+KLoA5TrTbhA/vocKACaaY10Z1XzeLCocFPlgRvxKndNgK4RpW0LxIqk HfAalffFinmCBGiAiBvIfVM5huvk89Q7QJK4rF4Wu1Ed7wmB1IUSaEo X-Developer-Key: i=quic_abhinavk@quicinc.com; a=ed25519; pk=SD3D8dOKDDh6BoX3jEYjsHrTFwuIK8+o0cLPgQok9ys= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: N63Ymxed8R_ETFDIoL6dXhi0Z5GWXAXt X-Proofpoint-ORIG-GUID: N63Ymxed8R_ETFDIoL6dXhi0Z5GWXAXt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 malwarescore=0 spamscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412020174 Adjust the h_active calculation to account for widebus in tpg. Fixes: 757a2f36ab09 ("drm/msm/dp: enable widebus feature for display port") Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/dp/dp_catalog.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index b4c8856fb25d..05c8e1996f60 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -1011,9 +1011,21 @@ void msm_dp_catalog_panel_tpg_enable(struct msm_dp_c= atalog *msm_dp_catalog, u32 v_sync_width; u32 hsync_ctl; u32 display_hctl; + u32 h_sync_width; + u32 h_front_porch; + u32 h_back_porch; + u32 h_active; + + h_active =3D drm_mode->hdisplay; + h_back_porch =3D drm_mode->htotal - drm_mode->hsync_end; + h_sync_width =3D drm_mode->htotal - (drm_mode->hsync_start + h_back_porch= ); + h_front_porch =3D drm_mode->hsync_start - drm_mode->hdisplay; + + if (msm_dp_catalog->wide_bus_en) + h_active /=3D 2; =20 /* TPG config parameters*/ - hsync_period =3D drm_mode->htotal; + hsync_period =3D h_sync_width + h_back_porch + h_active + h_front_porch; vsync_period =3D drm_mode->vtotal; =20 display_v_start =3D ((drm_mode->vtotal - drm_mode->vsync_start) * --=20 2.34.1 From nobody Wed Dec 4 18:51:13 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A59A1DEFC5; Mon, 2 Dec 2024 20:42:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733172166; cv=none; b=rmPQJJCKzkF2uETQ5OsVJUDlATtI1xsN9RCkvoCrE+HrhwgVDjYvAeVbWIOYXdmjmJleIUl6cxPq1eg4ehAmVQeZ+X7EKd5LYu7uQCKU8Pkh3DRuEHTZoi7UwdIzQ+LnZBmktvNp1HvEf8xZQBYUzo/VipNFm5TpsebWDKosabo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733172166; c=relaxed/simple; bh=dIijZwoRaA6rxyvoqR4huEu7nEMw44IUyghyh0WYPc8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=XfudkMFzPN4K+NdlJLkyl4TbD9jRP+qWQdj8N1mZJ2phX29adJLUPwXu0XoLPKhV1XqBjPwvvBhX2eOYkvA3nMWpE8MSe96hqFWHxc2vQ7YLKtQ+7BD5BXTF5+eZvqAGThREKIr5eD5Q1U/k9NU8HFQCv12oIpB+ylHuUACbcYk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=XEuFWHkS; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="XEuFWHkS" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B29XNBl026469; Mon, 2 Dec 2024 20:42:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 6BGp4ismpDEOyFPSZ2otVrrI661Oz81+8eHZ9x8VmKU=; b=XEuFWHkSWZXVTfCZ nSAkCYK+NgIwhzP87sLRyuhisuEHNDO2YWp9i70stx2J/lyp0lZ8jHpJUtpz7jK6 56Tsm+Kr2KdYRYvbXybY6m5Idr+KixnGMDsEP/bumBBErjsDnEd8DCZRMqb35TWH vviP9NyCPhkv51fSeLvhr2e8V+c3tkgUutd3god7n1lPyXRXBDEeI83W7NNmx1q8 NbOFyzo672ZMNf0bOmEcYKerWdLtSmXsFjFXJVTw4FN9ibp95iwo8vMB2wy7PtrZ FGglAmcn//qfvGZz8GfjDTMGltwAgWXfaZJdSj/aOUn3VETV239Y5dcvppHTPvCK EvNvnQ== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 437ufe5u6q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 02 Dec 2024 20:42:36 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B2KgZhk028654 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 2 Dec 2024 20:42:35 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 12:42:35 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 12:41:59 -0800 Subject: [PATCH 2/3] drm/msm/dp: do not touch the MMSS_DP_INTF_CONFIG for tpg Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241202-tpg-v1-2-0fd6b518b914@quicinc.com> References: <20241202-tpg-v1-0-0fd6b518b914@quicinc.com> In-Reply-To: <20241202-tpg-v1-0-0fd6b518b914@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Stephen Boyd , Kuogee Hsieh CC: , , , , "Jessica Zhang" , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733172154; l=1252; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; bh=dIijZwoRaA6rxyvoqR4huEu7nEMw44IUyghyh0WYPc8=; b=4B7z7IF5pWVXkf23L/XprZeUT8sv4/9yuOhEZynQnUI085ig+bwm74lAgavAJnFmEgph/dlIx DYCsqg6D+cYClY+HIPBjOXcnTPdLsOe2tNjaBoqxZn8xRBlumWecxga X-Developer-Key: i=quic_abhinavk@quicinc.com; a=ed25519; pk=SD3D8dOKDDh6BoX3jEYjsHrTFwuIK8+o0cLPgQok9ys= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: rkYBwRkElpsSTBXFBLVK7fUpvzg3hGDH X-Proofpoint-GUID: rkYBwRkElpsSTBXFBLVK7fUpvzg3hGDH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=962 clxscore=1015 adultscore=0 bulkscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412020174 MMSS_DP_INTF_CONFIG has already been setup by the main datapath for DP to account for widebus to be used/unused etc. In current implementation, TPG only switches the DP controller to use the main datapath stream OR use the test pattern but expects the rest of the controller to be already setup. Keeping the same behavior intact, drop the clearing of MMSS_DP_INTF_CONFIG from the msm_dp_catalog_panel_tpg_enable() API. Fixes: 757a2f36ab09 ("drm/msm/dp: enable widebus feature for display port") Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 05c8e1996f60..36d3f3d248ca 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -1048,7 +1048,6 @@ void msm_dp_catalog_panel_tpg_enable(struct msm_dp_ca= talog *msm_dp_catalog, display_hctl =3D (hsync_end_x << 16) | hsync_start_x; =20 =20 - msm_dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, 0x0); msm_dp_write_p0(catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); --=20 2.34.1 From nobody Wed Dec 4 18:51:13 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CEA71DEFC6; Mon, 2 Dec 2024 20:42:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733172166; cv=none; b=oVqNODBAcXcfHCNwdcLW7NeSY3myO5bF7sKFY4XVUSTh58DiitAGrZXHuYIKEKdHdwz+tmNJA/nwhz7LgXOhDtfX+mZgN7TR48IdBLnF+vsfskC57eWw15P/tC82Xbc4D3eu5Sckt9Q9MVJBljzL7QbxuqFgUkt0U0lIAIOWvCY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733172166; c=relaxed/simple; bh=8xU8eZvxuxJZRudg+03NMMrCYKY67CgFbv6HcpsX0CA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=qvpxlDPjH87AtZgmdcH5QNFexJ2Jn6M2WYta0K8s10z9AUo7nkicvhU3OwhNhMA4Oxuvqm/HPulqupbmwx/7XKgHJAEKH/JcTKd7zMoM+5tzwubbZvAfscNgE6It2QQ4VPL2x263NIc5rXexDZXjb2H6DxbmoVmGwUJ14UEwSbs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=PnfW2M6/; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="PnfW2M6/" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B2K9dJc002804; Mon, 2 Dec 2024 20:42:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= wVmZna+XbYf+uUPJxg0T3pmfRS7RDVjCkPeIXRm81gA=; b=PnfW2M6/apYhs833 yUh2DmFG15kprWwlFB5+P0kSrwuk18PeSwmZkxBJEJe6gg3G5TpN7ebnyzBRuuaW 4Ih8ARynQNTkY6UYWEl1+ZJdUGq4kQs7L5aXGuHspLR7Wpuv9jdlnm9APOSSZolG sohyFB6wfWrixKtNYtcgv+kfdtP7J3YQoJXiauGO6YMejF0Gu8WJgJTXHhzWMxwp G3CtiE1RSIl2WVgiughfHGcuRdnofXGprMNqL5+ZiJYqGUqz0iUROGL2s/5YodLo BDoO28MtYV8DsNFwP8M+nlBCCAG1px1NTutZiCo+hPquhlXQVwZvOVILNFFUdB5H YpDNUw== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 437uvjwsdc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 02 Dec 2024 20:42:36 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B2Kga9i029657 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 2 Dec 2024 20:42:36 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 12:42:35 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 12:42:00 -0800 Subject: [PATCH 3/3] drm/msm/dp: add a debugfs node for using tpg Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241202-tpg-v1-3-0fd6b518b914@quicinc.com> References: <20241202-tpg-v1-0-0fd6b518b914@quicinc.com> In-Reply-To: <20241202-tpg-v1-0-0fd6b518b914@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Stephen Boyd , Kuogee Hsieh CC: , , , , "Jessica Zhang" , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733172154; l=3055; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; bh=8xU8eZvxuxJZRudg+03NMMrCYKY67CgFbv6HcpsX0CA=; b=4/ROjG1S7kkiQW2W6xJJvNSX5rNWFt7upb0DJunvrd04bgETUqKSs9h8eftzb6NsxXhwVpFx9 JP/udaRE1NpA/kZpT9tCAjzKExBq+T0TG1TAzgV6Bgd391F+hWIpJec X-Developer-Key: i=quic_abhinavk@quicinc.com; a=ed25519; pk=SD3D8dOKDDh6BoX3jEYjsHrTFwuIK8+o0cLPgQok9ys= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: PJnDwuu67LYDulM6sF_bp-nAaWxHrNEM X-Proofpoint-ORIG-GUID: PJnDwuu67LYDulM6sF_bp-nAaWxHrNEM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 impostorscore=0 adultscore=0 phishscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412020173 DP test pattern generator is a very useful tool to debug issues where monitor is showing incorrect output as it helps to isolate whether the issue is due to rest of DPU pipeline or in the DP controller itself. Expose a debugfs to use the TPG configuration to help debug DP issues. Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/dp/dp_debug.c | 61 +++++++++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/dp/dp_panel.h | 2 ++ 2 files changed, 63 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c b/drivers/gpu/drm/msm/dp/dp_= debug.c index 22fd946ee201..843fe77268f8 100644 --- a/drivers/gpu/drm/msm/dp/dp_debug.c +++ b/drivers/gpu/drm/msm/dp/dp_debug.c @@ -197,6 +197,65 @@ static const struct file_operations test_active_fops = =3D { .write =3D msm_dp_test_active_write }; =20 +static ssize_t msm_dp_tpg_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + const struct msm_dp_debug_private *debug; + char *input_buffer; + int val; + int status =3D 0; + struct msm_dp_panel *dp_panel; + + debug =3D ((struct seq_file *)file->private_data)->private; + dp_panel =3D debug->panel; + + input_buffer =3D memdup_user_nul(ubuf, len); + if (IS_ERR(input_buffer)) + return PTR_ERR(input_buffer); + + status =3D kstrtoint(input_buffer, 10, &val); + if (status < 0) { + kfree(input_buffer); + return status; + } + + msm_dp_panel_tpg_config(dp_panel, val); + + dp_panel->tpg_enabled =3D val; + + kfree(input_buffer); + + *offp +=3D len; + return len; +} + +static int msm_dp_tpg_show(struct seq_file *f, void *data) +{ + struct msm_dp_debug_private *debug =3D f->private; + struct msm_dp_panel *dp_panel =3D debug->panel; + + if (dp_panel->tpg_enabled) + seq_puts(f, "1"); + else + seq_puts(f, "0"); + + return 0; +} + +static int msm_dp_tpg_open(struct inode *inode, struct file *file) +{ + return single_open(file, msm_dp_tpg_show, inode->i_private); +} + +static const struct file_operations msm_dp_tpg_fops =3D { + .owner =3D THIS_MODULE, + .open =3D msm_dp_tpg_open, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, + .write =3D msm_dp_tpg_write +}; + int msm_dp_debug_init(struct device *dev, struct msm_dp_panel *panel, struct msm_dp_link *link, struct drm_connector *connector, @@ -231,6 +290,8 @@ int msm_dp_debug_init(struct device *dev, struct msm_dp= _panel *panel, debugfs_create_file("dp_test_type", 0444, root, debug, &msm_dp_test_type_fops); + + debugfs_create_file("dp_tpg", 0444, root, debug, &msm_dp_tpg_fops); } =20 return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 0e944db3adf2..7910b11fd685 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -50,6 +50,8 @@ struct msm_dp_panel { u32 max_dp_link_rate; =20 u32 max_bw_code; + + bool tpg_enabled; }; =20 int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel); --=20 2.34.1