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Tue, 03 Dec 2024 04:20:07 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B34K6qK004322 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 04:20:06 GMT Received: from hu-azarrabi-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 20:20:05 -0800 From: Amirreza Zarrabi Date: Mon, 2 Dec 2024 20:19:20 -0800 Subject: [PATCH 04/10] firmware: qcom: scm: add support for object invocation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241202-qcom-tee-using-tee-ss-without-mem-obj-v1-4-f502ef01e016@quicinc.com> References: <20241202-qcom-tee-using-tee-ss-without-mem-obj-v1-0-f502ef01e016@quicinc.com> In-Reply-To: <20241202-qcom-tee-using-tee-ss-without-mem-obj-v1-0-f502ef01e016@quicinc.com> To: Jens Wiklander , Sumit Garg , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Bartosz Golaszewski" , Srinivas Kandagatla CC: , , , , , Amirreza Zarrabi X-Mailer: b4 0.13.0 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: O0wZ70XPl-fToVsOs_2kbIYqTls9LMmc X-Proofpoint-GUID: O0wZ70XPl-fToVsOs_2kbIYqTls9LMmc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 suspectscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412030034 Qualcomm TEE (QTEE) hosts Trusted Applications (TAs) and services in the secure world, accessed via objects. A QTEE client can invoke these objects to request services. Similarly, QTEE can request services from the nonsecure world using objects exported to the secure world. This introduces low-level primitives to facilitate the invocation of objects hosted in QTEE, as well as those hosted in the nonsecure world. Signed-off-by: Amirreza Zarrabi --- drivers/firmware/qcom/qcom_scm.c | 60 ++++++++++++++++++++++++++++++= ++++ drivers/firmware/qcom/qcom_scm.h | 7 ++++ include/linux/firmware/qcom/qcom_scm.h | 9 +++++ 3 files changed, 76 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 72bf87ddcd96..8ac570df192b 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -1862,6 +1862,66 @@ static int qcom_scm_qseecom_init(struct qcom_scm *sc= m) =20 #endif /* CONFIG_QCOM_QSEECOM */ =20 +#ifdef CONFIG_QCOMTEE + +int qcom_scm_qtee_invoke_smc(u64 inbuf, u64 inbuf_size, u64 outbuf, u64 ou= tbuf_size, + u64 *result, u64 *response_type, u64 *data) +{ + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_SMCINVOKE, + .cmd =3D QCOM_SCM_SMCINVOKE_INVOKE, + .owner =3D ARM_SMCCC_OWNER_TRUSTED_OS, + .args[0] =3D inbuf, + .args[1] =3D inbuf_size, + .args[2] =3D outbuf, + .args[3] =3D outbuf_size, + .arginfo =3D QCOM_SCM_ARGS(4, QCOM_SCM_RW, QCOM_SCM_VAL, QCOM_SCM_RW, QC= OM_SCM_VAL), + }; + struct qcom_scm_res res; + int ret; + + ret =3D qcom_scm_call(__scm->dev, &desc, &res); + if (ret) + return ret; + + *response_type =3D res.result[0]; + *result =3D res.result[1]; + if (data) + *data =3D res.result[2]; + + return 0; +} +EXPORT_SYMBOL(qcom_scm_qtee_invoke_smc); + +int qcom_scm_qtee_callback_response(u64 buf, u64 buf_size, u64 *result, u6= 4 *response_type, + u64 *data) +{ + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_SMCINVOKE, + .cmd =3D QCOM_SCM_SMCINVOKE_CB_RSP, + .owner =3D ARM_SMCCC_OWNER_TRUSTED_OS, + .args[0] =3D buf, + .args[1] =3D buf_size, + .arginfo =3D QCOM_SCM_ARGS(2, QCOM_SCM_RW, QCOM_SCM_VAL), + }; + struct qcom_scm_res res; + int ret; + + ret =3D qcom_scm_call(__scm->dev, &desc, &res); + if (ret) + return ret; + + *response_type =3D res.result[0]; + *result =3D res.result[1]; + if (data) + *data =3D res.result[2]; + + return 0; +} +EXPORT_SYMBOL(qcom_scm_qtee_callback_response); + +#endif /* CONFIG_QCOMTEE */ + /** * qcom_scm_is_available() - Checks if SCM is available */ diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_= scm.h index e36b2f67607f..6b6bdee39236 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -148,6 +148,13 @@ struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void); #define QCOM_SCM_SVC_GPU 0x28 #define QCOM_SCM_SVC_GPU_INIT_REGS 0x01 =20 +/* ARM_SMCCC_OWNER_TRUSTED_OS calls */ + +#define QCOM_SCM_SVC_SMCINVOKE 0x06 +#define QCOM_SCM_SMCINVOKE_INVOKE_LEGACY 0x00 +#define QCOM_SCM_SMCINVOKE_CB_RSP 0x01 +#define QCOM_SCM_SMCINVOKE_INVOKE 0x02 + /* common error codes */ #define QCOM_SCM_V2_EBUSY -12 #define QCOM_SCM_ENOMEM -5 diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmwar= e/qcom/qcom_scm.h index 4621aec0328c..2e2a6abf9e34 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -168,4 +168,13 @@ static inline int qcom_scm_qseecom_app_send(u32 app_id, =20 #endif /* CONFIG_QCOM_QSEECOM */ =20 +#ifdef CONFIG_QCOMTEE + +int qcom_scm_qtee_invoke_smc(u64 inbuf, u64 inbuf_size, u64 outbuf, u64 ou= tbuf_size, + u64 *result, u64 *response_type, u64 *data); +int qcom_scm_qtee_callback_response(u64 buf, u64 buf_size, u64 *result, u6= 4 *response_type, + u64 *data); + +#endif /* CONFIG_QCOMTEE */ + #endif --=20 2.34.1