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In order to distinguish the streams better, describe the current pixel clock better to emphasize that it drives the stream 0. Signed-off-by: Abhinav Kumar --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index a212f335d5ff..35ae2630c2b3 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -55,7 +55,7 @@ properties: - description: Display Port AUX clock - description: Display Port Link clock - description: Link interface clock between DP and PHY - - description: Display Port Pixel clock + - description: Display Port stream 0 Pixel clock =20 clock-names: items: @@ -68,7 +68,7 @@ properties: assigned-clocks: items: - description: link clock source - - description: pixel clock source + - description: stream 0 pixel clock source =20 assigned-clock-parents: items: --=20 2.34.1 From nobody Wed Dec 4 18:57:03 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B7B52905; 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Signed-off-by: Abhinav Kumar --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 35ae2630c2b3..9fe2bf0484d8 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -72,8 +72,8 @@ properties: =20 assigned-clock-parents: items: - - description: phy 0 parent - - description: phy 1 parent + - description: Link clock PLL output provided by PHY block + - description: Stream 0 pixel clock PLL output provided by PHY block =20 phys: maxItems: 1 --=20 2.34.1 From nobody Wed Dec 4 18:57:03 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CDDB36AEC; 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Tue, 03 Dec 2024 03:32:15 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B33WEeY003570 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 03:32:14 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 19:32:14 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 19:31:41 -0800 Subject: [PATCH 3/4] dt-bindings: display/msm: add stream 1 pixel clock binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241202-dp_mst_bindings-v1-3-9a9a43b0624a@quicinc.com> References: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> In-Reply-To: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Mahadevan CC: , , , , , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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To support MST on such chipsets, add the binding for stream 1 pixel clock for display port controller. Since this mode is not supported on all chipsets, add exception rules and min/max items to clearly mark which chipsets support only SST mode (single stream) and which ones support MST. Signed-off-by: Abhinav Kumar --- .../bindings/display/msm/dp-controller.yaml | 32 ++++++++++++++++++= ++++ .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 9 ++++-- 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 9fe2bf0484d8..650d19e58277 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -50,30 +50,38 @@ properties: maxItems: 1 =20 clocks: + minItems: 5 items: - description: AHB clock to enable register access - description: Display Port AUX clock - description: Display Port Link clock - description: Link interface clock between DP and PHY - description: Display Port stream 0 Pixel clock + - description: Display Port stream 1 Pixel clock =20 clock-names: + minItems: 5 items: - const: core_iface - const: core_aux - const: ctrl_link - const: ctrl_link_iface - const: stream_pixel + - const: stream_1_pixel =20 assigned-clocks: + minItems: 2 items: - description: link clock source - description: stream 0 pixel clock source + - description: stream 1 pixel clock source =20 assigned-clock-parents: + minItems: 2 items: - description: Link clock PLL output provided by PHY block - description: Stream 0 pixel clock PLL output provided by PHY block + - description: Stream 1 pixel clock PLL output provided by PHY block =20 phys: maxItems: 1 @@ -175,6 +183,30 @@ allOf: required: - "#sound-dai-cells" =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-dp + + then: + properties: + clocks: + maxItems: 6 + clock-names: + items: + - const: core_iface + - const: core_aux + - const: ctrl_link + - const: ctrl_link_iface + - const: stream_pixel + - const: stream_1_pixel + assigned-clocks: + maxItems: 3 + assigned-clock-parents: + maxItems: 3 + additionalProperties: false =20 examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mds= s.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.ya= ml index 58f8a01f29c7..7f10e6ad8f63 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -177,16 +177,19 @@ examples: <&dispcc_dptx0_aux_clk>, <&dispcc_dptx0_link_clk>, <&dispcc_dptx0_link_intf_clk>, - <&dispcc_dptx0_pixel0_clk>; + <&dispcc_dptx0_pixel0_clk>, + <&dispcc_dptx0_pixel1_clk>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 assigned-clocks =3D <&dispcc_mdss_dptx0_link_clk_src>, + <&dispcc_mdss_dptx0_pixel1_clk_src>, <&dispcc_mdss_dptx0_pixel0_clk_src>; - assigned-clock-parents =3D <&mdss0_edp_phy 0>, <&mdss0_edp_phy= 1>; + assigned-clock-parents =3D <&mdss0_edp_phy 0>, <&mdss0_edp_phy= 1>, <&mdss0_edp_phy 1>; =20 phys =3D <&mdss0_edp_phy>; phy-names =3D "dp"; --=20 2.34.1 From nobody Wed Dec 4 18:57:03 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36A853F9D2; Tue, 3 Dec 2024 03:32:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; 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Tue, 03 Dec 2024 03:32:16 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B33WFhX003573 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 03:32:15 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 19:32:14 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 19:31:42 -0800 Subject: [PATCH 4/4] dt-bindings: display: msm: dp: update maintainer entry Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241202-dp_mst_bindings-v1-4-9a9a43b0624a@quicinc.com> References: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> In-Reply-To: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Mahadevan CC: , , , , , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Signed-off-by: Abhinav Kumar --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 650d19e58277..9867eb5133ab 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -8,6 +8,7 @@ title: MSM Display Port Controller =20 maintainers: - Kuogee Hsieh + - Abhinav Kumar =20 description: | Device tree bindings for DisplayPort host controller for MSM targets --=20 2.34.1