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[82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:18 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v4 01/18] clk: imx8mm: rename video_pll1 to video_pll Date: Sun, 1 Dec 2024 18:46:01 +0100 Message-ID: <20241201174639.742000-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings. The IMX8MM_VIDEO_PLL1* constants have not been removed to ensure backward compatibility of the patch. No functional changes intended. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) drivers/clk/imx/clk-imx8mm.c | 102 +++++++++++------------ include/dt-bindings/clock/imx8mm-clock.h | 12 ++- 2 files changed, 59 insertions(+), 55 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 342049b847b9..8a1fc7e17ba2 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -28,7 +28,7 @@ static u32 share_count_nand; static const char *pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy", "dumm= y", }; static const char *audio_pll1_bypass_sels[] =3D {"audio_pll1", "audio_pll1= _ref_sel", }; static const char *audio_pll2_bypass_sels[] =3D {"audio_pll2", "audio_pll2= _ref_sel", }; -static const char *video_pll1_bypass_sels[] =3D {"video_pll1", "video_pll1= _ref_sel", }; +static const char *video_pll_bypass_sels[] =3D {"video_pll", "video_pll_re= f_sel", }; static const char *dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pll_ref_s= el", }; static const char *gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_ref_sel"= , }; static const char *vpu_pll_bypass_sels[] =3D {"vpu_pll", "vpu_pll_ref_sel"= , }; @@ -42,22 +42,22 @@ static const char *imx8mm_a53_sels[] =3D {"osc_24m", "a= rm_pll_out", "sys_pll2_500m static const char * const imx8mm_a53_core_sels[] =3D {"arm_a53_div", "arm_= pll_out", }; =20 static const char *imx8mm_m4_sels[] =3D {"osc_24m", "sys_pll2_200m", "sys_= pll2_250m", "sys_pll1_266m", - "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_= out", }; + "sys_pll1_800m", "audio_pll1_out", "video_pll_out", "sys_pll3_o= ut", }; =20 static const char *imx8mm_vpu_sels[] =3D {"osc_24m", "arm_pll_out", "sys_p= ll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "vpu_pll_out", }; =20 static const char *imx8mm_gpu3d_sels[] =3D {"osc_24m", "gpu_pll_out", "sys= _pll1_800m", "sys_pll3_out", - "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_o= ut", }; + "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "audio_pll2_ou= t", }; =20 static const char *imx8mm_gpu2d_sels[] =3D {"osc_24m", "gpu_pll_out", "sys= _pll1_800m", "sys_pll3_out", - "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_o= ut", }; + "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "audio_pll2_ou= t", }; =20 static const char *imx8mm_main_axi_sels[] =3D {"osc_24m", "sys_pll2_333m",= "sys_pll1_800m", "sys_pll2_250m", - "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "sys_pll1_= 100m",}; + "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "sys_pll1_1= 00m",}; =20 static const char *imx8mm_enet_axi_sels[] =3D {"osc_24m", "sys_pll1_266m",= "sys_pll1_800m", "sys_pll2_250m", - "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_o= ut", }; + "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_ou= t", }; =20 static const char *imx8mm_nand_usdhc_sels[] =3D {"osc_24m", "sys_pll1_266m= ", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_= out", }; @@ -72,28 +72,28 @@ static const char *imx8mm_disp_apb_sels[] =3D {"osc_24m= ", "sys_pll2_125m", "sys_pl "sys_pll1_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", }; =20 static const char *imx8mm_disp_rtrm_sels[] =3D {"osc_24m", "sys_pll1_800m"= , "sys_pll2_200m", "sys_pll2_1000m", - "audio_pll1_out", "video_pll1_out", "clk_ext2", "clk_ext3", }; + "audio_pll1_out", "video_pll_out", "clk_ext2", "clk_ext3", }; =20 static const char *imx8mm_usb_bus_sels[] =3D {"osc_24m", "sys_pll2_500m", = "sys_pll1_800m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; =20 static const char *imx8mm_gpu_axi_sels[] =3D {"osc_24m", "sys_pll1_800m", = "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", - "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; =20 static const char *imx8mm_gpu_ahb_sels[] =3D {"osc_24m", "sys_pll1_800m", = "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", - "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; =20 static const char *imx8mm_noc_sels[] =3D {"osc_24m", "sys_pll1_800m", "sys= _pll3_out", "sys_pll2_1000m", "sys_pll2_500m", - "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; =20 static const char *imx8mm_noc_apb_sels[] =3D {"osc_24m", "sys_pll1_400m", = "sys_pll3_out", "sys_pll2_333m", "sys_pll2_200m", - "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", }; + "sys_pll1_800m", "audio_pll1_out", "video_pll_out", }; =20 static const char *imx8mm_ahb_sels[] =3D {"osc_24m", "sys_pll1_133m", "sys= _pll1_800m", "sys_pll1_400m", - "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", = }; + "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", }; =20 static const char *imx8mm_audio_ahb_sels[] =3D {"osc_24m", "sys_pll2_500m"= , "sys_pll1_800m", "sys_pll2_1000m", - "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll1_= out", }; + "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll_o= ut", }; =20 static const char *imx8mm_dram_alt_sels[] =3D {"osc_24m", "sys_pll1_800m",= "sys_pll1_100m", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll1_out", "sys_pll1_26= 6m", }; @@ -108,10 +108,10 @@ static const char *imx8mm_vpu_g2_sels[] =3D {"osc_24m= ", "vpu_pll_out", "sys_pll1_8 "sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out"= , }; =20 static const char *imx8mm_disp_dtrc_sels[] =3D {"osc_24m", "dummy", "sys_p= ll1_800m", "sys_pll2_1000m", - "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_= out", }; + "sys_pll1_160m", "video_pll_out", "sys_pll3_out", "audio_pll2_o= ut", }; =20 static const char *imx8mm_disp_dc8000_sels[] =3D {"osc_24m", "dummy", "sys= _pll1_800m", "sys_pll2_1000m", - "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out",= }; + "sys_pll1_160m", "video_pll_out", "sys_pll3_out", "audio_pll2_out", = }; =20 static const char *imx8mm_pcie1_ctrl_sels[] =3D {"osc_24m", "sys_pll2_250m= ", "sys_pll2_200m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_o= ut", }; @@ -122,47 +122,47 @@ static const char *imx8mm_pcie1_phy_sels[] =3D {"osc_= 24m", "sys_pll2_100m", "sys_p static const char *imx8mm_pcie1_aux_sels[] =3D {"osc_24m", "sys_pll2_200m"= , "sys_pll2_50m", "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200= m", }; =20 -static const char *imx8mm_dc_pixel_sels[] =3D {"osc_24m", "video_pll1_out"= , "audio_pll2_out", "audio_pll1_out", +static const char *imx8mm_dc_pixel_sels[] =3D {"osc_24m", "video_pll_out",= "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; =20 -static const char *imx8mm_lcdif_pixel_sels[] =3D {"osc_24m", "video_pll1_o= ut", "audio_pll2_out", "audio_pll1_out", +static const char *imx8mm_lcdif_pixel_sels[] =3D {"osc_24m", "video_pll_ou= t", "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; =20 -static const char *imx8mm_sai1_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai1_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", }; =20 -static const char *imx8mm_sai2_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai2_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 -static const char *imx8mm_sai3_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai3_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 -static const char *imx8mm_sai4_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai4_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", }; =20 -static const char *imx8mm_sai5_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai5_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 -static const char *imx8mm_sai6_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai6_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 -static const char *imx8mm_spdif1_sels[] =3D {"osc_24m", "audio_pll1_out", = "audio_pll2_out", "video_pll1_out", +static const char *imx8mm_spdif1_sels[] =3D {"osc_24m", "audio_pll1_out", = "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 -static const char *imx8mm_spdif2_sels[] =3D {"osc_24m", "audio_pll1_out", = "audio_pll2_out", "video_pll1_out", +static const char *imx8mm_spdif2_sels[] =3D {"osc_24m", "audio_pll1_out", = "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 static const char *imx8mm_enet_ref_sels[] =3D {"osc_24m", "sys_pll2_125m",= "sys_pll2_50m", "sys_pll2_100m", - "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4",= }; + "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", = }; =20 static const char *imx8mm_enet_timer_sels[] =3D {"osc_24m", "sys_pll2_100m= ", "audio_pll1_out", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4", "video_pll1_out", }; + "clk_ext3", "clk_ext4", "video_pll_out", }; =20 static const char *imx8mm_enet_phy_sels[] =3D {"osc_24m", "sys_pll2_50m", = "sys_pll2_125m", "sys_pll2_200m", - "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", }; + "sys_pll2_500m", "video_pll_out", "audio_pll2_out", }; =20 static const char *imx8mm_nand_sels[] =3D {"osc_24m", "sys_pll2_500m", "au= dio_pll1_out", "sys_pll1_400m", - "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll1_out",= }; + "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll_out", = }; =20 static const char *imx8mm_qspi_sels[] =3D {"osc_24m", "sys_pll1_400m", "sy= s_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", = }; @@ -174,16 +174,16 @@ static const char *imx8mm_usdhc2_sels[] =3D {"osc_24m= ", "sys_pll1_400m", "sys_pll1 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m"= , }; =20 static const char *imx8mm_i2c1_sels[] =3D {"osc_24m", "sys_pll1_160m", "sy= s_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char *imx8mm_i2c2_sels[] =3D {"osc_24m", "sys_pll1_160m", "sy= s_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char *imx8mm_i2c3_sels[] =3D {"osc_24m", "sys_pll1_160m", "sy= s_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char *imx8mm_i2c4_sels[] =3D {"osc_24m", "sys_pll1_160m", "sy= s_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char *imx8mm_uart1_sels[] =3D {"osc_24m", "sys_pll1_80m", "sy= s_pll2_200m", "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; @@ -213,19 +213,19 @@ static const char *imx8mm_ecspi2_sels[] =3D {"osc_24m= ", "sys_pll2_200m", "sys_pll1 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out"= , }; =20 static const char *imx8mm_pwm1_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; =20 static const char *imx8mm_pwm2_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; =20 static const char *imx8mm_pwm3_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; =20 static const char *imx8mm_pwm4_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; =20 static const char *imx8mm_gpt1_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_400m", "sys_pll1_40m", - "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; + "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; =20 static const char *imx8mm_wdog_sels[] =3D {"osc_24m", "sys_pll1_133m", "sy= s_pll1_160m", "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; @@ -234,31 +234,31 @@ static const char *imx8mm_wrclk_sels[] =3D {"osc_24m"= , "sys_pll1_40m", "vpu_pll_ou "sys_pll1_266m", "sys_pll2_500m", "sys_pll1_100m", }; =20 static const char *imx8mm_dsi_core_sels[] =3D {"osc_24m", "sys_pll1_266m",= "sys_pll2_250m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_= out", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_o= ut", }; =20 static const char *imx8mm_dsi_phy_sels[] =3D {"osc_24m", "sys_pll2_125m", = "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out",= }; + "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out", = }; =20 static const char *imx8mm_dsi_dbi_sels[] =3D {"osc_24m", "sys_pll1_266m", = "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_o= ut", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_ou= t", }; =20 static const char *imx8mm_usdhc3_sels[] =3D {"osc_24m", "sys_pll1_400m", "= sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m"= , }; =20 static const char *imx8mm_csi1_core_sels[] =3D {"osc_24m", "sys_pll1_266m"= , "sys_pll2_250m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1= _out", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_= out", }; =20 static const char *imx8mm_csi1_phy_sels[] =3D {"osc_24m", "sys_pll2_333m",= "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out"= , }; + "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out",= }; =20 static const char *imx8mm_csi1_esc_sels[] =3D {"osc_24m", "sys_pll2_100m",= "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", = }; =20 static const char *imx8mm_csi2_core_sels[] =3D {"osc_24m", "sys_pll1_266m"= , "sys_pll2_250m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1= _out", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_= out", }; =20 static const char *imx8mm_csi2_phy_sels[] =3D {"osc_24m", "sys_pll2_333m",= "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out"= , }; + "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out",= }; =20 static const char *imx8mm_csi2_esc_sels[] =3D {"osc_24m", "sys_pll2_100m",= "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", = }; @@ -286,9 +286,9 @@ static const char *imx8mm_dram_core_sels[] =3D {"dram_p= ll_out", "dram_alt_root", } static const char *imx8mm_clko1_sels[] =3D {"osc_24m", "sys_pll1_800m", "d= ummy", "sys_pll1_200m", "audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", }; static const char *imx8mm_clko2_sels[] =3D {"osc_24m", "sys_pll2_200m", "s= ys_pll1_400m", "sys_pll2_166m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", }; + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", }; =20 -static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll1_out", +static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; @@ -327,7 +327,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MM_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", b= ase + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", b= ase + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_VIDEO_PLL1_REF_SEL] =3D imx_clk_hw_mux("video_pll1_ref_sel", b= ase + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", bas= e + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", base = + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", base + = 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_VPU_PLL_REF_SEL] =3D imx_clk_hw_mux("vpu_pll_ref_sel", base + = 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); @@ -336,7 +336,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MM_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", base + 0x28, &imx_1443x_pll); + hws[IMX8MM_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", base + 0x28, &imx_1443x_pll); hws[IMX8MM_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); hws[IMX8MM_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); hws[IMX8MM_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = base + 0x74, &imx_1416x_pll); @@ -348,7 +348,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) /* PLL bypass out */ hws[IMX8MM_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels),= CLK_SET_RATE_PARENT); hws[IMX8MM_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_VIDEO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("video_pll1_bypass= ", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass= _sels), CLK_SET_RATE_PARENT); + hws[IMX8MM_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sel= s), CLK_SET_RATE_PARENT); hws[IMX8MM_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", b= ase + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), = CLK_SET_RATE_PARENT); hws[IMX8MM_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", bas= e + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); hws[IMX8MM_VPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("vpu_pll_bypass", bas= e + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); @@ -358,7 +358,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) /* PLL out gate */ hws[IMX8MM_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", base, 13); hws[IMX8MM_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", base + 0x14, 13); - hws[IMX8MM_VIDEO_PLL1_OUT] =3D imx_clk_hw_gate("video_pll1_out", "video_p= ll1_bypass", base + 0x28, 13); + hws[IMX8MM_VIDEO_PLL_OUT] =3D imx_clk_hw_gate("video_pll_out", "video_pll= _bypass", base + 0x28, 13); hws[IMX8MM_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", base + 0x50, 13); hws[IMX8MM_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", base + 0x64, 11); hws[IMX8MM_VPU_PLL_OUT] =3D imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypas= s", base + 0x74, 11); diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings= /clock/imx8mm-clock.h index 1f768b2eeb1a..102d8a6cdb55 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -16,7 +16,8 @@ #define IMX8MM_CLK_EXT4 7 #define IMX8MM_AUDIO_PLL1_REF_SEL 8 #define IMX8MM_AUDIO_PLL2_REF_SEL 9 -#define IMX8MM_VIDEO_PLL1_REF_SEL 10 +#define IMX8MM_VIDEO_PLL_REF_SEL 10 +#define IMX8MM_VIDEO_PLL1_REF_SEL IMX8MM_VIDEO_PLL_REF_SEL #define IMX8MM_DRAM_PLL_REF_SEL 11 #define IMX8MM_GPU_PLL_REF_SEL 12 #define IMX8MM_VPU_PLL_REF_SEL 13 @@ -26,7 +27,8 @@ #define IMX8MM_SYS_PLL3_REF_SEL 17 #define IMX8MM_AUDIO_PLL1 18 #define IMX8MM_AUDIO_PLL2 19 -#define IMX8MM_VIDEO_PLL1 20 +#define IMX8MM_VIDEO_PLL 20 +#define IMX8MM_VIDEO_PLL1 IMX8MM_VIDEO_PLL #define IMX8MM_DRAM_PLL 21 #define IMX8MM_GPU_PLL 22 #define IMX8MM_VPU_PLL 23 @@ -36,7 +38,8 @@ #define IMX8MM_SYS_PLL3 27 #define IMX8MM_AUDIO_PLL1_BYPASS 28 #define IMX8MM_AUDIO_PLL2_BYPASS 29 -#define IMX8MM_VIDEO_PLL1_BYPASS 30 +#define IMX8MM_VIDEO_PLL_BYPASS 30 +#define IMX8MM_VIDEO_PLL1_BYPASS IMX8MM_VIDEO_PLL_BYPASS #define IMX8MM_DRAM_PLL_BYPASS 31 #define IMX8MM_GPU_PLL_BYPASS 32 #define IMX8MM_VPU_PLL_BYPASS 33 @@ -46,7 +49,8 @@ #define IMX8MM_SYS_PLL3_BYPASS 37 #define IMX8MM_AUDIO_PLL1_OUT 38 #define IMX8MM_AUDIO_PLL2_OUT 39 -#define IMX8MM_VIDEO_PLL1_OUT 40 +#define IMX8MM_VIDEO_PLL_OUT 40 +#define IMX8MM_VIDEO_PLL1_OUT IMX8MM_VIDEO_PLL_OUT #define IMX8MM_DRAM_PLL_OUT 41 #define IMX8MM_GPU_PLL_OUT 42 #define IMX8MM_VPU_PLL_OUT 43 --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D10661D86E6 for ; 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[82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:19 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v4 02/18] clk: imx8mp: rename video_pll1 to video_pll Date: Sun, 1 Dec 2024 18:46:02 +0100 Message-ID: <20241201174639.742000-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings. The IMX8MP_VIDEO_PLL1* constants have not been removed to ensure backward compatibility of the patch. No functional changes intended. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) drivers/clk/imx/clk-imx8mp.c | 118 +++++++++++------------ include/dt-bindings/clock/imx8mp-clock.h | 9 +- 2 files changed, 65 insertions(+), 62 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 516dbd170c8a..e96460534e7d 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -23,7 +23,7 @@ static u32 share_count_audio; static const char * const pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy"= , "dummy", }; static const char * const audio_pll1_bypass_sels[] =3D {"audio_pll1", "aud= io_pll1_ref_sel", }; static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; -static const char * const video_pll1_bypass_sels[] =3D {"video_pll1", "vid= eo_pll1_ref_sel", }; +static const char * const video_pll_bypass_sels[] =3D {"video_pll", "video= _pll_ref_sel", }; static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; static const char * const vpu_pll_bypass_sels[] =3D {"vpu_pll", "vpu_pll_r= ef_sel", }; @@ -40,27 +40,27 @@ static const char * const imx8mp_a53_core_sels[] =3D {"= arm_a53_div", "arm_pll_out" =20 static const char * const imx8mp_m7_sels[] =3D {"osc_24m", "sys_pll2_200m"= , "sys_pll2_250m", "vpu_pll_out", "sys_pll1_800m", "audio_pll1_out", - "video_pll1_out", "sys_pll3_out", }; + "video_pll_out", "sys_pll3_out", }; =20 static const char * const imx8mp_ml_sels[] =3D {"osc_24m", "gpu_pll_out", = "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_gpu3d_core_sels[] =3D {"osc_24m", "gpu_pl= l_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_gpu3d_shader_sels[] =3D {"osc_24m", "gpu_= pll_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_gpu2d_sels[] =3D {"osc_24m", "gpu_pll_out= ", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_audio_axi_sels[] =3D {"osc_24m", "gpu_pll= _out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_hsio_axi_sels[] =3D {"osc_24m", "sys_pll2= _500m", "sys_pll1_800m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", @@ -72,11 +72,11 @@ static const char * const imx8mp_media_isp_sels[] =3D {= "osc_24m", "sys_pll2_1000m" =20 static const char * const imx8mp_main_axi_sels[] =3D {"osc_24m", "sys_pll2= _333m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "sys_pll1_100m",}; + "video_pll_out", "sys_pll1_100m",}; =20 static const char * const imx8mp_enet_axi_sels[] =3D {"osc_24m", "sys_pll1= _266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", - "video_pll1_out", "sys_pll3_out", }; + "video_pll_out", "sys_pll3_out", }; =20 static const char * const imx8mp_nand_usdhc_sels[] =3D {"osc_24m", "sys_pl= l1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", @@ -96,35 +96,35 @@ static const char * const imx8mp_media_apb_sels[] =3D {= "osc_24m", "sys_pll2_125m", =20 static const char * const imx8mp_gpu_axi_sels[] =3D {"osc_24m", "sys_pll1_= 800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_gpu_ahb_sels[] =3D {"osc_24m", "sys_pll1_= 800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_noc_sels[] =3D {"osc_24m", "sys_pll1_800m= ", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_noc_io_sels[] =3D {"osc_24m", "sys_pll1_8= 00m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_ml_axi_sels[] =3D {"osc_24m", "sys_pll1_8= 00m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_ml_ahb_sels[] =3D {"osc_24m", "sys_pll1_8= 00m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_ahb_sels[] =3D {"osc_24m", "sys_pll1_133m= ", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; =20 static const char * const imx8mp_audio_ahb_sels[] =3D {"osc_24m", "sys_pll= 2_500m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; =20 static const char * const imx8mp_mipi_dsi_esc_rx_sels[] =3D {"osc_24m", "s= ys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", @@ -159,56 +159,56 @@ static const char * const imx8mp_pcie_aux_sels[] =3D = {"osc_24m", "sys_pll2_200m", "sys_pll1_160m", "sys_pll1_200m", }; =20 static const char * const imx8mp_i2c5_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_i2c6_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_sai1_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", }; =20 static const char * const imx8mp_sai2_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 static const char * const imx8mp_sai3_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mp_sai5_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 static const char * const imx8mp_sai6_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mp_enet_qos_sels[] =3D {"osc_24m", "sys_pll2= _125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", - "video_pll1_out", "clk_ext4", }; + "video_pll_out", "clk_ext4", }; =20 static const char * const imx8mp_enet_qos_timer_sels[] =3D {"osc_24m", "sy= s_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", - "clk_ext4", "video_pll1_out", }; + "clk_ext4", "video_pll_out", }; =20 static const char * const imx8mp_enet_ref_sels[] =3D {"osc_24m", "sys_pll2= _125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", - "video_pll1_out", "clk_ext4", }; + "video_pll_out", "clk_ext4", }; =20 static const char * const imx8mp_enet_timer_sels[] =3D {"osc_24m", "sys_pl= l2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", - "clk_ext4", "video_pll1_out", }; + "clk_ext4", "video_pll_out", }; =20 static const char * const imx8mp_enet_phy_ref_sels[] =3D {"osc_24m", "sys_= pll2_50m", "sys_pll2_125m", "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_nand_sels[] =3D {"osc_24m", "sys_pll2_500= m", "audio_pll1_out", "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", - "sys_pll2_250m", "video_pll1_out", }; + "sys_pll2_250m", "video_pll_out", }; =20 static const char * const imx8mp_qspi_sels[] =3D {"osc_24m", "sys_pll1_400= m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", @@ -223,19 +223,19 @@ static const char * const imx8mp_usdhc2_sels[] =3D {"= osc_24m", "sys_pll1_400m", "s "audio_pll2_out", "sys_pll1_100m", }; =20 static const char * const imx8mp_i2c1_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_i2c2_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_i2c3_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_i2c4_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_uart1_sels[] =3D {"osc_24m", "sys_pll1_80= m", "sys_pll2_200m", @@ -276,42 +276,42 @@ static const char * const imx8mp_ecspi2_sels[] =3D {"= osc_24m", "sys_pll2_200m", "s =20 static const char * const imx8mp_pwm1_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mp_pwm2_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mp_pwm3_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mp_pwm4_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mp_gpt1_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; =20 static const char * const imx8mp_gpt2_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext2" }; =20 static const char * const imx8mp_gpt3_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext3" }; =20 static const char * const imx8mp_gpt4_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; =20 static const char * const imx8mp_gpt5_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext2" }; =20 static const char * const imx8mp_gpt6_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext3" }; =20 static const char * const imx8mp_wdog_sels[] =3D {"osc_24m", "sys_pll1_133= m", "sys_pll1_160m", @@ -328,19 +328,19 @@ static const char * const imx8mp_ipp_do_clko1_sels[] = =3D {"osc_24m", "sys_pll1_800 =20 static const char * const imx8mp_ipp_do_clko2_sels[] =3D {"osc_24m", "sys_= pll2_200m", "sys_pll1_400m", "sys_pll1_166m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "osc_32k" }; + "video_pll_out", "osc_32k" }; =20 static const char * const imx8mp_hdmi_fdcc_tst_sels[] =3D {"osc_24m", "sys= _pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; =20 static const char * const imx8mp_hdmi_24m_sels[] =3D {"osc_24m", "sys_pll1= _160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_hdmi_ref_266m_sels[] =3D {"osc_24m", "sys= _pll1_400m", "sys_pll3_out", "sys_pll2_333m", "sys_pll1_266m", "sys_pll2_200m", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; =20 static const char * const imx8mp_usdhc3_sels[] =3D {"osc_24m", "sys_pll1_4= 00m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", @@ -349,26 +349,26 @@ static const char * const imx8mp_usdhc3_sels[] =3D {"= osc_24m", "sys_pll1_400m", "s static const char * const imx8mp_media_cam1_pix_sels[] =3D {"osc_24m", "sy= s_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; =20 static const char * const imx8mp_media_mipi_phy1_ref_sels[] =3D {"osc_24m"= , "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; =20 -static const char * const imx8mp_media_disp_pix_sels[] =3D {"osc_24m", "vi= deo_pll1_out", "audio_pll2_out", +static const char * const imx8mp_media_disp_pix_sels[] =3D {"osc_24m", "vi= deo_pll_out", "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; =20 static const char * const imx8mp_media_cam2_pix_sels[] =3D {"osc_24m", "sy= s_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; =20 static const char * const imx8mp_media_ldb_sels[] =3D {"osc_24m", "sys_pll= 2_333m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; =20 static const char * const imx8mp_memrepair_sels[] =3D {"osc_24m", "sys_pll= 2_100m", "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", @@ -392,12 +392,12 @@ static const char * const imx8mp_vpu_vc8000e_sels[] = =3D {"osc_24m", "vpu_pll_out", "sys_pll3_out", "audio_pll1_out", }; =20 static const char * const imx8mp_sai7_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mp_dram_core_sels[] =3D {"dram_pll_out", "dr= am_alt_root", }; =20 -static const char * const imx8mp_clkout_sels[] =3D {"audio_pll1_out", "aud= io_pll2_out", "video_pll1_out", +static const char * const imx8mp_clkout_sels[] =3D {"audio_pll1_out", "aud= io_pll2_out", "video_pll_out", "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; @@ -440,7 +440,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MP_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", a= natop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", a= natop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MP_VIDEO_PLL1_REF_SEL] =3D imx_clk_hw_mux("video_pll1_ref_sel", a= natop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MP_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", ana= top_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", anato= p_base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", anatop_= base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_VPU_PLL_REF_SEL] =3D imx_clk_hw_mux("vpu_pll_ref_sel", anatop_= base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); @@ -451,7 +451,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MP_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", anatop_base, &imx_1443x_pll); hws[IMX8MP_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", anatop_base + 0x14, &imx_1443x_pll); - hws[IMX8MP_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", anatop_base + 0x28, &imx_1443x_pll); + hws[IMX8MP_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", anatop_base + 0x28, &imx_1443x_pll); hws[IMX8MP_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", anatop_base + 0x50, &imx_1443x_dram_pll); hws[IMX8MP_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = anatop_base + 0x64, &imx_1416x_pll); hws[IMX8MP_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = anatop_base + 0x74, &imx_1416x_pll); @@ -462,7 +462,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MP_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass= _sels), CLK_SET_RATE_PARENT); hws[IMX8MP_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2= _bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MP_VIDEO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("video_pll1_bypass= ", anatop_base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1= _bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MP_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= anatop_base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_byp= ass_sels), CLK_SET_RATE_PARENT); hws[IMX8MP_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", a= natop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_= sels), CLK_SET_RATE_PARENT); hws[IMX8MP_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", ana= top_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels= ), CLK_SET_RATE_PARENT); hws[IMX8MP_VPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("vpu_pll_bypass", ana= top_base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels= ), CLK_SET_RATE_PARENT); @@ -473,7 +473,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MP_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", anatop_base, 13); hws[IMX8MP_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", anatop_base + 0x14, 13); - hws[IMX8MP_VIDEO_PLL1_OUT] =3D imx_clk_hw_gate("video_pll1_out", "video_p= ll1_bypass", anatop_base + 0x28, 13); + hws[IMX8MP_VIDEO_PLL_OUT] =3D imx_clk_hw_gate("video_pll_out", "video_pll= _bypass", anatop_base + 0x28, 13); hws[IMX8MP_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", anatop_base + 0x50, 13); hws[IMX8MP_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", anatop_base + 0x64, 11); hws[IMX8MP_VPU_PLL_OUT] =3D imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypas= s", anatop_base + 0x74, 11); diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings= /clock/imx8mp-clock.h index 7da4243984b2..0601df6c8d38 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -16,7 +16,8 @@ #define IMX8MP_CLK_EXT4 7 #define IMX8MP_AUDIO_PLL1_REF_SEL 8 #define IMX8MP_AUDIO_PLL2_REF_SEL 9 -#define IMX8MP_VIDEO_PLL1_REF_SEL 10 +#define IMX8MP_VIDEO_PLL_REF_SEL 10 +#define IMX8MP_VIDEO_PLL1_REF_SEL IMX8MP_VIDEO_PLL_REF_SEL #define IMX8MP_DRAM_PLL_REF_SEL 11 #define IMX8MP_GPU_PLL_REF_SEL 12 #define IMX8MP_VPU_PLL_REF_SEL 13 @@ -26,7 +27,8 @@ #define IMX8MP_SYS_PLL3_REF_SEL 17 #define IMX8MP_AUDIO_PLL1 18 #define IMX8MP_AUDIO_PLL2 19 -#define IMX8MP_VIDEO_PLL1 20 +#define IMX8MP_VIDEO_PLL 20 +#define IMX8MP_VIDEO_PLL1 IMX8MP_VIDEO_PLL #define IMX8MP_DRAM_PLL 21 #define IMX8MP_GPU_PLL 22 #define IMX8MP_VPU_PLL 23 @@ -46,7 +48,8 @@ #define IMX8MP_SYS_PLL3_BYPASS 37 #define IMX8MP_AUDIO_PLL1_OUT 38 #define IMX8MP_AUDIO_PLL2_OUT 39 -#define IMX8MP_VIDEO_PLL1_OUT 40 +#define IMX8MP_VIDEO_PLL_OUT 40 +#define IMX8MP_VIDEO_PLL1_OUT IMX8MP_VIDEO_PLL_OUT #define IMX8MP_DRAM_PLL_OUT 41 #define IMX8MP_GPU_PLL_OUT 42 #define IMX8MP_VPU_PLL_OUT 43 --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A28B91D88DC for ; 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[82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:22 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v4 03/18] dt-bindings: clock: imx8m-anatop: define clocks/clock-names Date: Sun, 1 Dec 2024 18:46:03 +0100 Message-ID: <20241201174639.742000-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define clocks and clock-names properties of the anatop device node. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) .../bindings/clock/fsl,imx8m-anatop.yaml | 53 ++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml = b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml index bbd22e95b319..f439b0a94ce2 100644 --- a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml +++ b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml @@ -30,22 +30,73 @@ properties: interrupts: maxItems: 1 =20 + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + '#clock-cells': const: 1 =20 required: - compatible - reg + - clocks + - clock-names - '#clock-cells' =20 +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8mq-anatop + then: + properties: + clocks: + items: + - description: 32k osc + - description: 25m osc + - description: 27m osc + clock-names: + items: + - const: ckil + - const: osc_25m + - const: osc_27m + else: + properties: + clocks: + items: + - description: 32k osc + - description: 24m osc + + clock-names: + items: + - const: osc_32k + - const: osc_24m + additionalProperties: false =20 examples: - | - anatop: clock-controller@30360000 { + clock-controller@30360000 { compatible =3D "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg =3D <0x30360000 0x10000>; #clock-cells =3D <1>; + clocks =3D <&osc_32k>, <&osc_24m>; + clock-names =3D "osc_32k", "osc_24m"; + }; + + - | + clock-controller@30360000 { + compatible =3D "fsl,imx8mq-anatop"; + reg =3D <0x30360000 0x10000>; + #clock-cells =3D <1>; + clocks =3D <&ckil>, <&osc_25m>, <&osc_27m>; + clock-names =3D "ckil", "osc_25m", "osc_27m"; }; =20 ... --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9D2A1D9329 for ; Sun, 1 Dec 2024 17:47:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733075250; cv=none; b=OQt2crmJ7+nSSB+JpQk863JjV9LfKt9op+luxKWAwrY+ffxNovjtVMB6PiWrklUc7zjFpn3Hb5RwILvKDUC0LFdk7MU5NK+37UUoCrLtTPOSewnHTtXSgJ4RuXbmPc6/ElY1Du0BaRNPkTXNllNjZVbYip9maFHH2Df6PLJQCS8= ARC-Message-Signature: i=1; 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[82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:23 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 04/18] arm64: dts: imx8mm: add anatop clocks Date: Sun, 1 Dec 2024 18:46:04 +0100 Message-ID: <20241201174639.742000-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clocks to anatop node. Add the bindings definitions for the anatop node. The patch is preparatory for future developments. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mm.dtsi index 4de3bf22902b..597041a05073 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -600,6 +600,8 @@ anatop: clock-controller@30360000 { compatible =3D "fsl,imx8mm-anatop"; reg =3D <0x30360000 0x10000>; #clock-cells =3D <1>; + clocks =3D <&osc_32k>, <&osc_24m>; + clock-names =3D "osc_32k", "osc_24m"; }; =20 snvs: snvs@30370000 { --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45AD31D933A for ; Sun, 1 Dec 2024 17:47:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733075250; cv=none; b=iJM58CYT5VLIcTi+zvR7U9wIg9FV6fzbTzSakWaJhJd2qA30Jy9F4/F5taU4Lp5pYzmscfT1flZpdJItywchGplET4BWXHTqhwUz9GYlsB2al1RIyuW0ICZ75Gbu2w8ju00jJEVUONSWrBGRApNlpTAsyTmYz+2mMt3soFgDoNo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733075250; c=relaxed/simple; bh=pAZvwlhdsPQOXTECn8htnfBSk5QEXWk0LGMj+aO20ko=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=h8soqBc0839bmYKhYm6RgafRCiwc5WB3xLXauee8w/W4mqMGo2PHbZCBz+JamybRKkyw2E8RKpDw9oaxT+zSZMZnOk2mj9GgLSaiMHwTt0rxmTwhvbHu0Z7nW2WP8XaxUmLRmbbdRMOESfjRSvy08j18BYrHdhoQnXYbxUCaeyE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=A42SVbds; arc=none smtp.client-ip=209.85.218.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="A42SVbds" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-aa5b0d8bd41so373380766b.2 for ; Sun, 01 Dec 2024 09:47:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1733075247; x=1733680047; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=25hkQ29mTLGKqj1oFjf7AGoT1DWsKqPuwzAecsYSYFU=; b=A42SVbdsNGzk3gHTrp22u1MnL7so/pO639stk/E4fX9ySQvMbdX7RTjwCQNUuEt2aF P5xUPci9D2RRLiaPKl6tc6QjRKCb/Is9nRXSezQ02hKBar2mgWLMT3D752z5UvM186CT Ds/P9Xf/H2C0ehlvINPQsSRI9jsU9GPdjqlSc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733075247; x=1733680047; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=25hkQ29mTLGKqj1oFjf7AGoT1DWsKqPuwzAecsYSYFU=; b=oSCOU6UnnCVefYKajG8vTNHlRKwP2AwHRmWwqc6ANo3g3AYl32IdbvxRsVDQjS3vLl DruMA6Nl/fMVI8ARfvC90WuhuuE+K0uctLBBRORdU3O9qxGvZdEjNMEhE2CBJQ/l48PE 4r9K1mMRpV+qEISlAmAhH5g5hKSRjOAwKBsh9jlfygwLcaf4WlDXxlEFFTNVIJxw6/qD bW0qb52IGH3Yg8Afu5bW5Gm/xe98rXQMU2iAnKkWdUGxhnswUjtlQXJBp0vO98e+1S2j 4vWJFrjgKTOjX3j6Z/oytNxh0lql8YnhPS2h/Dt6VHA0dBW2hRvktSKNYDgVoVMdnEGA 0yHQ== X-Gm-Message-State: AOJu0YwziuyiJJJFQAymiFFm+AzDVz7B2oHLftoOUqIUKoFk55LPDNFe qUEEG7bSi4OKUNvJQ8YKhxjeW6tgnNBgAfYgOIDYDexB5ZN/fufQccMqn6scFMnGHbDQHmDVws6 a X-Gm-Gg: ASbGncsS8RgeNhZwG1mM4YPzcGt2feXzkhAHVKP/iLiz2UpW1ykFHekkTLumKFwZhEm yYzAVmI7xqq7Ne2LSqNlXMwTI0XGwRMXO104N+zUcvla//467TucX4VzSXwrMTeWd5Q2u5LMQcO R+wNRR6ZZmXu7a9yEh+U566gk1Hs5OGanAkmAbSIHxsdLfgLiFDHzb24g9ThSj2z5+N0WinxIn0 C6O8Z+jRJEH+Tmso4tY/JNUwr441FYCWbBdeEQgJKfcNT1HjsZ3lYBD2Oh7qPmuA1nvw+gTWoHv YdskimHBJBudr1c3Th42ElbycVfiqMyzpLF7wdkyX3rF9rNNyInp3nXMHMwmbs7C/Eq6R/V7k2R nJxhG+5TU9aZQ1wMK X-Google-Smtp-Source: AGHT+IETqWOabkVlO1PkfWKeKFWRO9lagZn7Lq5BjUv+Xpoj3trCPw9o4vBjnJJzR25eaHHFJ7m37Q== X-Received: by 2002:a17:906:3152:b0:aa5:2232:c8e4 with SMTP id a640c23a62f3a-aa580ee8d1cmr1705022666b.11.1733075247468; Sun, 01 Dec 2024 09:47:27 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-82-54-94-193.retail.telecomitalia.it. [82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:26 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 05/18] arm64: dts: imx8mn: add anatop clocks Date: Sun, 1 Dec 2024 18:46:05 +0100 Message-ID: <20241201174639.742000-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clocks to anatop node. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) arch/arm64/boot/dts/freescale/imx8mn.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mn.dtsi index a5f9cfb46e5d..49be492b5687 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -606,6 +606,8 @@ anatop: clock-controller@30360000 { compatible =3D "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg =3D <0x30360000 0x10000>; #clock-cells =3D <1>; + clocks =3D <&osc_32k>, <&osc_24m>; + clock-names =3D "osc_32k", "osc_24m"; }; =20 snvs: snvs@30370000 { --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A964E1D95AA for ; Sun, 1 Dec 2024 17:47:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733075252; cv=none; b=NPFZY6MoWO/9IqKwjEF5n8rRJCz5bjcE4R/YaYuU/FUUCCEq0CFt6rD5V3jVLDSDQ10ecqeqYxrARtzXvLaM+EFRYHn9kfH+ehGorrK4HjrJLLwspDdcaqwfeuhNNswkeN+nTGPQ99I3BmkFM8vg+K3sYbn5shebK6luGpxyjnw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733075252; c=relaxed/simple; bh=Ac4blgYWf7CVzjbS2BlFj/S4aCoc/+2YA3/WYpgya9E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PVsRDBlo8hVRWXvBKEaCvHC3Oy7XkMqNS+QpSrmyWuFHWQgCEnGqLGi/W07XuZR+QuvXkezg3onIDsE8JYaltcFYuH76U97nN0azzaIBAWnalgQ4/htEWn3gIRtfr/8P2A6s406vngFQvmdHt/rHBYggC4xkmzmAyHajClIqm0k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=BCRYhjhe; arc=none smtp.client-ip=209.85.218.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="BCRYhjhe" Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-aa503cced42so519224866b.3 for ; Sun, 01 Dec 2024 09:47:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1733075248; x=1733680048; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GYgi3gWsFZ6bxt2QyzESPfQwAyIPmeSWspE8fxXg91M=; b=BCRYhjheXnEUeISKgl1r1QINcE5GchNUBbuVt2yfNm+YVZAgSTFrpw9GuwF4brQekp zKV1hpfbFuOAQqRlStSIxFofSis4TNkbNqoVgVuB8Zq/UlpyhKHMo1Lv3iwIC5iO716I HaHDreP1CtbP5l3l7/o2OHFB27kKhz4OVp2w8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733075248; x=1733680048; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GYgi3gWsFZ6bxt2QyzESPfQwAyIPmeSWspE8fxXg91M=; b=DBk7xKXGJKUJ7pccHhAHeII9GEpPcQTYqls0xHdR6M5awM77iLJBtxou4aVxHt42m1 RZnGU5D2sm8IMIvtt4D2aVGWpVPfMvDh9yrgo8jLzklJnvpfn6Z6njK6aFPTkzt9IDoh bM4NLi18NBt4swbqqdJSB4pKwZYEnz4gKRVVYOVd7Mh6b0U8fyCJg1w+wvEU82KRkWkS 0EDSncRLD3j4fcGLmLE2jFL2sdywqRx9S46uEwpp04BWqQ884wuoDCpe+qZQskLErJ1i 3i/quu/hykAiL4Q9YYrk5rWulb4DxbTFA9xpV/DesJcEGe+Fo743QlaSCQyyxK3nKjQV nJGw== X-Gm-Message-State: AOJu0YwBgtwT0s1Au70LvDpC44Nij8u8JosPJx0ydkD5I/iONrMOxlBX jt3R9n3ZntZTfhPwfefl0zUoKt8kaGDWW42Uwhi99WChsgUZXzcejk+Fys8RAq/V4yvpbqp260q t X-Gm-Gg: ASbGncv1LHwwaMAUYpdE8P297e4lnHGob8dVCKXBnVpyu60ghFzP5pbDFIhgS6XVYx5 tegJssCzio1SkjIL4AaYGHM6tOTaXDHUOQserCYZBZ5YfQj6xW/oj1JkXNrRuTUK4JwYuatOc6y ezBzDTZ165a33ktsuOc2XPUlJ9e+LDyzeOS1WHjg3ABqVkWwBuEfpVt6OFH3mg9839FBX6dBayw wefBKALOz/MN83CWsFGcdTbdiGO5Q4aKeYrRJ032je3dvKo0eyUOeEPQRO1nI55VA7ZUBhUtKgx P4RsZMh8kqlWXv6+CddOTIGKHNNPIPF5lRwRl53uPZBvFHjQW/xLEYqAoZ1rz6UwiGMaeiNd/J0 Aa6M+qqfLYOuU9riP X-Google-Smtp-Source: AGHT+IFEnqfNEU+rcacBAMtddOncowvVosTxbTcww82LB9zIQkVF6gwcSPLsVyk8WzQcN3keRGes3Q== X-Received: by 2002:a17:906:2932:b0:aa5:396a:c9e8 with SMTP id a640c23a62f3a-aa580f27899mr1226207466b.23.1733075248682; Sun, 01 Dec 2024 09:47:28 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-82-54-94-193.retail.telecomitalia.it. [82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:28 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 06/18] arm64: dts: imx8mp: add anatop clocks Date: Sun, 1 Dec 2024 18:46:06 +0100 Message-ID: <20241201174639.742000-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clocks to anatop node. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index e0d3b8cba221..0b928e173f29 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -709,6 +709,8 @@ anatop: clock-controller@30360000 { compatible =3D "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg =3D <0x30360000 0x10000>; #clock-cells =3D <1>; + clocks =3D <&osc_32k>, <&osc_24m>; + clock-names =3D "osc_32k", "osc_24m"; }; =20 snvs: snvs@30370000 { --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5EE31D9A78 for ; Sun, 1 Dec 2024 17:47:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733075253; cv=none; b=HhSlRkAuXJ4NnRy/oX5gS162UiNo+PK/PoKvaXtUEf4ZUubA5h0uPluBDBNP3tiraDjLEt52W+BqEpqcfpML5raHS8av4SbOvy4llSmlOifE7K7eYxoLi9DS59OFyhovBZuFhmKfUNmHVxatMlPioVDU3AM49/AdUdCZbBv84G0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733075253; c=relaxed/simple; bh=7IXa6n6R8jf8EtYbD7eJtuKKeIWgvUP8tyBiBe9Mka4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=T/+YqZJUYj87dBUJMkLn2fEqYVubbgeC46rrUmifQdRVXgeLo6zm2b8IonubE5xDxd7E7xH6eZQYIm8btiVZ3FWJaV5huJaqZyouyr+Hs0LvOuaDclxftCUI9T+oEnHs9MEvVu+SiPhLj1jMDaYaERhrQiKIzZ8SyOTRY3LBKWQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=edFtZ6vX; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="edFtZ6vX" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-a9e8522445dso499945166b.1 for ; Sun, 01 Dec 2024 09:47:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1733075250; x=1733680050; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m3DWv5cRaHU4Io1NaeAcsTV4k9nDv9YZHhdkDqWmPyg=; b=edFtZ6vX93Sr8TDD7ZcOk0U2aldZ9rhmmqPDfxN0hLAJhc5rOR9zRGRPdnzhTe0vn1 +wrT+5V6l+cd4hj8k2QthuYiNdL9McHSkMf3NPSqBMmK1Jjlm3WKm6sjGaijeoTJUNWE K6Bjqb5Buv95Akv1QyW8iBuSaR2Hs6ePHiRVM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733075250; x=1733680050; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m3DWv5cRaHU4Io1NaeAcsTV4k9nDv9YZHhdkDqWmPyg=; b=wIv1NSrFdI99vnVgzEMvmpSkWUDm2JNhPo8cXW75W2/+AEQARYRZrLF9N8S+1xvgHC gueACwr411hQYGhQUP9HliNs2QyjSm/fOLgdgXkMVC1N1XamB7U6YUioAVcxrWPv7Iym m5lMe30m+GTeqUi6Gg4ANVNSRLBySs51XFpAB9zytwUFoN9gJ27KdiJ+C0oMV6Hd1sjw wL0Kb2z7akUSvHNQqi0xPbrXUNEJybSnKapBpZqR4A3e0i1We0dJM7ENxTe1HjkpXnVa 6r1PTc71CD2x7wDzKYk4uoQUJ77ZvsU5JuSlgxa1eawjNynTEHgG6xgtEBTAiPmHsejq U74Q== X-Gm-Message-State: AOJu0YymeUAWRMODfP4/H92vkGzihiSftiw9nBObac7eQ+6vb9m+IaTC GN//G2EQsLcCKjLtutMn+UEuze8kkLqZdz9ZbpgPjCPKSr5wlI5SaXZ+zNqb+XokrmNYYPgBAmK B X-Gm-Gg: ASbGnct+5qZMa57EcBSZU7UEpTBA0evfjNm0/vUXALRHdCEHtjDRGAlsSUERC7mFNdp Qm6Anp4gtCeE7/E3eg7DMaD7PAgLhnLpVZcqS5Uxwn28FMm9QkCPsinRRa7DAoRbOBzreFPBFj6 0WsHf9idsINNAZg39hgfXkkP6MrDQNUxrC3Mx9I2oDnjFG2bShSqBIWjplx5cB7hYyHl5xnHTlx VCZAdMw3OpdEBnS1pvRM0w02g4QJ8CBO0TDBE05I8l3KdBt/Dwyn6r744rX5ZmzDADUVKfmT+30 3E8w4y0l10TZyCUocsCaR6AkYKBm9FHK1zRchd5Dudy7dL3RlCmU+u+LO5lP7RkB9vq8wD3j66r YarfRTlFMgtkZgGOK X-Google-Smtp-Source: AGHT+IGjTr544po85HL/yFGlp7Fz9SND5Mszl3n0nyOzsFi4lUmL2IW6mDDVfOELB47d4l21pa4qgw== X-Received: by 2002:a17:907:3f9f:b0:a9e:c267:78c5 with SMTP id a640c23a62f3a-aa58108aa97mr1582174766b.55.1733075250065; Sun, 01 Dec 2024 09:47:30 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-82-54-94-193.retail.telecomitalia.it. [82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:29 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 07/18] arm64: dts: imx8mq: add anatop clocks Date: Sun, 1 Dec 2024 18:46:07 +0100 Message-ID: <20241201174639.742000-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clocks to anatop node. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mq.dtsi index d51de8d899b2..1d1424a136f0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -817,6 +817,8 @@ anatop: clock-controller@30360000 { reg =3D <0x30360000 0x10000>; interrupts =3D ; #clock-cells =3D <1>; + clocks =3D <&ckil>, <&osc_25m>, <&osc_27m>; + clock-names =3D "ckil", "osc_25m", "osc_27m"; }; =20 snvs: snvs@30370000 { --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75FE71DACAA for ; Sun, 1 Dec 2024 17:47:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733075255; cv=none; b=nBZp6O2hgi//wathA5z+09IVaQCiKX3VyuT5FnFtNQgW8Xw7VLNpEk6H+QxyjwazO3VH+veyqqGEF/IUxYhv2KlPEVKjNlyioai9sqlrlvD9Llrc69BnyKyMk/h4q4CuaS+GtdoYU71BOBf6I9/nD/i2OdDCfyxEQ3C1V/4gl9E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733075255; c=relaxed/simple; bh=Nwn3EKKlmGoN86TIQsDCmmh1hRjCTmWLWbVqZEcZ4hA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RL2dNPgfvfOPNWG3imS3+9EMOUOWc0+yS2gi3L/KLjKqIyNOPZvkfVKx5/aUqKS3dfQMXZn9VaPHUbGgcqqEXY9Zl9Kh73z5PQFLBz+aaamyXQ0zEQo1BrBdIwF1C7127df/T9NG6/o2MR8h1Idl8wN3yOREg4ES4RVgyIc7Xwk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=MxNw785V; arc=none smtp.client-ip=209.85.208.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="MxNw785V" Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-5d0cd8a0e91so1851098a12.3 for ; Sun, 01 Dec 2024 09:47:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1733075251; x=1733680051; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6vpGtyZ0NLJqQmHQubdh3p8VNW8Gv2lh2Riw5LPZEts=; b=MxNw785VNqSy0qe6fFTaBpCQzlra3GjmtJuJe5mLY1Be8IAGVaeWDpuVYVtGsMwgHj AE4hUjRPRc/XGUJQNiYpYh1upCirOeQMIcEp/1qsdyqP+l/AkOfFewPPGjSDDR20LRw5 LJKE1jQulOOG/Qpx0whRkmzDLt5BQfAZ5ZqHE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733075251; x=1733680051; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6vpGtyZ0NLJqQmHQubdh3p8VNW8Gv2lh2Riw5LPZEts=; b=SjfBk8WRH43NOUMDPocfIx92zttiq3CFwhzzetXqQXSuYuAlvN4wjuUfdyBTcYKwgh vpGGKVowolj1LKUnZF3FGZs7e6NoGHf1Wq0O4xgqVeeziT+Ae1Kz1YxJI+AFp9/tUMi0 ZyYX8P/67N8IrrCKUNiE+X4LyTtCm6zxTj+gQKoXF1Mwccbg1GTCPsM7PGT/Mk9nWjqE FapAjoAjC0+dSd9SfkuytaSSfXLeVqdVLK3wHSl4BWwEZv77y1qPWNwizEUFUXqwqDeQ dJw/IY6dCfb+UpE5A4N6iU3OKSmF7ePMZ88pcQ1iVSe8URnGtdGU3lvFxRsP31smOAhF qd4A== X-Gm-Message-State: AOJu0Yw+GtVvY4p2fiovl2OyjKQ06e5GMT7qkrHY3obtAQAijLxWbd/I gewq04CYBNaaEjQMUzDw0KXLp2BtCj9uRHbAKy52jXtFWG46I2JnM5f3QMENLln6dwOLOvIPyYS j X-Gm-Gg: ASbGncsxrgJ5sxqdbHHkCUMbnLPGibnTfIV/QjrUBRLbQQZ7fGO5s799eKE8ZJKxKMX RKH4FoBZvf71/N/gprQ9HegBzecyJAgrvU7z1Iu8DgpVPiIodvUlKt4bJ411mPMOx1JdLN+Tx2i Xi9QH0SairS4T6YX+zrPeej444731tS5KWZvMsSXb+e5mnGjIjqHeyVyMOAwegN7/FCkNA4Yo7t bBbqRL7hi0wTPotFWU8rxTy2fX+EE/CJD1C/1/oCf3ttdNanJiTBSoQIF2cjeECX6+4xtyxzN45 OiujnXEv7/0at4/nu8XcK64wRWOEzDBQmGEr2XPY6LQJvJdAjafd6Lg4wlWREFS/sa5rzhonYGO pCdr+mNkihLcS5Btt X-Google-Smtp-Source: AGHT+IH6kOma2DObSZmZth2XtVd8Da7MknZR6nKDqDOJ+2Riopq+leVAbUkamxADzB83IjOAlOgwqg== X-Received: by 2002:a17:906:23ea:b0:a9a:10c9:f4b8 with SMTP id a640c23a62f3a-aa58109dc28mr1664550866b.61.1733075251568; Sun, 01 Dec 2024 09:47:31 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-82-54-94-193.retail.telecomitalia.it. [82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:31 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v4 08/18] dt-bindings: clock: imx8mm: add binding definitions for anatop Date: Sun, 1 Dec 2024 18:46:08 +0100 Message-ID: <20241201174639.742000-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the bindings definitions for the anatop node. The patch is preparatory for future developments. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) include/dt-bindings/clock/imx8mm-clock.h | 66 ++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings= /clock/imx8mm-clock.h index 102d8a6cdb55..1962b0a1e732 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -287,4 +287,70 @@ =20 #define IMX8MM_CLK_END 258 =20 +#define IMX8MM_ANATOP_CLK_DUMMY 0 +#define IMX8MM_ANATOP_CLK_32K 1 +#define IMX8MM_ANATOP_CLK_24M 2 +#define IMX8MM_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MM_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MM_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MM_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MM_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MM_ANATOP_VPU_PLL_REF_SEL 8 +#define IMX8MM_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MM_ANATOP_SYS_PLL3_REF_SEL 10 +#define IMX8MM_ANATOP_AUDIO_PLL1 11 +#define IMX8MM_ANATOP_AUDIO_PLL2 12 +#define IMX8MM_ANATOP_VIDEO_PLL 13 +#define IMX8MM_ANATOP_DRAM_PLL 14 +#define IMX8MM_ANATOP_GPU_PLL 15 +#define IMX8MM_ANATOP_VPU_PLL 16 +#define IMX8MM_ANATOP_ARM_PLL 17 +#define IMX8MM_ANATOP_SYS_PLL1 18 +#define IMX8MM_ANATOP_SYS_PLL2 19 +#define IMX8MM_ANATOP_SYS_PLL3 20 +#define IMX8MM_ANATOP_AUDIO_PLL1_BYPASS 21 +#define IMX8MM_ANATOP_AUDIO_PLL2_BYPASS 22 +#define IMX8MM_ANATOP_VIDEO_PLL_BYPASS 23 +#define IMX8MM_ANATOP_DRAM_PLL_BYPASS 24 +#define IMX8MM_ANATOP_GPU_PLL_BYPASS 25 +#define IMX8MM_ANATOP_VPU_PLL_BYPASS 26 +#define IMX8MM_ANATOP_ARM_PLL_BYPASS 27 +#define IMX8MM_ANATOP_SYS_PLL3_BYPASS 28 +#define IMX8MM_ANATOP_AUDIO_PLL1_OUT 29 +#define IMX8MM_ANATOP_AUDIO_PLL2_OUT 30 +#define IMX8MM_ANATOP_VIDEO_PLL_OUT 31 +#define IMX8MM_ANATOP_DRAM_PLL_OUT 32 +#define IMX8MM_ANATOP_GPU_PLL_OUT 33 +#define IMX8MM_ANATOP_VPU_PLL_OUT 34 +#define IMX8MM_ANATOP_ARM_PLL_OUT 35 +#define IMX8MM_ANATOP_SYS_PLL3_OUT 36 +#define IMX8MM_ANATOP_SYS_PLL1_OUT 37 +#define IMX8MM_ANATOP_SYS_PLL1_40M 38 +#define IMX8MM_ANATOP_SYS_PLL1_80M 39 +#define IMX8MM_ANATOP_SYS_PLL1_100M 40 +#define IMX8MM_ANATOP_SYS_PLL1_133M 41 +#define IMX8MM_ANATOP_SYS_PLL1_160M 42 +#define IMX8MM_ANATOP_SYS_PLL1_200M 43 +#define IMX8MM_ANATOP_SYS_PLL1_266M 44 +#define IMX8MM_ANATOP_SYS_PLL1_400M 45 +#define IMX8MM_ANATOP_SYS_PLL1_800M 46 +#define IMX8MM_ANATOP_SYS_PLL2_OUT 47 +#define IMX8MM_ANATOP_SYS_PLL2_50M 48 +#define IMX8MM_ANATOP_SYS_PLL2_100M 49 +#define IMX8MM_ANATOP_SYS_PLL2_125M 50 +#define IMX8MM_ANATOP_SYS_PLL2_166M 51 +#define IMX8MM_ANATOP_SYS_PLL2_200M 52 +#define IMX8MM_ANATOP_SYS_PLL2_250M 53 +#define IMX8MM_ANATOP_SYS_PLL2_333M 54 +#define IMX8MM_ANATOP_SYS_PLL2_500M 55 +#define IMX8MM_ANATOP_SYS_PLL2_1000M 56 +#define IMX8MM_ANATOP_CLK_CLKOUT1_SEL 57 +#define IMX8MM_ANATOP_CLK_CLKOUT1_DIV 58 +#define IMX8MM_ANATOP_CLK_CLKOUT1 59 +#define IMX8MM_ANATOP_CLK_CLKOUT2_SEL 60 +#define IMX8MM_ANATOP_CLK_CLKOUT2_DIV 61 +#define IMX8MM_ANATOP_CLK_CLKOUT2 62 + +#define IMX8MM_ANATOP_CLK_END 63 + #endif --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D03D41DBB13 for ; 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[82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:32 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v4 09/18] dt-bindings: clock: imx8mn: add binding definitions for anatop Date: Sun, 1 Dec 2024 18:46:09 +0100 Message-ID: <20241201174639.742000-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the bindings definitions for the anatop node. The patch is preparatory for future developments. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) include/dt-bindings/clock/imx8mn-clock.h | 67 ++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings= /clock/imx8mn-clock.h index 04809edab33c..732ff87a16c2 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -267,4 +267,71 @@ =20 #define IMX8MN_CLK_END 235 =20 +#define IMX8MN_ANATOP_CLK_DUMMY 0 +#define IMX8MN_ANATOP_CLK_32K 1 +#define IMX8MN_ANATOP_CLK_24M 2 +#define IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MN_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MN_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MN_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL 8 +#define IMX8MN_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MN_ANATOP_SYS_PLL3_REF_SEL 10 +#define IMX8MN_ANATOP_AUDIO_PLL1 11 +#define IMX8MN_ANATOP_AUDIO_PLL2 12 +#define IMX8MN_ANATOP_VIDEO_PLL 13 +#define IMX8MN_ANATOP_DRAM_PLL 14 +#define IMX8MN_ANATOP_GPU_PLL 15 +#define IMX8MN_ANATOP_M7_ALT_PLL 16 +#define IMX8MN_ANATOP_ARM_PLL 17 +#define IMX8MN_ANATOP_SYS_PLL1 18 +#define IMX8MN_ANATOP_SYS_PLL2 19 +#define IMX8MN_ANATOP_SYS_PLL3 20 +#define IMX8MN_ANATOP_AUDIO_PLL1_BYPASS 21 +#define IMX8MN_ANATOP_AUDIO_PLL2_BYPASS 22 +#define IMX8MN_ANATOP_VIDEO_PLL_BYPASS 23 +#define IMX8MN_ANATOP_DRAM_PLL_BYPASS 24 +#define IMX8MN_ANATOP_GPU_PLL_BYPASS 25 +#define IMX8MN_ANATOP_M7_ALT_PLL_BYPASS 26 +#define IMX8MN_ANATOP_ARM_PLL_BYPASS 27 +#define IMX8MN_ANATOP_SYS_PLL3_BYPASS 28 +#define IMX8MN_ANATOP_AUDIO_PLL1_OUT 29 +#define IMX8MN_ANATOP_AUDIO_PLL2_OUT 30 +#define IMX8MN_ANATOP_VIDEO_PLL_OUT 31 +#define IMX8MN_ANATOP_DRAM_PLL_OUT 32 +#define IMX8MN_ANATOP_GPU_PLL_OUT 33 +#define IMX8MN_ANATOP_M7_ALT_PLL_OUT 34 +#define IMX8MN_ANATOP_ARM_PLL_OUT 35 +#define IMX8MN_ANATOP_SYS_PLL3_OUT 36 +#define IMX8MN_ANATOP_SYS_PLL1_OUT 37 +#define IMX8MN_ANATOP_SYS_PLL1_40M 38 +#define IMX8MN_ANATOP_SYS_PLL1_80M 39 +#define IMX8MN_ANATOP_SYS_PLL1_100M 40 +#define IMX8MN_ANATOP_SYS_PLL1_133M 41 +#define IMX8MN_ANATOP_SYS_PLL1_160M 42 +#define IMX8MN_ANATOP_SYS_PLL1_200M 43 +#define IMX8MN_ANATOP_SYS_PLL1_266M 44 +#define IMX8MN_ANATOP_SYS_PLL1_400M 45 +#define IMX8MN_ANATOP_SYS_PLL1_800M 46 +#define IMX8MN_ANATOP_SYS_PLL2_OUT 47 +#define IMX8MN_ANATOP_SYS_PLL2_50M 48 +#define IMX8MN_ANATOP_SYS_PLL2_100M 49 +#define IMX8MN_ANATOP_SYS_PLL2_125M 50 +#define IMX8MN_ANATOP_SYS_PLL2_166M 51 +#define IMX8MN_ANATOP_SYS_PLL2_200M 52 +#define IMX8MN_ANATOP_SYS_PLL2_250M 53 +#define IMX8MN_ANATOP_SYS_PLL2_333M 54 +#define IMX8MN_ANATOP_SYS_PLL2_500M 55 +#define IMX8MN_ANATOP_SYS_PLL2_1000M 56 + +#define IMX8MN_ANATOP_CLK_CLKOUT1_SEL 57 +#define IMX8MN_ANATOP_CLK_CLKOUT1_DIV 58 +#define IMX8MN_ANATOP_CLK_CLKOUT1 59 +#define IMX8MN_ANATOP_CLK_CLKOUT2_SEL 60 +#define IMX8MN_ANATOP_CLK_CLKOUT2_DIV 61 +#define IMX8MN_ANATOP_CLK_CLKOUT2 62 + +#define IMX8MN_ANATOP_CLK_END 63 + #endif --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B8C01DD526 for ; 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[82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:34 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v4 10/18] dt-bindings: clock: imx8mp: add binding definitions for anatop Date: Sun, 1 Dec 2024 18:46:10 +0100 Message-ID: <20241201174639.742000-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the bindings definitions for the anatop node. The patch is preparatory for future developments. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) include/dt-bindings/clock/imx8mp-clock.h | 70 ++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings= /clock/imx8mp-clock.h index 0601df6c8d38..39e4ad470927 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -401,4 +401,74 @@ =20 #define IMX8MP_CLK_AUDIOMIX_END 59 =20 +#define IMX8MP_ANATOP_CLK_DUMMY 0 +#define IMX8MP_ANATOP_CLK_24M 1 +#define IMX8MP_ANATOP_CLK_32K 2 +#define IMX8MP_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MP_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MP_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MP_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MP_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MP_ANATOP_VPU_PLL_REF_SEL 8 +#define IMX8MP_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MP_ANATOP_SYS_PLL1_REF_SEL 10 +#define IMX8MP_ANATOP_SYS_PLL2_REF_SEL 11 +#define IMX8MP_ANATOP_SYS_PLL3_REF_SEL 12 +#define IMX8MP_ANATOP_AUDIO_PLL1 13 +#define IMX8MP_ANATOP_AUDIO_PLL2 14 +#define IMX8MP_ANATOP_VIDEO_PLL 15 +#define IMX8MP_ANATOP_DRAM_PLL 16 +#define IMX8MP_ANATOP_GPU_PLL 17 +#define IMX8MP_ANATOP_VPU_PLL 18 +#define IMX8MP_ANATOP_ARM_PLL 19 +#define IMX8MP_ANATOP_SYS_PLL1 20 +#define IMX8MP_ANATOP_SYS_PLL2 21 +#define IMX8MP_ANATOP_SYS_PLL3 22 +#define IMX8MP_ANATOP_AUDIO_PLL1_BYPASS 23 +#define IMX8MP_ANATOP_AUDIO_PLL2_BYPASS 24 +#define IMX8MP_ANATOP_VIDEO_PLL_BYPASS 25 +#define IMX8MP_ANATOP_DRAM_PLL_BYPASS 26 +#define IMX8MP_ANATOP_GPU_PLL_BYPASS 27 +#define IMX8MP_ANATOP_VPU_PLL_BYPASS 28 +#define IMX8MP_ANATOP_ARM_PLL_BYPASS 29 +#define IMX8MP_ANATOP_SYS_PLL1_BYPASS 30 +#define IMX8MP_ANATOP_SYS_PLL2_BYPASS 31 +#define IMX8MP_ANATOP_SYS_PLL3_BYPASS 32 +#define IMX8MP_ANATOP_AUDIO_PLL1_OUT 33 +#define IMX8MP_ANATOP_AUDIO_PLL2_OUT 34 +#define IMX8MP_ANATOP_VIDEO_PLL_OUT 35 +#define IMX8MP_ANATOP_DRAM_PLL_OUT 36 +#define IMX8MP_ANATOP_GPU_PLL_OUT 37 +#define IMX8MP_ANATOP_VPU_PLL_OUT 38 +#define IMX8MP_ANATOP_ARM_PLL_OUT 39 +#define IMX8MP_ANATOP_SYS_PLL3_OUT 40 +#define IMX8MP_ANATOP_SYS_PLL1_OUT 41 +#define IMX8MP_ANATOP_SYS_PLL1_40M 42 +#define IMX8MP_ANATOP_SYS_PLL1_80M 43 +#define IMX8MP_ANATOP_SYS_PLL1_100M 44 +#define IMX8MP_ANATOP_SYS_PLL1_133M 45 +#define IMX8MP_ANATOP_SYS_PLL1_160M 46 +#define IMX8MP_ANATOP_SYS_PLL1_200M 47 +#define IMX8MP_ANATOP_SYS_PLL1_266M 48 +#define IMX8MP_ANATOP_SYS_PLL1_400M 49 +#define IMX8MP_ANATOP_SYS_PLL1_800M 50 +#define IMX8MP_ANATOP_SYS_PLL2_OUT 51 +#define IMX8MP_ANATOP_SYS_PLL2_50M 52 +#define IMX8MP_ANATOP_SYS_PLL2_100M 53 +#define IMX8MP_ANATOP_SYS_PLL2_125M 54 +#define IMX8MP_ANATOP_SYS_PLL2_166M 55 +#define IMX8MP_ANATOP_SYS_PLL2_200M 56 +#define IMX8MP_ANATOP_SYS_PLL2_250M 57 +#define IMX8MP_ANATOP_SYS_PLL2_333M 58 +#define IMX8MP_ANATOP_SYS_PLL2_500M 59 +#define IMX8MP_ANATOP_SYS_PLL2_1000M 60 +#define IMX8MP_ANATOP_CLK_CLKOUT1_SEL 61 +#define IMX8MP_ANATOP_CLK_CLKOUT1_DIV 62 +#define IMX8MP_ANATOP_CLK_CLKOUT1 63 +#define IMX8MP_ANATOP_CLK_CLKOUT2_SEL 64 +#define IMX8MP_ANATOP_CLK_CLKOUT2_DIV 65 +#define IMX8MP_ANATOP_CLK_CLKOUT2 66 + +#define IMX8MP_ANATOP_CLK_END 67 + #endif --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60FB31DDC0F for ; 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[82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:36 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v4 11/18] clk: imx: add hw API imx8m_anatop_get_clk_hw Date: Sun, 1 Dec 2024 18:46:11 +0100 Message-ID: <20241201174639.742000-12-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Get the hw of a clock registered by the anatop module. This function is preparatory for future developments. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) drivers/clk/imx/clk.c | 26 ++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 6 ++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index df83bd939492..8a8473a77b7c 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -128,6 +128,32 @@ struct clk_hw *imx_get_clk_hw_by_name(struct device_no= de *np, const char *name) } EXPORT_SYMBOL_GPL(imx_get_clk_hw_by_name); =20 +#if defined(CONFIG_CLK_IMX8MM) || defined(CONFIG_CLK_IMX8MN) || \ + defined(CONFIG_CLK_IMX8MP) || defined(CONFIG_CLK_IMX8MQ) +struct clk_hw *imx8m_anatop_get_clk_hw(int id) +{ +#if defined(CONFIG_CLK_IMX8MQ) + const char *compatible =3D "fsl,imx8mq-anatop"; +#else + const char *compatible =3D "fsl,imx8mm-anatop"; +#endif + struct device_node *np; + struct of_phandle_args args; + struct clk_hw *hw; + + np =3D of_find_compatible_node(NULL, NULL, compatible); + args.np =3D np; + args.args_count =3D 1; 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[82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:38 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v4 12/18] clk: imx: add support for i.MX8MN anatop clock driver Date: Sun, 1 Dec 2024 18:46:12 +0100 Message-ID: <20241201174639.742000-13-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root. By doing so, we also simplify the CCM driver code. The changes are backward compatible. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-imx8mn-anatop.c | 281 ++++++++++++++++++++++++++++ drivers/clk/imx/clk-imx8mn.c | 175 ++++++++--------- 3 files changed, 355 insertions(+), 103 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8mn-anatop.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 03f2b2a1ab63..f0f1d01c68f8 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -26,7 +26,7 @@ mxc-clk-objs +=3D clk-gpr-mux.o obj-$(CONFIG_MXC_CLK) +=3D mxc-clk.o =20 obj-$(CONFIG_CLK_IMX8MM) +=3D clk-imx8mm.o -obj-$(CONFIG_CLK_IMX8MN) +=3D clk-imx8mn.o +obj-$(CONFIG_CLK_IMX8MN) +=3D clk-imx8mn-anatop.o clk-imx8mn.o obj-$(CONFIG_CLK_IMX8MP) +=3D clk-imx8mp.o clk-imx8mp-audiomix.o obj-$(CONFIG_CLK_IMX8MQ) +=3D clk-imx8mq.o =20 diff --git a/drivers/clk/imx/clk-imx8mn-anatop.c b/drivers/clk/imx/clk-imx8= mn-anatop.c new file mode 100644 index 000000000000..f02e4d5114a5 --- /dev/null +++ b/drivers/clk/imx/clk-imx8mn-anatop.c @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * clk-imx8mn-anatop.c - NXP i.MX8MN anatop clock driver + * + * Copyright (c) 2022 Dario Binacchi + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +static const char * const pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy"= , "dummy", }; +static const char * const audio_pll1_bypass_sels[] =3D {"audio_pll1", "aud= io_pll1_ref_sel", }; +static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; +static const char * const video_pll_bypass_sels[] =3D {"video_pll", "video= _pll_ref_sel", }; +static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; +static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; +static const char * const m7_alt_pll_bypass_sels[] =3D {"m7_alt_pll", "m7_= alt_pll_ref_sel", }; +static const char * const arm_pll_bypass_sels[] =3D {"arm_pll", "arm_pll_r= ef_sel", }; +static const char * const sys_pll3_bypass_sels[] =3D {"sys_pll3", "sys_pll= 3_ref_sel", }; +static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", + "dummy", "dummy", "gpu_pll_out", "dummy", + "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", + "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; + +static struct clk_hw_onecell_data *clk_hw_data; +static struct clk_hw **hws; + +static int imx8mn_anatop_clocks_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(dev, "failed to get base address\n"); + return PTR_ERR(base); + } + + clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, + IMX8MN_ANATOP_CLK_END), + GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num =3D IMX8MN_ANATOP_CLK_END; + hws =3D clk_hw_data->hws; + + hws[IMX8MN_ANATOP_CLK_DUMMY] =3D imx_clk_hw_fixed("dummy", 0); + hws[IMX8MN_ANATOP_CLK_32K] =3D imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MN_ANATOP_CLK_24M] =3D imx_get_clk_hw_by_name(np, "osc_24m"); + + hws[IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL] =3D + imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL] =3D + imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_VIDEO_PLL_REF_SEL] =3D + imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_DRAM_PLL_REF_SEL] =3D + imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_GPU_PLL_REF_SEL] =3D + imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL] =3D + imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_ARM_PLL_REF_SEL] =3D + imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_SYS_PLL3_REF_SEL] =3D + imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + hws[IMX8MN_ANATOP_AUDIO_PLL1] =3D + imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", + base, &imx_1443x_pll); + hws[IMX8MN_ANATOP_AUDIO_PLL2] =3D + imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", + base + 0x14, &imx_1443x_pll); + hws[IMX8MN_ANATOP_VIDEO_PLL] =3D + imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", + base + 0x28, &imx_1443x_pll); + hws[IMX8MN_ANATOP_DRAM_PLL] =3D + imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, + &imx_1443x_dram_pll); + hws[IMX8MN_ANATOP_GPU_PLL] =3D + imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, + &imx_1416x_pll); + hws[IMX8MN_ANATOP_M7_ALT_PLL] =3D + imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", + base + 0x74, &imx_1416x_pll); + hws[IMX8MN_ANATOP_ARM_PLL] =3D + imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, + &imx_1416x_pll); + hws[IMX8MN_ANATOP_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000); + hws[IMX8MN_ANATOP_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000); + hws[IMX8MN_ANATOP_SYS_PLL3] =3D + imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, + &imx_1416x_pll); + + /* PLL bypass out */ + hws[IMX8MN_ANATOP_AUDIO_PLL1_BYPASS] =3D + imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, + audio_pll1_bypass_sels, + ARRAY_SIZE(audio_pll1_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_AUDIO_PLL2_BYPASS] =3D + imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, + audio_pll2_bypass_sels, + ARRAY_SIZE(audio_pll2_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_VIDEO_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, + video_pll_bypass_sels, + ARRAY_SIZE(video_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_DRAM_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, + dram_pll_bypass_sels, + ARRAY_SIZE(dram_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_GPU_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, + gpu_pll_bypass_sels, + ARRAY_SIZE(gpu_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_M7_ALT_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, + m7_alt_pll_bypass_sels, + ARRAY_SIZE(m7_alt_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_ARM_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, + arm_pll_bypass_sels, + ARRAY_SIZE(arm_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_SYS_PLL3_BYPASS] =3D + imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, + sys_pll3_bypass_sels, + ARRAY_SIZE(sys_pll3_bypass_sels), + CLK_SET_RATE_PARENT); + + /* PLL out gate */ + hws[IMX8MN_ANATOP_AUDIO_PLL1_OUT] =3D + imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", + base, 13); + hws[IMX8MN_ANATOP_AUDIO_PLL2_OUT] =3D + imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", + base + 0x14, 13); + hws[IMX8MN_ANATOP_VIDEO_PLL_OUT] =3D + imx_clk_hw_gate("video_pll_out", "video_pll_bypass", + base + 0x28, 13); + hws[IMX8MN_ANATOP_DRAM_PLL_OUT] =3D + imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", + base + 0x50, 13); + hws[IMX8MN_ANATOP_GPU_PLL_OUT] =3D + imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", + base + 0x64, 11); + hws[IMX8MN_ANATOP_M7_ALT_PLL_OUT] =3D + imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", + base + 0x74, 11); + hws[IMX8MN_ANATOP_ARM_PLL_OUT] =3D + imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", + base + 0x84, 11); + hws[IMX8MN_ANATOP_SYS_PLL3_OUT] =3D + imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", + base + 0x114, 11); + + /* SYS PLL1 fixed output */ + hws[IMX8MN_ANATOP_SYS_PLL1_OUT] =3D + imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11); + hws[IMX8MN_ANATOP_SYS_PLL1_40M] =3D + imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + hws[IMX8MN_ANATOP_SYS_PLL1_80M] =3D + imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + hws[IMX8MN_ANATOP_SYS_PLL1_100M] =3D + imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + hws[IMX8MN_ANATOP_SYS_PLL1_133M] =3D + imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + hws[IMX8MN_ANATOP_SYS_PLL1_160M] =3D + imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + hws[IMX8MN_ANATOP_SYS_PLL1_200M] =3D + imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + hws[IMX8MN_ANATOP_SYS_PLL1_266M] =3D + imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + hws[IMX8MN_ANATOP_SYS_PLL1_400M] =3D + imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); + hws[IMX8MN_ANATOP_SYS_PLL1_800M] =3D + imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + + /* SYS PLL2 fixed output */ + hws[IMX8MN_ANATOP_SYS_PLL2_OUT] =3D + imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); + hws[IMX8MN_ANATOP_SYS_PLL2_50M] =3D + imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + hws[IMX8MN_ANATOP_SYS_PLL2_100M] =3D + imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + hws[IMX8MN_ANATOP_SYS_PLL2_125M] =3D + imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + hws[IMX8MN_ANATOP_SYS_PLL2_166M] =3D + imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + hws[IMX8MN_ANATOP_SYS_PLL2_200M] =3D + imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + hws[IMX8MN_ANATOP_SYS_PLL2_250M] =3D + imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + hws[IMX8MN_ANATOP_SYS_PLL2_333M] =3D + imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + hws[IMX8MN_ANATOP_SYS_PLL2_500M] =3D + imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); + hws[IMX8MN_ANATOP_SYS_PLL2_1000M] =3D + imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); + + hws[IMX8MN_ANATOP_CLK_CLKOUT1_SEL] =3D + imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MN_ANATOP_CLK_CLKOUT1_DIV] =3D + imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, + 0, 4); + hws[IMX8MN_ANATOP_CLK_CLKOUT1] =3D + imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); + hws[IMX8MN_ANATOP_CLK_CLKOUT2_SEL] + =3D imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MN_ANATOP_CLK_CLKOUT2_DIV] =3D + imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, + 16, 4); + hws[IMX8MN_ANATOP_CLK_CLKOUT2] =3D + imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); + + imx_check_clk_hws(hws, IMX8MN_ANATOP_CLK_END); + + ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + if (ret < 0) { + imx_unregister_hw_clocks(hws, IMX8MN_ANATOP_CLK_END); + return dev_err_probe(dev, ret, + "failed to register anatop clock provider\n"); + } + + dev_info(dev, "NXP i.MX8MN anatop clock driver probed\n"); + return 0; +} + +static const struct of_device_id imx8mn_anatop_clk_of_match[] =3D { + { .compatible =3D "fsl,imx8mn-anatop" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx8mn_anatop_clk_of_match); + +static struct platform_driver imx8mn_anatop_clk_driver =3D { + .probe =3D imx8mn_anatop_clocks_probe, + .driver =3D { + .name =3D "imx8mn-anatop", + /* + * Disable bind attributes: clocks are not removed and + * reloading the driver will crash or break devices. + */ + .suppress_bind_attrs =3D true, + .of_match_table =3D imx8mn_anatop_clk_of_match, + }, +}; + +module_platform_driver(imx8mn_anatop_clk_driver); + +MODULE_AUTHOR("Dario Binacchi "); +MODULE_DESCRIPTION("NXP i.MX8MN anatop clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index ab77e148e70c..588cebce6c9d 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -24,16 +24,6 @@ static u32 share_count_disp; static u32 share_count_pdm; static u32 share_count_nand; =20 -static const char * const pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy"= , "dummy", }; -static const char * const audio_pll1_bypass_sels[] =3D {"audio_pll1", "aud= io_pll1_ref_sel", }; -static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; -static const char * const video_pll_bypass_sels[] =3D {"video_pll", "video= _pll_ref_sel", }; -static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; -static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; -static const char * const m7_alt_pll_bypass_sels[] =3D {"m7_alt_pll", "m7_= alt_pll_ref_sel", }; -static const char * const arm_pll_bypass_sels[] =3D {"arm_pll", "arm_pll_r= ef_sel", }; -static const char * const sys_pll3_bypass_sels[] =3D {"sys_pll3", "sys_pll= 3_ref_sel", }; - static const char * const imx8mn_a53_sels[] =3D {"osc_24m", "arm_pll_out",= "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; @@ -308,11 +298,6 @@ static const char * const imx8mn_clko2_sels[] =3D {"os= c_24m", "sys_pll2_200m", "sy "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", }; =20 -static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", - "dummy", "dummy", "gpu_pll_out", "dummy", - "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", - "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; - static struct clk_hw_onecell_data *clk_hw_data; static struct clk_hw **hws; =20 @@ -323,6 +308,10 @@ static int imx8mn_clocks_probe(struct platform_device = *pdev) void __iomem *base; int ret; =20 + base =3D devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(base))) + return PTR_ERR(base); + clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MN_CLK_END), GFP_KERNEL); if (WARN_ON(!clk_hw_data)) @@ -331,99 +320,84 @@ static int imx8mn_clocks_probe(struct platform_device= *pdev) clk_hw_data->num =3D IMX8MN_CLK_END; hws =3D clk_hw_data->hws; =20 - hws[IMX8MN_CLK_DUMMY] =3D imx_clk_hw_fixed("dummy", 0); - hws[IMX8MN_CLK_24M] =3D imx_get_clk_hw_by_name(np, "osc_24m"); - hws[IMX8MN_CLK_32K] =3D imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MN_CLK_DUMMY] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_CLK_DUMMY= ); + hws[IMX8MN_CLK_24M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_CLK_24M); + hws[IMX8MN_CLK_32K] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_CLK_32K); hws[IMX8MN_CLK_EXT1] =3D imx_get_clk_hw_by_name(np, "clk_ext1"); hws[IMX8MN_CLK_EXT2] =3D imx_get_clk_hw_by_name(np, "clk_ext2"); hws[IMX8MN_CLK_EXT3] =3D imx_get_clk_hw_by_name(np, "clk_ext3"); hws[IMX8MN_CLK_EXT4] =3D imx_get_clk_hw_by_name(np, "clk_ext4"); =20 - np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); - base =3D devm_of_iomap(dev, np, 0, NULL); - of_node_put(np); - if (WARN_ON(IS_ERR(base))) { - ret =3D PTR_ERR(base); - goto unregister_hws; - } - - hws[IMX8MN_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", b= ase + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", b= ase + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", bas= e + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", base = + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", base + = 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_M7_ALT_PLL_REF_SEL] =3D imx_clk_hw_mux("m7_alt_pll_ref_sel", b= ase + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", base + = 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", base = + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - - hws[IMX8MN_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); - hws[IMX8MN_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MN_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", base + 0x28, &imx_1443x_pll); - hws[IMX8MN_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); - hws[IMX8MN_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); - hws[IMX8MN_M7_ALT_PLL] =3D imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_r= ef_sel", base + 0x74, &imx_1416x_pll); - hws[IMX8MN_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = base + 0x84, &imx_1416x_pll); - hws[IMX8MN_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000); - hws[IMX8MN_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000); - hws[IMX8MN_SYS_PLL3] =3D imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel= ", base + 0x114, &imx_1416x_pll); + hws[IMX8MN_AUDIO_PLL1_REF_SEL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_= AUDIO_PLL1_REF_SEL); + hws[IMX8MN_AUDIO_PLL2_REF_SEL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_= AUDIO_PLL2_REF_SEL); + hws[IMX8MN_VIDEO_PLL_REF_SEL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_V= IDEO_PLL_REF_SEL); + hws[IMX8MN_DRAM_PLL_REF_SEL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_DR= AM_PLL_REF_SEL); + hws[IMX8MN_GPU_PLL_REF_SEL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_GPU= _PLL_REF_SEL); + hws[IMX8MN_M7_ALT_PLL_REF_SEL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_= M7_ALT_PLL_REF_SEL); + hws[IMX8MN_ARM_PLL_REF_SEL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_ARM= _PLL_REF_SEL); + hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SY= S_PLL3_REF_SEL); + + hws[IMX8MN_AUDIO_PLL1] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_AUDIO_PL= L1); + hws[IMX8MN_AUDIO_PLL2] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_AUDIO_PL= L2); + hws[IMX8MN_VIDEO_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_VIDEO_PLL= ); + hws[IMX8MN_DRAM_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_DRAM_PLL); + hws[IMX8MN_GPU_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_GPU_PLL); + hws[IMX8MN_M7_ALT_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_M7_ALT_P= LL); + hws[IMX8MN_ARM_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_ARM_PLL); + hws[IMX8MN_SYS_PLL1] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_PLL1); + hws[IMX8MN_SYS_PLL2] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_PLL2); + hws[IMX8MN_SYS_PLL3] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_PLL3); =20 /* PLL bypass out */ - hws[IMX8MN_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels),= CLK_SET_RATE_PARENT); - hws[IMX8MN_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sel= s), CLK_SET_RATE_PARENT); - hws[IMX8MN_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", b= ase + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), = CLK_SET_RATE_PARENT); - hws[IMX8MN_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", bas= e + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MN_M7_ALT_PLL_BYPASS] =3D imx_clk_hw_mux_flags("m7_alt_pll_bypass= ", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_ARM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("arm_pll_bypass", bas= e + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MN_SYS_PLL3_BYPASS] =3D imx_clk_hw_mux_flags("sys_pll3_bypass", b= ase + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels),= CLK_SET_RATE_PARENT); + hws[IMX8MN_AUDIO_PLL1_BYPASS] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_A= UDIO_PLL1_BYPASS); + hws[IMX8MN_AUDIO_PLL2_BYPASS] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_A= UDIO_PLL2_BYPASS); + hws[IMX8MN_VIDEO_PLL_BYPASS] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_VI= DEO_PLL_BYPASS); + hws[IMX8MN_DRAM_PLL_BYPASS] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_DRA= M_PLL_BYPASS); + hws[IMX8MN_GPU_PLL_BYPASS] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_GPU_= PLL_BYPASS); + hws[IMX8MN_M7_ALT_PLL_BYPASS] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_M= 7_ALT_PLL_BYPASS); + hws[IMX8MN_ARM_PLL_BYPASS] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_ARM_= PLL_BYPASS); + hws[IMX8MN_SYS_PLL3_BYPASS] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS= _PLL3_BYPASS); =20 /* PLL out gate */ - hws[IMX8MN_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", base, 13); - hws[IMX8MN_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", base + 0x14, 13); - hws[IMX8MN_VIDEO_PLL_OUT] =3D imx_clk_hw_gate("video_pll_out", "video_pll= _bypass", base + 0x28, 13); - hws[IMX8MN_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", base + 0x50, 13); - hws[IMX8MN_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", base + 0x64, 11); - hws[IMX8MN_M7_ALT_PLL_OUT] =3D imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_= pll_bypass", base + 0x74, 11); - hws[IMX8MN_ARM_PLL_OUT] =3D imx_clk_hw_gate("arm_pll_out", "arm_pll_bypas= s", base + 0x84, 11); - hws[IMX8MN_SYS_PLL3_OUT] =3D imx_clk_hw_gate("sys_pll3_out", "sys_pll3_by= pass", base + 0x114, 11); + hws[IMX8MN_AUDIO_PLL1_OUT] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_AUDI= O_PLL1_OUT); + hws[IMX8MN_AUDIO_PLL2_OUT] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_AUDI= O_PLL2_OUT); + hws[IMX8MN_VIDEO_PLL_OUT] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_VIDEO= _PLL_OUT); + hws[IMX8MN_DRAM_PLL_OUT] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_DRAM_P= LL_OUT); + hws[IMX8MN_GPU_PLL_OUT] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_GPU_PLL= _OUT); + hws[IMX8MN_M7_ALT_PLL_OUT] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_M7_A= LT_PLL_OUT); + hws[IMX8MN_ARM_PLL_OUT] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_ARM_PLL= _OUT); + hws[IMX8MN_SYS_PLL3_OUT] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_PL= L3_OUT); =20 /* SYS PLL1 fixed output */ - hws[IMX8MN_SYS_PLL1_OUT] =3D imx_clk_hw_gate("sys_pll1_out", "sys_pll1", = base + 0x94, 11); - hws[IMX8MN_SYS_PLL1_40M] =3D imx_clk_hw_fixed_factor("sys_pll1_40m", "sys= _pll1_out", 1, 20); - hws[IMX8MN_SYS_PLL1_80M] =3D imx_clk_hw_fixed_factor("sys_pll1_80m", "sys= _pll1_out", 1, 10); - hws[IMX8MN_SYS_PLL1_100M] =3D imx_clk_hw_fixed_factor("sys_pll1_100m", "s= ys_pll1_out", 1, 8); - hws[IMX8MN_SYS_PLL1_133M] =3D imx_clk_hw_fixed_factor("sys_pll1_133m", "s= ys_pll1_out", 1, 6); - hws[IMX8MN_SYS_PLL1_160M] =3D imx_clk_hw_fixed_factor("sys_pll1_160m", "s= ys_pll1_out", 1, 5); - hws[IMX8MN_SYS_PLL1_200M] =3D imx_clk_hw_fixed_factor("sys_pll1_200m", "s= ys_pll1_out", 1, 4); - hws[IMX8MN_SYS_PLL1_266M] =3D imx_clk_hw_fixed_factor("sys_pll1_266m", "s= ys_pll1_out", 1, 3); - hws[IMX8MN_SYS_PLL1_400M] =3D imx_clk_hw_fixed_factor("sys_pll1_400m", "s= ys_pll1_out", 1, 2); - hws[IMX8MN_SYS_PLL1_800M] =3D imx_clk_hw_fixed_factor("sys_pll1_800m", "s= ys_pll1_out", 1, 1); + hws[IMX8MN_SYS_PLL1_OUT] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_PL= L1_OUT); + hws[IMX8MN_SYS_PLL1_40M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_PL= L1_40M); + hws[IMX8MN_SYS_PLL1_80M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_PL= L1_80M); + hws[IMX8MN_SYS_PLL1_100M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_P= LL1_100M); + hws[IMX8MN_SYS_PLL1_133M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_P= LL1_133M); + hws[IMX8MN_SYS_PLL1_160M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_P= LL1_160M); + hws[IMX8MN_SYS_PLL1_200M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_P= LL1_200M); + hws[IMX8MN_SYS_PLL1_266M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_P= LL1_266M); + hws[IMX8MN_SYS_PLL1_400M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_P= LL1_400M); + hws[IMX8MN_SYS_PLL1_800M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_P= LL1_800M); =20 /* SYS PLL2 fixed output */ - hws[IMX8MN_SYS_PLL2_OUT] =3D imx_clk_hw_gate("sys_pll2_out", "sys_pll2", = base + 0x104, 11); - hws[IMX8MN_SYS_PLL2_50M] =3D imx_clk_hw_fixed_factor("sys_pll2_50m", "sys= _pll2_out", 1, 20); - hws[IMX8MN_SYS_PLL2_100M] =3D imx_clk_hw_fixed_factor("sys_pll2_100m", "s= ys_pll2_out", 1, 10); - hws[IMX8MN_SYS_PLL2_125M] =3D imx_clk_hw_fixed_factor("sys_pll2_125m", "s= ys_pll2_out", 1, 8); - hws[IMX8MN_SYS_PLL2_166M] =3D imx_clk_hw_fixed_factor("sys_pll2_166m", "s= ys_pll2_out", 1, 6); - hws[IMX8MN_SYS_PLL2_200M] =3D imx_clk_hw_fixed_factor("sys_pll2_200m", "s= ys_pll2_out", 1, 5); - hws[IMX8MN_SYS_PLL2_250M] =3D imx_clk_hw_fixed_factor("sys_pll2_250m", "s= ys_pll2_out", 1, 4); - hws[IMX8MN_SYS_PLL2_333M] =3D imx_clk_hw_fixed_factor("sys_pll2_333m", "s= ys_pll2_out", 1, 3); - hws[IMX8MN_SYS_PLL2_500M] =3D imx_clk_hw_fixed_factor("sys_pll2_500m", "s= ys_pll2_out", 1, 2); - hws[IMX8MN_SYS_PLL2_1000M] =3D imx_clk_hw_fixed_factor("sys_pll2_1000m", = "sys_pll2_out", 1, 1); - - hws[IMX8MN_CLK_CLKOUT1_SEL] =3D imx_clk_hw_mux2("clkout1_sel", base + 0x1= 28, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MN_CLK_CLKOUT1_DIV] =3D imx_clk_hw_divider("clkout1_div", "clkout= 1_sel", base + 0x128, 0, 4); - hws[IMX8MN_CLK_CLKOUT1] =3D imx_clk_hw_gate("clkout1", "clkout1_div", bas= e + 0x128, 8); - hws[IMX8MN_CLK_CLKOUT2_SEL] =3D imx_clk_hw_mux2("clkout2_sel", base + 0x1= 28, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MN_CLK_CLKOUT2_DIV] =3D imx_clk_hw_divider("clkout2_div", "clkout= 2_sel", base + 0x128, 16, 4); - hws[IMX8MN_CLK_CLKOUT2] =3D imx_clk_hw_gate("clkout2", "clkout2_div", bas= e + 0x128, 24); - - np =3D dev->of_node; - base =3D devm_platform_ioremap_resource(pdev, 0); - if (WARN_ON(IS_ERR(base))) { - ret =3D PTR_ERR(base); - goto unregister_hws; - } + hws[IMX8MN_SYS_PLL2_OUT] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_PL= L2_OUT); + hws[IMX8MN_SYS_PLL2_50M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_PL= L2_50M); + hws[IMX8MN_SYS_PLL2_100M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_P= LL2_100M); + hws[IMX8MN_SYS_PLL2_125M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_P= LL2_125M); + hws[IMX8MN_SYS_PLL2_166M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_P= LL2_166M); + hws[IMX8MN_SYS_PLL2_200M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_P= LL2_200M); + hws[IMX8MN_SYS_PLL2_250M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_P= LL2_250M); + hws[IMX8MN_SYS_PLL2_333M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_P= LL2_333M); + hws[IMX8MN_SYS_PLL2_500M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_P= LL2_500M); + hws[IMX8MN_SYS_PLL2_1000M] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SYS_= PLL2_1000M); + + hws[IMX8MN_CLK_CLKOUT1_SEL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_CLK= _CLKOUT1_SEL); + hws[IMX8MN_CLK_CLKOUT1_DIV] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_CLK= _CLKOUT1_DIV); + hws[IMX8MN_CLK_CLKOUT1] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_CLK_CLK= OUT1); + hws[IMX8MN_CLK_CLKOUT2_SEL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_CLK= _CLKOUT2_SEL); + hws[IMX8MN_CLK_CLKOUT2_DIV] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_CLK= _CLKOUT2_DIV); + hws[IMX8MN_CLK_CLKOUT2] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_CLK_CLK= OUT2); =20 /* CORE */ hws[IMX8MN_CLK_A53_DIV] =3D imx8m_clk_hw_composite_core("arm_a53_div", im= x8mn_a53_sels, base + 0x8000); @@ -599,18 +573,15 @@ static int imx8mn_clocks_probe(struct platform_device= *pdev) =20 ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); if (ret < 0) { - dev_err(dev, "failed to register hws for i.MX8MN\n"); - goto unregister_hws; + imx_unregister_hw_clocks(hws, IMX8MN_CLK_END); + return dev_err_probe(dev, ret, + "failed to register hws for i.MX8MN\n"); } =20 imx_register_uart_clocks(); =20 + dev_info(dev, "NXP i.MX8MN ccm clock driver probed\n"); return 0; - -unregister_hws: - imx_unregister_hw_clocks(hws, IMX8MN_CLK_END); - - return ret; } =20 static const struct of_device_id imx8mn_clk_of_match[] =3D { --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48D481DE2A2 for ; Sun, 1 Dec 2024 17:47:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:40 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v4 13/18] dt-bindings: clock: imx8m-clock: support spread spectrum clocking Date: Sun, 1 Dec 2024 18:46:13 +0100 Message-ID: <20241201174639.742000-14-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds the DT bindings for enabling and tuning spread spectrum clocking generation. Signed-off-by: Dario Binacchi - Drop "fsl,ssc-clocks" property. The other added properties now refer to the clock list. - Updated minItems and maxItems of - clocks - clock-names - fsl,ssc-modfreq-hz - fsl,ssc-modrate-percent - fsl,ssc-modmethod - Updated the dts examples - Added in v3 - The dt-bindings have been moved from fsl,imx8m-anatop.yaml to imx8m-clock.yaml. The anatop device (fsl,imx8m-anatop.yaml) is indeed more or less a syscon, so it represents a memory area accessible by ccm (imx8m-clock.yaml) to setup the PLLs. - Add "allOf:" and place it after "required:" block, like in the example schema. - Move the properties definition to the top-level. - Drop unit types as requested by the "make dt_binding_check" command. --- (no changes since v1) .../bindings/clock/imx8m-clock.yaml | 77 +++++++++++++++++-- 1 file changed, 71 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Doc= umentation/devicetree/bindings/clock/imx8m-clock.yaml index c643d4a81478..83036f6d2274 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -29,12 +29,12 @@ properties: maxItems: 2 =20 clocks: - minItems: 6 - maxItems: 7 + minItems: 7 + maxItems: 10 =20 clock-names: - minItems: 6 - maxItems: 7 + minItems: 7 + maxItems: 10 =20 '#clock-cells': const: 1 @@ -43,6 +43,34 @@ properties: ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m= -clock.h for the full list of i.MX8M clock IDs. =20 + fsl,ssc-modfreq-hz: + description: + The values of modulation frequency (Hz unit) for each clock + supporting spread spectrum. + minItems: 7 + maxItems: 10 + + fsl,ssc-modrate-percent: + description: + The percentage values of modulation rate for each clock + supporting spread spectrum. + minItems: 7 + maxItems: 10 + + fsl,ssc-modmethod: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: + The modulation techniques for each clock supporting spread + spectrum. + minItems: 7 + maxItems: 10 + items: + enum: + - "" + - down-spread + - up-spread + - center-spread + required: - compatible - reg @@ -76,6 +104,10 @@ allOf: - const: clk_ext2 - const: clk_ext3 - const: clk_ext4 + fsl,ssc-modfreq-hz: false + fsl,ssc-modrate-percent: false + fsl,ssc-modmethod: false + else: properties: clocks: @@ -86,6 +118,10 @@ allOf: - description: ext2 clock input - description: ext3 clock input - description: ext4 clock input + - description: audio1 PLL input + - description: audio2 PLL input + - description: dram PLL input + - description: video PLL input =20 clock-names: items: @@ -95,20 +131,49 @@ allOf: - const: clk_ext2 - const: clk_ext3 - const: clk_ext4 + - const: audio_pll1 + - const: audio_pll2 + - const: dram_pll + - const: video_pll =20 additionalProperties: false =20 examples: # Clock Control Module node: - | + #include + clock-controller@30380000 { compatible =3D "fsl,imx8mm-ccm"; reg =3D <0x30380000 0x10000>; #clock-cells =3D <1>; clocks =3D <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MM_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MM_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MM_ANATOP_DRAM_PLL>, + <&anatop IMX8MM_ANATOP_VIDEO_PLL>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; + fsl,ssc-modfreq-hz =3D <0>, <0>, <0>, <0>, + <0>, <0>, + <6818>, + <0>, + <0>, + <2419>; + fsl,ssc-modrate-percent =3D <0>, <0>, <0>, <0>, + <0>, <0>, + <3>, + <0>, + <0>, + <7>; + fsl,ssc-modmethod =3D "", "", "", "", + "", "", + "down-spread", + "", + "", + "center-spread"; }; =20 - | --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8904A1DE2D4 for ; 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[82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:43 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 14/18] arm64: dts: imx8mm: add PLLs to clock controller module (ccm) Date: Sun, 1 Dec 2024 18:46:14 +0100 Message-ID: <20241201174639.742000-15-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the PLLs generated by anatop to the clock list of the Clock Controller Module (CCM) node. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mm.dtsi index 597041a05073..0b35aecb6755 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -642,9 +642,14 @@ clk: clock-controller@30380000 { ; #clock-cells =3D <1>; clocks =3D <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MM_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MM_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MM_ANATOP_DRAM_PLL>, + <&anatop IMX8MM_ANATOP_VIDEO_PLL>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; assigned-clocks =3D <&clk IMX8MM_CLK_A53_SRC>, <&clk IMX8MM_CLK_A53_CORE>, <&clk IMX8MM_CLK_NOC>, --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A382A1DE2AB for ; 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[82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:45 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 15/18] arm64: dts: imx8mn: add PLLs to clock controller module (ccm) Date: Sun, 1 Dec 2024 18:46:15 +0100 Message-ID: <20241201174639.742000-16-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the PLLs generated by anatop to the clock list of the Clock Controller Module (CCM) node. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mn.dtsi index 49be492b5687..aaa179784717 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -643,9 +643,14 @@ clk: clock-controller@30380000 { ; #clock-cells =3D <1>; clocks =3D <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MN_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MN_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MN_ANATOP_DRAM_PLL>, + <&anatop IMX8MN_ANATOP_VIDEO_PLL>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; assigned-clocks =3D <&clk IMX8MN_CLK_A53_SRC>, <&clk IMX8MN_CLK_A53_CORE>, <&clk IMX8MN_CLK_NOC>, --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A3FE1BC094 for ; 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[82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:49 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 16/18] arm64: dts: imx8mp: add PLLs to clock controller module (ccm) Date: Sun, 1 Dec 2024 18:46:16 +0100 Message-ID: <20241201174639.742000-17-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the PLLs generated by anatop to the clock list of the Clock Controller Module (CCM) node. Signed-off-by: Dario Binacchi - Added in v4 --- (no changes since v1) arch/arm64/boot/dts/freescale/imx8mp.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index 0b928e173f29..861bd4f4dced 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -751,9 +751,14 @@ clk: clock-controller@30380000 { ; #clock-cells =3D <1>; clocks =3D <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MP_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MP_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MP_ANATOP_DRAM_PLL>, + <&anatop IMX8MP_ANATOP_VIDEO_PLL>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; assigned-clocks =3D <&clk IMX8MP_CLK_A53_SRC>, <&clk IMX8MP_CLK_A53_CORE>, <&clk IMX8MP_CLK_NOC>, --=20 2.43.0 From nobody Sun Feb 8 16:53:18 2026 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E7C21D7E5C for ; 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[82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:51 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v4 17/18] clk: imx: pll14xx: support spread spectrum clock generation Date: Sun, 1 Dec 2024 18:46:17 +0100 Message-ID: <20241201174639.742000-18-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for spread spectrum clock (SSC) generation to the pll14xxx driver. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-pll14xx.c | 127 ++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 16 +++++ 2 files changed, 143 insertions(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index d63564dbb12c..b07c59fd659a 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -20,6 +20,8 @@ #define GNRL_CTL 0x0 #define DIV_CTL0 0x4 #define DIV_CTL1 0x8 +#define SSCG_CTRL 0xc + #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -31,6 +33,10 @@ #define KDIV_MASK GENMASK(15, 0) #define KDIV_MIN SHRT_MIN #define KDIV_MAX SHRT_MAX +#define SSCG_ENABLE BIT(31) +#define MFREQ_CTL_MASK GENMASK(19, 12) +#define MRAT_CTL_MASK GENMASK(9, 4) +#define SEL_PF_MASK GENMASK(1, 0) =20 #define LOCK_TIMEOUT_US 10000 =20 @@ -40,6 +46,8 @@ struct clk_pll14xx { enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; int rate_count; + bool ssc_enable; + struct imx_pll14xx_ssc ssc_conf; }; =20 #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) @@ -347,6 +355,27 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, un= signed long drate, return 0; } =20 +static void clk_pll1443x_enable_ssc(struct clk_hw *hw, unsigned long paren= t_rate, + unsigned int pdiv, unsigned int mdiv) +{ + struct clk_pll14xx *pll =3D to_clk_pll14xx(hw); + struct imx_pll14xx_ssc *conf =3D &pll->ssc_conf; + u32 sscg_ctrl, mfr, mrr; + + sscg_ctrl =3D readl_relaxed(pll->base + SSCG_CTRL); + sscg_ctrl &=3D + ~(SSCG_ENABLE | MFREQ_CTL_MASK | MRAT_CTL_MASK | SEL_PF_MASK); + + mfr =3D parent_rate / (conf->mod_freq * pdiv * (1 << 5)); + mrr =3D (conf->mod_rate * mdiv * (1 << 6)) / (100 * mfr); + + sscg_ctrl |=3D SSCG_ENABLE | FIELD_PREP(MFREQ_CTL_MASK, mfr) | + FIELD_PREP(MRAT_CTL_MASK, mrr) | + FIELD_PREP(SEL_PF_MASK, conf->mod_type); + + writel_relaxed(sscg_ctrl, pll->base + SSCG_CTRL); +} + static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { @@ -368,6 +397,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, uns= igned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); =20 + if (pll->ssc_enable) + clk_pll1443x_enable_ssc(hw, prate, rate.pdiv, rate.mdiv); + return 0; } =20 @@ -408,6 +440,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, uns= igned long drate, gnrl_ctl &=3D ~BYPASS_MASK; writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); =20 + if (pll->ssc_enable) + clk_pll1443x_enable_ssc(hw, prate, rate.pdiv, rate.mdiv); + return 0; } =20 @@ -542,3 +577,95 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *d= ev, const char *name, return hw; } EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx); + +void imx_clk_pll14xx_enable_ssc(struct clk_hw *hw, struct imx_pll14xx_ssc = *conf) +{ + struct clk_pll14xx *pll =3D to_clk_pll14xx(hw); + + pll->ssc_enable =3D true; + memcpy(&pll->ssc_conf, conf, sizeof(pll->ssc_conf)); +} +EXPORT_SYMBOL_GPL(imx_clk_pll14xx_enable_ssc); + +static int clk_pll14xx_ssc_mod_type(const char *name, + enum imx_pll14xx_ssc_mod_type *mod_type) +{ + int i; + struct { + const char *name; + enum imx_pll14xx_ssc_mod_type id; + } mod_types[] =3D { + { .name =3D "down-spread", .id =3D IMX_PLL14XX_SSC_DOWN_SPREAD }, + { .name =3D "up-spread", .id =3D IMX_PLL14XX_SSC_UP_SPREAD }, + { .name =3D "center-spread", .id =3D IMX_PLL14XX_SSC_CENTER_SPREAD } + }; + + pr_info("%s, name: %s\n", __func__, name); + for (i =3D 0; i < ARRAY_SIZE(mod_types); i++) { + if (!strcmp(name, mod_types[i].name)) { + *mod_type =3D mod_types[i].id; + return 0; + } + } + + return -EINVAL; +} + +int imx_clk_pll14xx_ssc_parse_dt(struct device_node *np, const char *pll_n= ame, + struct imx_pll14xx_ssc *conf) +{ + int i, ret, num_clks; + const char *s; + + if (!conf) + return -EINVAL; + + ret =3D of_property_count_strings(np, "clock-names"); + if (ret < 0) + return ret; + + num_clks =3D ret; + for (i =3D 0; i < num_clks; i++) { + ret =3D of_property_read_string_index(np, "clock-names", i, &s); + if (strcmp(pll_name, s)) + continue; + + ret =3D of_property_read_u32_index(np, "fsl,ssc-modfreq-hz", i, + &conf->mod_freq); + if (ret) + return ret; + + ret =3D of_property_read_u32_index(np, "fsl,ssc-modrate-percent", i, + &conf->mod_rate); + if (ret) { + pr_err("missing fsl,ssc-modrate-percent property for %pOFn\n", + np); + return ret; + } + + ret =3D of_property_read_string_index(np, "fsl,ssc-modmethod", i, &s); + if (ret) { + pr_err("failed to get fsl,ssc-modmethod property for %pOFn\n", + np); + return ret; + } + + if (strlen(s) =3D=3D 0) + return -ENODEV; + + ret =3D clk_pll14xx_ssc_mod_type(s, &conf->mod_type); + if (ret) { + pr_err("wrong fsl,ssc-modmethod property for %pOFn\n", np); + return ret; + + } + + pr_debug("%s: mod_freq: %d, mod_rate: %d: mod_method: %s [%d]\n", + __func__, conf->mod_freq, conf->mod_rate, s, conf->mod_type); + + return 0; + } + + return -ENODEV; +} +EXPORT_SYMBOL_GPL(imx_clk_pll14xx_ssc_parse_dt); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 6b6af26f4f1e..dad6e90c7dc0 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -69,6 +69,18 @@ struct imx_pll14xx_clk { int flags; }; =20 +enum imx_pll14xx_ssc_mod_type { + IMX_PLL14XX_SSC_DOWN_SPREAD, + IMX_PLL14XX_SSC_UP_SPREAD, + IMX_PLL14XX_SSC_CENTER_SPREAD, +}; + +struct imx_pll14xx_ssc { + unsigned int mod_freq; + unsigned int mod_rate; + enum imx_pll14xx_ssc_mod_type mod_type; +}; + extern struct imx_pll14xx_clk imx_1416x_pll; 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[82.54.94.193]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa59990a78esm415220066b.163.2024.12.01.09.47.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 09:47:53 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v4 18/18] clk: imx8mn: support spread spectrum clock generation Date: Sun, 1 Dec 2024 18:46:18 +0100 Message-ID: <20241201174639.742000-19-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> References: <20241201174639.742000-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-imx8mn.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 588cebce6c9d..c61368e724f7 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -306,6 +306,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; void __iomem *base; + struct imx_pll14xx_ssc ssc_conf; int ret; =20 base =3D devm_platform_ioremap_resource(pdev, 0); @@ -338,9 +339,21 @@ static int imx8mn_clocks_probe(struct platform_device = *pdev) hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_SY= S_PLL3_REF_SEL); =20 hws[IMX8MN_AUDIO_PLL1] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_AUDIO_PL= L1); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll1", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL1], &ssc_conf); + hws[IMX8MN_AUDIO_PLL2] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_AUDIO_PL= L2); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll2", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL2], &ssc_conf); + hws[IMX8MN_VIDEO_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_VIDEO_PLL= ); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "video_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_VIDEO_PLL], &ssc_conf); + hws[IMX8MN_DRAM_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_DRAM_PLL); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "dram_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_DRAM_PLL], &ssc_conf); + hws[IMX8MN_GPU_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_GPU_PLL); hws[IMX8MN_M7_ALT_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_M7_ALT_P= LL); hws[IMX8MN_ARM_PLL] =3D imx8m_anatop_get_clk_hw(IMX8MN_ANATOP_ARM_PLL); --=20 2.43.0