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Sun, 01 Dec 2024 08:20:03 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nick Chan Subject: [PATCH 1/3] dt-bindings: arm: apple: Add T2 devices Date: Mon, 2 Dec 2024 00:18:41 +0800 Message-ID: <20241201161942.36027-2-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241201161942.36027-1-towinchenmi@gmail.com> References: <20241201161942.36027-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds the following apple,t8012 based platforms: - Apple T2 MacBookPro15,2 (j132) - Apple T2 iMacPro1,1 (j137) - Apple T2 MacBookAir8,2 (j140a) - Apple T2 MacBookAir8,1 (j140k) - Apple T2 MacBookPro16,1 (j152f) - Apple T2 MacPro7,1 (j160) - Apple T2 Macmini8,1 (j174) - Apple T2 iMac20,1 (j185) - Apple T2 iMac20,2 (j185f) - Apple T2 MacBookPro15,4 (j213) - Apple T2 MacBookPro16,2 (j214k) - Apple T2 MacBookPro16,4 (j215) - Apple T2 MacBookPro16,3 (j223) - Apple T2 MacBookAir9,1 (j230k) - Apple T2 MacBookPro15,1 (j680) - Apple T2 MacBookPro15,3 (j780) These devices have no offical names, the naming scheme is from libirecovery. Signed-off-by: Nick Chan Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/apple.yaml | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentati= on/devicetree/bindings/arm/apple.yaml index dc9aab19ff11..da60e9de1cfb 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -57,6 +57,25 @@ description: | - iPad Pro (2nd Generation) (10.5 Inch) - iPad Pro (2nd Generation) (12.9 Inch) =20 + Devices based on the "T2" SoC: + + - Apple T2 MacBookPro15,2 (j132) + - Apple T2 iMacPro1,1 (j137) + - Apple T2 MacBookAir8,2 (j140a) + - Apple T2 MacBookAir8,1 (j140k) + - Apple T2 MacBookPro16,1 (j152f) + - Apple T2 MacPro7,1 (j160) + - Apple T2 Macmini8,1 (j174) + - Apple T2 iMac20,1 (j185) + - Apple T2 iMac20,2 (j185f) + - Apple T2 MacBookPro15,4 (j213) + - Apple T2 MacBookPro16,2 (j214k) + - Apple T2 MacBookPro16,4 (j215) + - Apple T2 MacBookPro16,3 (j223) + - Apple T2 MacBookAir9,1 (j230k) + - Apple T2 MacBookPro15,1 (j680) + - Apple T2 MacBookPro15,3 (j780) + Devices based on the "A11" SoC: =20 - iPhone 8 @@ -211,6 +230,28 @@ properties: - const: apple,t8011 - const: apple,arm-platform =20 + - description: Apple T2 SoC based platforms + items: + - enum: + - apple,j132 # Apple T2 MacBookPro15,2 (j132) + - apple,j137 # Apple T2 iMacPro1,1 (j137) + - apple,j140a # Apple T2 MacBookAir8,2 (j140a) + - apple,j140k # Apple T2 MacBookAir8,1 (j140k) + - apple,j152f # Apple T2 MacBookPro16,1 (j152f) + - apple,j160 # Apple T2 MacPro7,1 (j160) + - apple,j174 # Apple T2 Macmini8,1 (j174) + - apple,j185 # Apple T2 iMac20,1 (j185) + - apple,j185f # Apple T2 iMac20,2 (j185f) + - apple,j213 # Apple T2 MacBookPro15,4 (j213) + - apple,j214k # Apple T2 MacBookPro16,2 (j214k) + - apple,j215 # Apple T2 MacBookPro16,4 (j215) + - apple,j223 # Apple T2 MacBookPro16,3 (j223) + - apple,j230k # Apple T2 MacBookAir9,1 (j230k) + - apple,j680 # Apple T2 MacBookPro15,1 (j680) + - apple,j780 # Apple T2 MacBookPro15,3 (j780) + - const: apple,t8012 + - const: apple,arm-platform + - description: Apple A11 SoC based platforms items: - enum: --=20 2.47.1 From nobody Sun Feb 8 02:20:48 2026 Received: from mail-pj1-f54.google.com (mail-pj1-f54.google.com [209.85.216.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DF8D1D79A7; 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Sun, 01 Dec 2024 08:20:07 -0800 (PST) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-2ee78834450sm3007392a91.6.2024.12.01.08.20.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 08:20:06 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nick Chan Subject: [PATCH 2/3] arm64: dts: apple: Add T2 devices Date: Mon, 2 Dec 2024 00:18:42 +0800 Message-ID: <20241201161942.36027-3-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241201161942.36027-1-towinchenmi@gmail.com> References: <20241201161942.36027-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DTS files for the T2 SoC and the following devices based on it: - Apple T2 MacBookPro15,2 (j132) - Apple T2 iMacPro1,1 (j137) - Apple T2 MacBookAir8,2 (j140a) - Apple T2 MacBookAir8,1 (j140k) - Apple T2 MacBookPro16,1 (j152f) - Apple T2 MacPro7,1 (j160) - Apple T2 Macmini8,1 (j174) - Apple T2 iMac20,1 (j185) - Apple T2 iMac20,2 (j185f) - Apple T2 MacBookPro15,4 (j213) - Apple T2 MacBookPro16,2 (j214k) - Apple T2 MacBookPro16,4 (j215) - Apple T2 MacBookPro16,3 (j223) - Apple T2 MacBookAir9,1 (j230k) - Apple T2 MacBookPro15,1 (j680) - Apple T2 MacBookPro15,3 (j780) The Apple T2 is an A10-based security chip found on some Intel Macs from 2017 onwards. On models with a touchbar, the touchbar's display is wired to it. These devices have no offical names, the naming scheme is from libirecovery. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/Makefile | 16 ++ arch/arm64/boot/dts/apple/t8012-j132.dts | 14 ++ arch/arm64/boot/dts/apple/t8012-j137.dts | 14 ++ arch/arm64/boot/dts/apple/t8012-j140a.dts | 14 ++ arch/arm64/boot/dts/apple/t8012-j140k.dts | 14 ++ arch/arm64/boot/dts/apple/t8012-j152f.dts | 15 ++ arch/arm64/boot/dts/apple/t8012-j160.dts | 14 ++ arch/arm64/boot/dts/apple/t8012-j174.dts | 14 ++ arch/arm64/boot/dts/apple/t8012-j185.dts | 14 ++ arch/arm64/boot/dts/apple/t8012-j185f.dts | 14 ++ arch/arm64/boot/dts/apple/t8012-j213.dts | 15 ++ arch/arm64/boot/dts/apple/t8012-j214k.dts | 15 ++ arch/arm64/boot/dts/apple/t8012-j215.dts | 15 ++ arch/arm64/boot/dts/apple/t8012-j223.dts | 15 ++ arch/arm64/boot/dts/apple/t8012-j230k.dts | 14 ++ arch/arm64/boot/dts/apple/t8012-j680.dts | 15 ++ arch/arm64/boot/dts/apple/t8012-j780.dts | 15 ++ arch/arm64/boot/dts/apple/t8012-jxxx.dtsi | 44 +++++ arch/arm64/boot/dts/apple/t8012-touchbar.dtsi | 19 ++ arch/arm64/boot/dts/apple/t8012.dtsi | 176 ++++++++++++++++++ 20 files changed, 486 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t8012-j132.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j137.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j140a.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j140k.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j152f.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j160.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j174.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j185.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j185f.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j213.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j214k.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j215.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j223.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j230k.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j680.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-j780.dts create mode 100644 arch/arm64/boot/dts/apple/t8012-jxxx.dtsi create mode 100644 arch/arm64/boot/dts/apple/t8012-touchbar.dtsi create mode 100644 arch/arm64/boot/dts/apple/t8012.dtsi diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple= /Makefile index ab6ebb53218a..4f337bff36cd 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -46,6 +46,22 @@ dtb-$(CONFIG_ARCH_APPLE) +=3D t8011-j120.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8011-j121.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8011-j207.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8011-j208.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j132.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j137.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j140a.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j140k.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j152f.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j160.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j174.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j185.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j185f.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j213.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j215.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j223.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j230k.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j214k.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j680.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8012-j780.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8015-d201.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8015-d20.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8015-d211.dtb diff --git a/arch/arm64/boot/dts/apple/t8012-j132.dts b/arch/arm64/boot/dts= /apple/t8012-j132.dts new file mode 100644 index 000000000000..778a69be18dd --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j132.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro15,2 (j132), J132, iBridge2,4 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model =3D "Apple T2 MacBookPro15,2 (j132)"; + compatible =3D "apple,j132", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j137.dts b/arch/arm64/boot/dts= /apple/t8012-j137.dts new file mode 100644 index 000000000000..dbde1ad7ce14 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j137.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 iMacPro1,1 (j137), J137, iBridge2,1 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model =3D "Apple T2 iMacPro1,1 (j137)"; + compatible =3D "apple,j137", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j140a.dts b/arch/arm64/boot/dt= s/apple/t8012-j140a.dts new file mode 100644 index 000000000000..5df1ff74d2df --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j140a.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookAir8,2 (j140a), J140a, iBridge2,12 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model =3D "Apple T2 MacBookAir8,2 (j140a)"; + compatible =3D "apple,j140a", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j140k.dts b/arch/arm64/boot/dt= s/apple/t8012-j140k.dts new file mode 100644 index 000000000000..a0ef1585e5c2 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j140k.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookAir8,1 (j140k), J140k, iBridge2,8 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model =3D "Apple T2 MacBookAir8,1 (j140k)"; + compatible =3D "apple,j140k", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j152f.dts b/arch/arm64/boot/dt= s/apple/t8012-j152f.dts new file mode 100644 index 000000000000..261416eaf97e --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j152f.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro16,1 (j152f), J152f, iBridge2,14 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model =3D "Apple T2 MacBookPro16,1 (j152f)"; + compatible =3D "apple,j152f", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j160.dts b/arch/arm64/boot/dts= /apple/t8012-j160.dts new file mode 100644 index 000000000000..fbcc0604f4a0 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j160.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacPro7,1 (j160), J160, iBridge2,6 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model =3D "Apple T2 MacPro7,1 (j160)"; + compatible =3D "apple,j160", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j174.dts b/arch/arm64/boot/dts= /apple/t8012-j174.dts new file mode 100644 index 000000000000..d11c70f84a71 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j174.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 Macmini8,1 (j174), J174, iBridge2,5 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model =3D "Apple T2 Macmini8,1 (j174)"; + compatible =3D "apple,j174", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j185.dts b/arch/arm64/boot/dts= /apple/t8012-j185.dts new file mode 100644 index 000000000000..33492f5db46d --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j185.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 iMac20,1 (j185), J185, iBridge2,19 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model =3D "Apple T2 iMac20,1 (j185)"; + compatible =3D "apple,j185", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j185f.dts b/arch/arm64/boot/dt= s/apple/t8012-j185f.dts new file mode 100644 index 000000000000..3a4abdd8f7d7 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j185f.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 iMac20,2 (j185f), J185f, iBridge2,20 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model =3D "Apple T2 iMac20,2 (j185f)"; + compatible =3D "apple,j185f", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j213.dts b/arch/arm64/boot/dts= /apple/t8012-j213.dts new file mode 100644 index 000000000000..8270812b9a68 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j213.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro15,4 (j213), J213, iBridge2,10 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model =3D "Apple T2 MacBookPro15,4 (j213)"; + compatible =3D "apple,j213", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j214k.dts b/arch/arm64/boot/dt= s/apple/t8012-j214k.dts new file mode 100644 index 000000000000..5b8e42512060 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j214k.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro16,2 (j214k), J214k, iBridge2,16 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model =3D "Apple T2 MacBookPro16,2 (j214k)"; + compatible =3D "apple,j214k", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j215.dts b/arch/arm64/boot/dts= /apple/t8012-j215.dts new file mode 100644 index 000000000000..ad574fbf7f92 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j215.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro16,4 (j215), J215, iBridge2,22 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model =3D "Apple T2 MacBookPro16,4 (j215)"; + compatible =3D "apple,j215", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j223.dts b/arch/arm64/boot/dts= /apple/t8012-j223.dts new file mode 100644 index 000000000000..de75d775aac5 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j223.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro16,3 (j223), J223, iBridge2,21 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model =3D "Apple T2 MacBookPro16,3 (j223)"; + compatible =3D "apple,j223", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j230k.dts b/arch/arm64/boot/dt= s/apple/t8012-j230k.dts new file mode 100644 index 000000000000..4b19bc70ab0f --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j230k.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookAir9,1 (j230k), J230k, iBridge2,15 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model =3D "Apple T2 MacBookAir9,1 (j230k)"; + compatible =3D "apple,j230k", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j680.dts b/arch/arm64/boot/dts= /apple/t8012-j680.dts new file mode 100644 index 000000000000..aa5a72e07d3f --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j680.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro15,1 (j680), J680, iBridge2,3 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model =3D "Apple T2 MacBookPro15,1 (j680)"; + compatible =3D "apple,j680", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-j780.dts b/arch/arm64/boot/dts= /apple/t8012-j780.dts new file mode 100644 index 000000000000..9cee891cb16d --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-j780.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro15,3 (j780), J780, iBridge2,7 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model =3D "Apple T2 MacBookPro15,3 (j780)"; + compatible =3D "apple,j780", "apple,t8012", "apple,arm-platform"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-jxxx.dtsi b/arch/arm64/boot/dt= s/apple/t8012-jxxx.dtsi new file mode 100644 index 000000000000..36e82633bc52 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-jxxx.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Common Device Tree for all T2 devices + * + * target-type: J132, J137, J140a, J140k, J152f, J160, J174, J185, J185f + * J213, J214k, J215, J223, J230k, J680, J780 + * + * Copyright (c) 2024, Nick Chan + */ + +#include "t8012.dtsi" + +/ { + chassis-type =3D "embedded"; + + aliases { + serial0 =3D &serial0; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + stdout-path =3D "serial0"; + }; + + memory@800000000 { + device_type =3D "memory"; + reg =3D <0x8 0 0 0>; /* To be filled by loader */ + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* To be filled by loader */ + }; +}; + +&serial0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-touchbar.dtsi b/arch/arm64/boo= t/dts/apple/t8012-touchbar.dtsi new file mode 100644 index 000000000000..f4a8b12437f0 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-touchbar.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Common Device Tree for T2 devices with a Touch Bar + * + * target-type: J152f, J213, J214k, J215, J223, J680, J780 + * + * Copyright (c) 2024, Nick Chan + */ + +/ { + chosen { + framebuffer0: framebuffer@0 { + compatible =3D "apple,simple-framebuffer", "simple-framebuffer"; + reg =3D <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status =3D "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8012.dtsi b/arch/arm64/boot/dts/app= le/t8012.dtsi new file mode 100644 index 000000000000..45d24ca091b0 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012.dtsi @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T8012 "T2" SoC + * + * Other names: H9M, "Gibraltar" + * + * Copyright (c) 2024, Nick Chan + */ + +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&aic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + clkref: clock-ref { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "clkref"; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@10000 { + compatible =3D "apple,hurricane-zephyr"; + reg =3D <0x0 0x10000>; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + enable-method =3D "spin-table"; + device_type =3D "cpu"; + }; + + cpu1: cpu@10001 { + compatible =3D "apple,hurricane-zephyr"; + reg =3D <0x0 0x10001>; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + enable-method =3D "spin-table"; + device_type =3D "cpu"; + }; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + nonposted-mmio; + ranges; + + serial0: serial@20a600000 { + compatible =3D "apple,s5l-uart"; + reg =3D <0x2 0x0a600000 0x0 0x4000>; + reg-io-width =3D <4>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + /* Use the bootloader-enabled clocks for now. */ + clocks =3D <&clkref>, <&clkref>; + clock-names =3D "uart", "clk_uart_baud0"; + status =3D "disabled"; + }; + + aic: interrupt-controller@20e100000 { + compatible =3D "apple,t8010-aic", "apple,aic"; + reg =3D <0x2 0x0e100000 0x0 0x100000>; + #interrupt-cells =3D <3>; + interrupt-controller; + }; + + pinctrl_ap: pinctrl@20f100000 { + compatible =3D "apple,t8010-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x0f100000 0x0 0x100000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_ap 0 0 221>; + apple,npins =3D <221>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + }; + + pinctrl_aop: pinctrl@2100f0000 { + compatible =3D "apple,t8010-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x0100f0000 0x0 0x10000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_aop 0 0 41>; + apple,npins =3D <41>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + }; + + pinctrl_nub: pinctrl@2111f0000 { + compatible =3D "apple,t8010-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x111f0000 0x0 0x1000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_nub 0 0 19>; + apple,npins =3D <19>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + ; + }; + + wdt: watchdog@2112b0000 { + compatible =3D "apple,t8010-wdt", "apple,wdt"; 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Sun, 01 Dec 2024 08:20:10 -0800 (PST) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-2ee78834450sm3007392a91.6.2024.12.01.08.20.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Dec 2024 08:20:09 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nick Chan Subject: [PATCH 3/3] arm64: dts: apple: t8012: Add PMGR nodes Date: Mon, 2 Dec 2024 00:18:43 +0800 Message-ID: <20241201161942.36027-4-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241201161942.36027-1-towinchenmi@gmail.com> References: <20241201161942.36027-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds the two PMGR nodes and all known power state subnodes. Since there are a large number of them, let's put them in a separate file to include. On models with only 1 GB of memory, only two memory channels are used, and on models with 2 GB of memory, four memory channels are used. The "apple,always-on" property of the extra memory channel power domains (ps_dcs2, ps_dcs3) will be removed by loader on models with 1 GB of memory. The amount of memory depends on the storage configuration of the Mac. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8012-pmgr.dtsi | 837 ++++++++++++++++++ arch/arm64/boot/dts/apple/t8012-touchbar.dtsi | 1 + arch/arm64/boot/dts/apple/t8012.dtsi | 22 + 3 files changed, 860 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t8012-pmgr.dtsi diff --git a/arch/arm64/boot/dts/apple/t8012-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/t8012-pmgr.dtsi new file mode 100644 index 000000000000..35a462edd4af --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8012-pmgr.dtsi @@ -0,0 +1,837 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8012 "T2" SoC + * + * Copyright (c) 2024 Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80040 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80158 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80158 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_busif"; + }; + + ps_sio_p: power-controller@80160 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80160 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_p"; + power-domains =3D <&ps_sio_busif>; + }; + + ps_iomux: power-controller@80150 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80150 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "iomux"; + }; + + ps_sbr: power-controller@80100 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aic"; + apple,always-on; /* Core device */ + }; + + ps_gpio: power-controller@80110 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gpio"; + }; + + ps_pcie_down_ref: power-controller@80138 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80138 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_down_ref"; + }; + + ps_pcie_stg0_ref: power-controller@80140 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80140 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_stg0_ref"; + }; + + ps_pcie_stg1_ref: power-controller@80148 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80148 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_stg1_ref"; + }; + + ps_mca0: power-controller@80170 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80170 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca1: power-controller@80178 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80178 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca2: power-controller@80180 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80180 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca3: power-controller@80188 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80188 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca4: power-controller@80190 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80190 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca5: power-controller@80198 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca5"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c0: power-controller@801a8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801b0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801b8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801c0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi0: power-controller@801e0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi1: power-controller@801e8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi2: power-controller@801f0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi3: power-controller@801f8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_pwm0: power-controller@801a0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pwm0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_sio: power-controller@80168 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80168 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio"; + power-domains =3D <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_isp_sens0: power-controller@80120 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80128 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens1"; + }; + + ps_isp_sens2: power-controller@80130 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens2"; + }; + + ps_pms: power-controller@80118 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms"; + apple,always-on; /* Core device */ + }; + + ps_i2c4: power-controller@801c8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c5: power-controller@801d0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c5"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c6: power-controller@801d8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c6"; + power-domains =3D <&ps_sio_p>; + }; + + ps_usb: power-controller@80268 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80268 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb"; + }; + + ps_usbctrl: power-controller@80270 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80270 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbctrl"; + power-domains =3D <&ps_usb>; + }; + + ps_usb2host0: power-controller@80278 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80278 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@80288 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80288 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host1"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_rtmux: power-controller@802a8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "rtmux"; + }; + + ps_media: power-controller@802d8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "media"; + }; + + ps_isp_sys: power-controller@802d0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sys"; + power-domains =3D <&ps_rtmux>; + }; + + ps_msr: power-controller@802e8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "msr"; + power-domains =3D <&ps_media>; + }; + + ps_jpg: power-controller@802e0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "jpg"; + power-domains =3D <&ps_media>; + }; + + ps_disp0_fe: power-controller@802b0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_fe"; + power-domains =3D <&ps_rtmux>; + }; + + ps_disp0_be: power-controller@802b8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_be"; + power-domains =3D <&ps_disp0_fe>; + }; + + ps_uart0: power-controller@80200 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80200 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart1: power-controller@80208 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80208 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart2: power-controller@80210 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80210 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart3: power-controller@80218 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80218 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart4: power-controller@80220 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80220 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_dpa: power-controller@80228 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80228 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dpa"; + power-domains =3D <&ps_sio_p>; + }; + + ps_hfd0: power-controller@80230 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80230 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hfd0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mcc: power-controller@80240 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80240 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80248 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80248 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80250 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80250 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80258 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80258 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs2"; + /* Not used on some devicecs, to be disabled by loader */ + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80260 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs3"; + /* Not used on some devicecs, to be disabled by loader */ + apple,always-on; /* LPDDR4 interface */ + }; + + ps_usb2host0_ohci: power-controller@80280 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80280 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0_ohci"; + power-domains =3D <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@80290 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80290 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbotg"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_smx: power-controller@80298 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80298 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802a0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mipi_dsi: power-controller@802c8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mipi_dsi"; + power-domains =3D <&ps_disp0_be>; + }; + + ps_pmp: power-controller@802f0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pmp"; + }; + + ps_pms_sram: power-controller@802f8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms_sram"; + }; + + ps_pcie_up_af: power-controller@80320 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80320 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_up_af"; + power-domains =3D <&ps_iomux>; + }; + + ps_pcie_up: power-controller@80328 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80328 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_up"; + power-domains =3D <&ps_pcie_up_af>; + }; + + ps_venc_sys: power-controller@80300 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80300 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_sys"; + power-domains =3D <&ps_media>; + }; + + ps_ans2: power-controller@80308 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80308 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ans2"; + power-domains =3D <&ps_iomux>; + }; + + ps_pcie_down: power-controller@80310 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80310 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_down"; + power-domains =3D <&ps_iomux>; + }; + + ps_pcie_down_aux: power-controller@80318 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80318 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_down_aux"; + }; + + ps_pcie_up_aux: power-controller@80330 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80330 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_up_aux"; + power-domains =3D <&ps_pcie_up>; + }; + + ps_pcie_stg0: power-controller@80338 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80338 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_stg0"; + power-domains =3D <&ps_ans2>; + }; + + ps_pcie_stg0_aux: power-controller@80340 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80340 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_stg0_aux"; + }; + + ps_pcie_stg1: power-controller@80348 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80348 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_stg1"; + power-domains =3D <&ps_ans2>; + }; + + ps_pcie_stg1_aux: power-controller@80350 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80350 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_stg1_aux"; + }; + + ps_sep: power-controller@80400 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80400 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sep"; + apple,always-on; /* Locked on */ + }; + + ps_isp_rsts0: power-controller@84000 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_rsts0"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_rsts1: power-controller@84008 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_rsts1"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_vis: power-controller@84010 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_vis"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_be: power-controller@84018 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_be"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_isp_pearl: power-controller@84020 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x84020 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_pearl"; + power-domains =3D <&ps_isp_sys>; + }; + + ps_venc_pipe4: power-controller@88000 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe4"; + }; + + ps_venc_pipe5: power-controller@88008 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe5"; + }; + + ps_venc_me0: power-controller@88010 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me0"; + }; + + ps_venc_me1: power-controller@88018 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me1"; + }; +}; + +&pmgr_mini { + ps_spmi: power-controller@80058 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80058 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spmi"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_aon: power-controller@80060 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80060 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "nub_aon"; + apple,always-on; /* Core AON device */ + }; + + ps_smc_fabric: power-controller@80030 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80030 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smc_fabric"; + apple,always-on; /* Core AON device */ + }; + + ps_smc_aon: power-controller@80088 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80088 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smc_aon"; + apple,always-on; /* Core AON device */ + }; + + ps_debug: power-controller@80050 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80050 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "debug"; + }; + + ps_nub_sram: power-controller@801a0 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "nub_sram"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_fabric: power-controller@80198 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "nub_fabric"; + apple,always-on; /* Core AON device */ + }; + + ps_smc_cpu: power-controller@801a8 { + compatible =3D "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smc_cpu"; + power-domains =3D <&ps_smc_fabric &ps_smc_aon>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8012-touchbar.dtsi b/arch/arm64/boo= t/dts/apple/t8012-touchbar.dtsi index f4a8b12437f0..fc4a80d0c787 100644 --- a/arch/arm64/boot/dts/apple/t8012-touchbar.dtsi +++ b/arch/arm64/boot/dts/apple/t8012-touchbar.dtsi @@ -12,6 +12,7 @@ chosen { framebuffer0: framebuffer@0 { compatible =3D "apple,simple-framebuffer", "simple-framebuffer"; reg =3D <0 0 0 0>; /* To be filled by loader */ + power-domains =3D <&ps_disp0_fe &ps_disp0_be &ps_mipi_dsi>; /* Format properties will be added by loader */ status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/apple/t8012.dtsi b/arch/arm64/boot/dts/app= le/t8012.dtsi index 45d24ca091b0..907ba127be79 100644 --- a/arch/arm64/boot/dts/apple/t8012.dtsi +++ b/arch/arm64/boot/dts/apple/t8012.dtsi @@ -61,19 +61,30 @@ serial0: serial@20a600000 { /* Use the bootloader-enabled clocks for now. */ clocks =3D <&clkref>, <&clkref>; clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart0>; status =3D "disabled"; }; =20 + pmgr: power-management@20e000000 { + compatible =3D "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0xe000000 0 0x8c000>; + }; + aic: interrupt-controller@20e100000 { compatible =3D "apple,t8010-aic", "apple,aic"; reg =3D <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells =3D <3>; interrupt-controller; + power-domains =3D <&ps_aic>; }; =20 pinctrl_ap: pinctrl@20f100000 { compatible =3D "apple,t8010-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x0f100000 0x0 0x100000>; + power-domains =3D <&ps_gpio>; =20 gpio-controller; #gpio-cells =3D <2>; @@ -130,6 +141,14 @@ pinctrl_nub: pinctrl@2111f0000 { ; }; =20 + pmgr_mini: power-management@211200000 { + compatible =3D "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0x11200000 0 0x84000>; + }; + wdt: watchdog@2112b0000 { compatible =3D "apple,t8010-wdt", "apple,wdt"; reg =3D <0x2 0x112b0000 0x0 0x4000>; @@ -141,6 +160,7 @@ wdt: watchdog@2112b0000 { pinctrl_smc: pinctrl@212024000 { compatible =3D "apple,t8010-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x12024000 0x0 0x1000>; + power-domains =3D <&ps_smc_cpu>; =20 gpio-controller; #gpio-cells =3D <2>; @@ -174,3 +194,5 @@ timer { ; }; }; + +#include "t8012-pmgr.dtsi" --=20 2.47.1