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Sat, 30 Nov 2024 16:47:42 -0500 (EST) From: Celeste Liu Date: Sun, 01 Dec 2024 05:47:13 +0800 Subject: [PATCH] riscv/ptrace: add new regset to get original a0 register Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241201-riscv-new-regset-v1-1-c83c58abcc7b@coelacanthus.name> X-B4-Tracking: v=1; b=H4sIAOCHS2cC/x3MMQqAMAxA0atIZgNt0KFeRRzUxpqlSiIqiHe3O L7h/weMVdigqx5QPsVkywW+rmBex5wYJRYDOWo8OY8qNp+Y+ULlZHxgbClMoaUxuggl25UXuf9 lP7zvB7f1anFiAAAA X-Change-ID: 20241201-riscv-new-regset-d529b952ad0d To: Oleg Nesterov , Paul Walmsley , Palmer Dabbelt , Albert Ou , Eric Biederman , Kees Cook Cc: Alexandre Ghiti , "Dmitry V. Levin" , Andrea Bolognani , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , Thomas Gleixner , Ron Economos , Felix Yan , Ruizhe Pan , Shiqi Zhang , Guo Ren , Yao Zi , Han Gao , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, stable@vger.kernel.org, Celeste Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3224; i=uwu@coelacanthus.name; h=from:subject:message-id; bh=tgFlapvT7VwQsZiO6n4iEi3XFX6DBlZjgTPZF2GhaDs=; b=owJ4nJvAy8zAJeafov85RWVtBeNptSSGdO/27+ejT67U17uYOJXz/fmPjJbrjI9p7nS4Ghh+I OvZwwgJVqeOUhYGMS4GWTFFlrwSlp+cl8527+3Y3gUzh5UJZAgDF6cATOTCe4b/mc2h98Ufndho syS/aQlXObP6vhNPbXcoqUzXOZr2OXAnB8P/4kuX7G7s7O9s/NO72mx2j+n+jpB2o1bBCWsCbxg vF9nGBwChJ0wk X-Developer-Key: i=uwu@coelacanthus.name; a=openpgp; fpr=892EBC7DC392DFF9C9C03F1D15F4180E73787863 The orig_a0 is missing in struct user_regs_struct of riscv, and there is no way to add it without breaking UAPI. (See Link tag below) Like NT_ARM_SYSTEM_CALL do, we add a new regset name NT_RISCV_ORIG_A0 to access original a0 register from userspace via ptrace API. Link: https://lore.kernel.org/all/59505464-c84a-403d-972f-d4b2055eeaac@gmai= l.com/ Signed-off-by: Celeste Liu --- arch/riscv/kernel/ptrace.c | 33 +++++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 2 files changed, 34 insertions(+) diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index ea67e9fb7a583683b922fe2c017ea61f3bc848db..faa46de9000376eb445a32d43a4= 0210d7b846844 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -31,6 +31,7 @@ enum riscv_regset { #ifdef CONFIG_RISCV_ISA_SUPM REGSET_TAGGED_ADDR_CTRL, #endif + REGSET_ORIG_A0, }; =20 static int riscv_gpr_get(struct task_struct *target, @@ -184,6 +185,30 @@ static int tagged_addr_ctrl_set(struct task_struct *ta= rget, } #endif =20 +static int riscv_orig_a0_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + return membuf_store(&to, task_pt_regs(target)->orig_a0); +} + +static int riscv_orig_a0_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int orig_a0 =3D task_pt_regs(target)->orig_a0; + int ret; + + ret =3D user_regset_copyin(&pos, &count, &kbuf, &ubuf, &orig_a0, 0, -1); + if (ret) + return ret; + + task_pt_regs(target)->orig_a0 =3D orig_a0; + return ret; +} + + static const struct user_regset riscv_user_regset[] =3D { [REGSET_X] =3D { .core_note_type =3D NT_PRSTATUS, @@ -224,6 +249,14 @@ static const struct user_regset riscv_user_regset[] = =3D { .set =3D tagged_addr_ctrl_set, }, #endif + [REGSET_ORIG_A0] =3D { + .core_note_type =3D NT_RISCV_ORIG_A0, + .n =3D 1, + .size =3D sizeof(elf_greg_t), + .align =3D sizeof(elf_greg_t), + .regset_get =3D riscv_orig_a0_get, + .set =3D riscv_orig_a0_set, + }, }; =20 static const struct user_regset_view riscv_user_native_view =3D { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index b44069d29cecc0f9de90ee66bfffd2137f4275a8..390060229601631da2fb27030d9= fa2142e676c14 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -452,6 +452,7 @@ typedef struct elf64_shdr { #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ #define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (= prctl()) */ +#define NT_RISCV_ORIG_A0 0x903 /* RISC-V original a0 register */ #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension regist= ers */ --- base-commit: 0e287d31b62bb53ad81d5e59778384a40f8b6f56 change-id: 20241201-riscv-new-regset-d529b952ad0d Best regards, --=20 Celeste Liu