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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241130-fix-board-clocks-v2-20-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2648; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=7OHCCY/C9Gi+J8yjNBu9jXr2t5pH4lXuG676E3PqyrQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm32u9te1Qpn5Qa9ML35WLzEI1r0Xn/Ay2PZV nezXo95cqeJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9gAKCRCLPIo+Aiko 1c41B/0TGGROPMQI5cFxBBrL+cOETVbJVXbve1qsZlcI88uOjKk4+WJJ40C4Is1ozIi9LEdtUWb UdvQ13lTw/wNECHJ+i3Dsy/HL8+GwfTvemGlrb9ZbTP4bBswkuxygCIj526qWpTl1yycXLty+Og wVh/aus15bo/QYD2K81AztGzmRhYPsoQcfbzSYiFf4IdurIxUELGW6QwkxzApLXqHV0KQt+YDw5 yrUO/ZjEM1tTJGNahFwdp7udfKnVn+Ggc3CJ4FqNpjgM7XLBam9mHBx5mXcWaRY+ya5/pcxWheU UA3D2RXp5P5Nh6XbXScyKlF9okMbuQ7bjWRziSvjVuU1YcfH X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A IPQ5018 is one of the platforms where board-level clocks (XO, sleep) definitions are split between the SoC dtsi file and the board file. This is not optimal, as the clocks are a part of the SoC + PMICs design. Frequencies are common for the whole set of devices using the same SoC. Remove the split and move frequencies to the SoC DTSI file. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 8 -------- arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts | 8 -------- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 2 ++ 3 files changed, 2 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/bo= ot/dts/qcom/ipq5018-rdp432-c2.dts index 8460b538eb6a3e2d6b971bd9637309809e0c0f0c..9bb87b7fd25777d4ba13bd2bb36= 024b8035d8afd 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -38,10 +38,6 @@ &sdhc_1 { status =3D "okay"; }; =20 -&sleep_clk { - clock-frequency =3D <32000>; -}; - &tlmm { sdc_default_state: sdc-default-state { clk-pins { @@ -78,7 +74,3 @@ &usb_dwc { &usbphy0 { status =3D "okay"; }; - -&xo_board_clk { - clock-frequency =3D <24000000>; -}; diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/a= rch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts index 5bb021cb29cd39cb95035bfac1bdbc976439838b..af281c285447f9845f542cc9d97= 6fcdc7f1cf766 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts @@ -95,10 +95,6 @@ &blsp1_uart1 { status =3D "okay"; }; =20 -&sleep_clk { - clock-frequency =3D <32000>; -}; - &tlmm { button_pins: button-pins-state { pins =3D "gpio25", "gpio31"; @@ -122,7 +118,3 @@ uart_pins: uart-pins-state { bias-disable; }; }; - -&xo_board_clk { - clock-frequency =3D <24000000>; -}; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 8914f2ef0bc47fda243b19174f77ce73fc10757d..fe617e9a086e6541854e03bd1f0= a6519079befed 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -19,11 +19,13 @@ clocks { sleep_clk: sleep-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; + clock-frequency =3D <32000>; }; =20 xo_board_clk: xo-board-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; + clock-frequency =3D <24000000>; }; }; =20 --=20 2.39.5