From nobody Thu Dec 26 11:44:12 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 961DA1A0B04; Fri, 29 Nov 2024 18:22:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732904573; cv=none; b=RL+WZMS+zWluGc7yhMPYErZ3XmUY4RQ5x88cqYaZx8JfBlXsTICt3kK7wQhiOn+nb2P3YxtnkYhxX5y+pvTsrz1E3QBM/uDjeTBFK9fRLTgJ7sUnFmDYe/kzSiiF5M92FIHdPbychzMNe5GZ/QYyZcwCM+NPLR1qLz2oDBDQh8Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732904573; c=relaxed/simple; bh=LYd2Z7bHeCCWjN/Q2ZNdswf4Q7BqSo9TVw8fJ8XD6jg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oKdhUyj2Dmd6RGnLZSaK1O7b0cmB/gqc0O6Kah6lrmHEI7kXuY+OQToauuYHJJUgGte7dh7cPTirfOlmRe5vTkCVDL8QTM/sAEFPJkFTxJ9LMPxdsQbb9MCof1DBesGykEolsqCFzKsLW6SkAyhcurZH9Va1XSnP5G2Qidf+/Vs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kw5XFExZ; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kw5XFExZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732904572; x=1764440572; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LYd2Z7bHeCCWjN/Q2ZNdswf4Q7BqSo9TVw8fJ8XD6jg=; b=kw5XFExZNxRgGuzNNGI5R+0/ez5IR6WE/kBSQQ0tmc9L6RAU4Ea8qlzR kjMaOrYWQFYzD36v0oVBfpypJt1ZXW7vlscWd9KuhOfRfJ7pgOLG4NK7d kJ9kgHjKC/s/AR+wjU1ePCm2FHJPyScqoOio4yTiUbO+C753a+GLCE/0w n7z6DeZBhUxLS0Mm9iKF4OyyFoXwGnzdp1VWODAmGjXmJ9JP6pGc9DVQr TZCKbqD6T76FgMdk5S/K+98Uy//CB7AZDkassjIflvgMAQ5NVsesMNVkb JuYmftwX/Hw9aDr6NTE0G5TjS5HeCN7zXh9FQd/1U/w05Jaj094+SUWak w==; X-CSE-ConnectionGUID: znKuqCo5SgmU0QJbC+FhqQ== X-CSE-MsgGUID: TXXWd0YwQDGpN7712O1DMA== X-IronPort-AV: E=McAfee;i="6700,10204,11271"; a="36811941" X-IronPort-AV: E=Sophos;i="6.12,196,1728975600"; d="scan'208";a="36811941" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2024 10:22:51 -0800 X-CSE-ConnectionGUID: bbwd57osQEKlHH8c28PZVg== X-CSE-MsgGUID: ce4C+h0AQ0iyZhemcpderg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,196,1728975600"; d="scan'208";a="92422113" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost.localdomain) ([10.245.245.203]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2024 10:22:48 -0800 From: Patryk Wlazlyn To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, rafael.j.wysocki@intel.com, peterz@infradead.org, dave.hansen@linux.intel.com, gautham.shenoy@amd.com, tglx@linutronix.de, len.brown@intel.com, artem.bityutskiy@linux.intel.com, patryk.wlazlyn@linux.intel.com Subject: [PATCH v7 1/4] x86/smp: Allow calling mwait_play_dead with an arbitrary hint Date: Fri, 29 Nov 2024 19:22:29 +0100 Message-ID: <20241129182232.14987-2-patryk.wlazlyn@linux.intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241129182232.14987-1-patryk.wlazlyn@linux.intel.com> References: <20241129182232.14987-1-patryk.wlazlyn@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a helper function to allow offlined CPUs to enter FFh idle states with a specific MWAIT hint. The new helper will be used in subsequent patches by the acpi_idle and intel_idle drivers. No functional change intended. Signed-off-by: Patryk Wlazlyn Reviewed-by: Gautham R. Shenoy --- arch/x86/include/asm/smp.h | 3 ++ arch/x86/kernel/smpboot.c | 90 ++++++++++++++++++++------------------ 2 files changed, 51 insertions(+), 42 deletions(-) diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index ca073f40698f..dfd09a1e09bf 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -114,6 +114,7 @@ void wbinvd_on_cpu(int cpu); int wbinvd_on_all_cpus(void); =20 void smp_kick_mwait_play_dead(void); +void mwait_play_dead(unsigned int hint); =20 void native_smp_send_reschedule(int cpu); void native_send_call_func_ipi(const struct cpumask *mask); @@ -164,6 +165,8 @@ static inline struct cpumask *cpu_llc_shared_mask(int c= pu) { return (struct cpumask *)cpumask_of(0); } + +static inline void mwait_play_dead(unsigned int eax_hint) { } #endif /* CONFIG_SMP */ =20 #ifdef CONFIG_DEBUG_NMI_SELFTEST diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index b5a8f0891135..8a3545c2cae9 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1272,13 +1272,57 @@ void play_dead_common(void) local_irq_disable(); } =20 +void __noreturn mwait_play_dead(unsigned int eax_hint) +{ + struct mwait_cpu_dead *md =3D this_cpu_ptr(&mwait_cpu_dead); + + /* Set up state for the kexec() hack below */ + md->status =3D CPUDEAD_MWAIT_WAIT; + md->control =3D CPUDEAD_MWAIT_WAIT; + + wbinvd(); + + while (1) { + /* + * The CLFLUSH is a workaround for erratum AAI65 for + * the Xeon 7400 series. It's not clear it is actually + * needed, but it should be harmless in either case. + * The WBINVD is insufficient due to the spurious-wakeup + * case where we return around the loop. + */ + mb(); + clflush(md); + mb(); + __monitor(md, 0, 0); + mb(); + __mwait(eax_hint, 0); + + if (READ_ONCE(md->control) =3D=3D CPUDEAD_MWAIT_KEXEC_HLT) { + /* + * Kexec is about to happen. Don't go back into mwait() as + * the kexec kernel might overwrite text and data including + * page tables and stack. So mwait() would resume when the + * monitor cache line is written to and then the CPU goes + * south due to overwritten text, page tables and stack. + * + * Note: This does _NOT_ protect against a stray MCE, NMI, + * SMI. They will resume execution at the instruction + * following the HLT instruction and run into the problem + * which this is trying to prevent. + */ + WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); + while(1) + native_halt(); + } + } +} + /* * We need to flush the caches before going to sleep, lest we have * dirty data in our caches when we come back up. */ -static inline void mwait_play_dead(void) +static inline void mwait_play_dead_cpuid_hint(void) { - struct mwait_cpu_dead *md =3D this_cpu_ptr(&mwait_cpu_dead); unsigned int eax, ebx, ecx, edx; unsigned int highest_cstate =3D 0; unsigned int highest_subcstate =3D 0; @@ -1316,45 +1360,7 @@ static inline void mwait_play_dead(void) (highest_subcstate - 1); } =20 - /* Set up state for the kexec() hack below */ - md->status =3D CPUDEAD_MWAIT_WAIT; - md->control =3D CPUDEAD_MWAIT_WAIT; - - wbinvd(); - - while (1) { - /* - * The CLFLUSH is a workaround for erratum AAI65 for - * the Xeon 7400 series. It's not clear it is actually - * needed, but it should be harmless in either case. - * The WBINVD is insufficient due to the spurious-wakeup - * case where we return around the loop. - */ - mb(); - clflush(md); - mb(); - __monitor(md, 0, 0); - mb(); - __mwait(eax, 0); - - if (READ_ONCE(md->control) =3D=3D CPUDEAD_MWAIT_KEXEC_HLT) { - /* - * Kexec is about to happen. Don't go back into mwait() as - * the kexec kernel might overwrite text and data including - * page tables and stack. So mwait() would resume when the - * monitor cache line is written to and then the CPU goes - * south due to overwritten text, page tables and stack. - * - * Note: This does _NOT_ protect against a stray MCE, NMI, - * SMI. They will resume execution at the instruction - * following the HLT instruction and run into the problem - * which this is trying to prevent. - */ - WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); - while(1) - native_halt(); - } - } + mwait_play_dead(eax); } =20 /* @@ -1407,7 +1413,7 @@ void native_play_dead(void) play_dead_common(); tboot_shutdown(TB_SHUTDOWN_WFS); =20 - mwait_play_dead(); + mwait_play_dead_cpuid_hint(); if (cpuidle_play_dead()) hlt_play_dead(); } --=20 2.47.1 From nobody Thu Dec 26 11:44:12 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0641E1A2554; Fri, 29 Nov 2024 18:22:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732904576; cv=none; b=LYIW/yKDnoL4puhrTmphLXUKCbn8kZk/ygd0AHYEgtVTmMX9kwNwLf8sEMuRBhErmPDEsPWQYZtXUS1z+jRXMp7MEKhpvLMSdYI9YQPtgsGlOQ2gcH1fGE1gBrBolcU0R+Ru6bm09pMnZo+X7NjY5V75TvCT5d6Fu07L/yoEb38= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732904576; c=relaxed/simple; bh=kMW48E7qpSBZTt1YOx6YAvCT+CU+LS/A1l7cEYEL4ig=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TqxoqWIvHygCPNGMJ3I9qTv2PvX5G9vE+3m76IJNFvjKftUDl1w6Xjb4rL6QJtCF5t6hh/22g/mbDVC67jY+vs/tswTlF901DlfZ/F/W3OReTE4yaLZOusgnOLjWPnQ3vDHxDRWyRvzUIbv6GEC+Bwic1ykc/DlxYU0rW1B1sK8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hCKqoEQr; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hCKqoEQr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732904575; x=1764440575; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kMW48E7qpSBZTt1YOx6YAvCT+CU+LS/A1l7cEYEL4ig=; b=hCKqoEQrYczc3iDxEjSU487tgXpB/F1ZNhp90lqVdKSjYDkJUIkUcjUV 2leQGE/3v97fmX4fvlvhxIJnzISnfhSQI9t8GruUjNLIYZM51nuZZiwt2 HTPpiFjT6BKNUQ7TLthykYl1yLnsSTVSOiOiWAfS+FCroTe3rrAVILut4 fux6EST15ZnVHxpYPsQhMp0d30EK1moJgp1LpDsdCqmuntxSXNrgo+yiV TrJ9V3pqDZF55t1/lIm+1ZEzHnw7uHp9AvieuNS7pXSOqSiwTtA3qppMh fEHGW0iHXqaLeWSIhqO8z83OQfRWFGQmRl3zHRL66pyGkNvFNYp2/IWt3 Q==; X-CSE-ConnectionGUID: fyuifrI6Rbaj7dGbOYqchg== X-CSE-MsgGUID: Z3AAukgOTsOkYi3ixdLavw== X-IronPort-AV: E=McAfee;i="6700,10204,11271"; a="36811948" X-IronPort-AV: E=Sophos;i="6.12,196,1728975600"; d="scan'208";a="36811948" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2024 10:22:55 -0800 X-CSE-ConnectionGUID: /hvGRJtATnesQn6vlP80yg== X-CSE-MsgGUID: 1+2PbXy6RWe/69G50FESgQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,196,1728975600"; d="scan'208";a="92422149" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost.localdomain) ([10.245.245.203]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2024 10:22:52 -0800 From: Patryk Wlazlyn To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, rafael.j.wysocki@intel.com, peterz@infradead.org, dave.hansen@linux.intel.com, gautham.shenoy@amd.com, tglx@linutronix.de, len.brown@intel.com, artem.bityutskiy@linux.intel.com, patryk.wlazlyn@linux.intel.com Subject: [PATCH v7 2/4] ACPI: processor_idle: Add FFH state handling Date: Fri, 29 Nov 2024 19:22:30 +0100 Message-ID: <20241129182232.14987-3-patryk.wlazlyn@linux.intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241129182232.14987-1-patryk.wlazlyn@linux.intel.com> References: <20241129182232.14987-1-patryk.wlazlyn@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Recent Intel platforms will depend on the idle driver to pass the correct hint for playing dead via mwait_play_dead_with_hint(). Expand the existing enter_dead interface with handling for FFH states and pass the MWAIT hint to the mwait_play_dead code. Signed-off-by: Patryk Wlazlyn Suggested-by: Gautham R. Shenoy Reviewed-by: Gautham R. Shenoy --- arch/x86/kernel/acpi/cstate.c | 10 ++++++++++ drivers/acpi/processor_idle.c | 2 ++ include/acpi/processor.h | 5 +++++ 3 files changed, 17 insertions(+) diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c index f3ffd0a3a012..8d7b8b02ddb9 100644 --- a/arch/x86/kernel/acpi/cstate.c +++ b/arch/x86/kernel/acpi/cstate.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 /* * Initialize bm_flags based on the CPU cache properties @@ -204,6 +205,15 @@ int acpi_processor_ffh_cstate_probe(unsigned int cpu, } EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe); =20 +void acpi_processor_ffh_play_dead(struct acpi_processor_cx *cx) +{ + unsigned int cpu =3D smp_processor_id(); + struct cstate_entry *percpu_entry; + + percpu_entry =3D per_cpu_ptr(cpu_cstate_entry, cpu); + mwait_play_dead(percpu_entry->states[cx->index].eax); +} + void __cpuidle acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *c= x) { unsigned int cpu =3D smp_processor_id(); diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index ce728cf7e301..83213fa47c1b 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -590,6 +590,8 @@ static void acpi_idle_play_dead(struct cpuidle_device *= dev, int index) raw_safe_halt(); else if (cx->entry_method =3D=3D ACPI_CSTATE_SYSTEMIO) { io_idle(cx->address); + } else if (cx->entry_method =3D=3D ACPI_CSTATE_FFH) { + acpi_processor_ffh_play_dead(cx); } else return; } diff --git a/include/acpi/processor.h b/include/acpi/processor.h index a17e97e634a6..63a37e72b721 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -280,6 +280,7 @@ int acpi_processor_ffh_cstate_probe(unsigned int cpu, struct acpi_processor_cx *cx, struct acpi_power_register *reg); void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cstate); +void acpi_processor_ffh_play_dead(struct acpi_processor_cx *cx); #else static inline void acpi_processor_power_init_bm_check(struct acpi_processor_flags @@ -300,6 +301,10 @@ static inline void acpi_processor_ffh_cstate_enter(str= uct acpi_processor_cx { return; } +static inline void acpi_processor_ffh_play_dead(struct acpi_processor_cx *= cx) +{ + return; +} #endif =20 static inline int call_on_cpu(int cpu, long (*fn)(void *), void *arg, --=20 2.47.1 From nobody Thu Dec 26 11:44:12 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C09F1A2C0E; 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charset="utf-8" Recent Intel platforms require idle driver to provide information about the MWAIT hint used to enter the deepest idle state in the play_dead code. Provide the default enter_dead() handler for all of the platforms and allow overwriting with a custom handler for each platform if needed. Signed-off-by: Patryk Wlazlyn --- drivers/idle/intel_idle.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index ac4d8faa3886..c6874a6dbe95 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -56,6 +56,7 @@ #include #include #include +#include =20 #define INTEL_IDLE_VERSION "0.5.1" =20 @@ -227,6 +228,16 @@ static __cpuidle int intel_idle_s2idle(struct cpuidle_= device *dev, return 0; } =20 +static __cpuidle void intel_idle_enter_dead(struct cpuidle_device *dev, + int index) +{ + struct cpuidle_driver *drv =3D cpuidle_get_cpu_driver(dev); + struct cpuidle_state *state =3D &drv->states[index]; + unsigned long eax =3D flg2MWAIT(state->flags); + + mwait_play_dead(eax); +} + /* * States are indexed by the cstate number, * which is also the index into the MWAIT hint array. @@ -1798,6 +1809,7 @@ static void __init intel_idle_init_cstates_acpi(struc= t cpuidle_driver *drv) state->flags |=3D CPUIDLE_FLAG_TIMER_STOP; =20 state->enter =3D intel_idle; + state->enter_dead =3D intel_idle_enter_dead; state->enter_s2idle =3D intel_idle_s2idle; } } @@ -2143,10 +2155,12 @@ static void __init intel_idle_init_cstates_icpu(str= uct cpuidle_driver *drv) if (intel_idle_max_cstate_reached(cstate)) break; =20 - if (!cpuidle_state_table[cstate].enter && - !cpuidle_state_table[cstate].enter_s2idle) + if (!cpuidle_state_table[cstate].enter) break; =20 + if (!cpuidle_state_table[cstate].enter_dead) + cpuidle_state_table[cstate].enter_dead =3D intel_idle_enter_dead; + /* If marked as unusable, skip this state. */ if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_UNUSABLE) { pr_debug("state %s is disabled\n", --=20 2.47.1 From nobody Thu Dec 26 11:44:12 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EB611A3AAD; Fri, 29 Nov 2024 18:23:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="36811968" X-IronPort-AV: E=Sophos;i="6.12,196,1728975600"; d="scan'208";a="36811968" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2024 10:23:01 -0800 X-CSE-ConnectionGUID: YfFSxJCRScO2yNseuMymEA== X-CSE-MsgGUID: OaGZ7WSaSMyMK4MLiUcLqg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,196,1728975600"; d="scan'208";a="92422167" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost.localdomain) ([10.245.245.203]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2024 10:22:58 -0800 From: Patryk Wlazlyn To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, rafael.j.wysocki@intel.com, peterz@infradead.org, dave.hansen@linux.intel.com, gautham.shenoy@amd.com, tglx@linutronix.de, len.brown@intel.com, artem.bityutskiy@linux.intel.com, patryk.wlazlyn@linux.intel.com Subject: [PATCH v7 4/4] x86/smp native_play_dead: Prefer cpuidle_play_dead() over mwait_play_dead() Date: Fri, 29 Nov 2024 19:22:32 +0100 Message-ID: <20241129182232.14987-5-patryk.wlazlyn@linux.intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241129182232.14987-1-patryk.wlazlyn@linux.intel.com> References: <20241129182232.14987-1-patryk.wlazlyn@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current algorithm* for looking up the mwait hint for the deepest cstate, in mwait_play_dead() code works by inspecting CPUID leaf 0x5 and calculates the mwait hint based on the number of reported substates. This approach depends on the hints associated with them to be continuous in the range [0, NUM_SUBSTATES-1]. This continuity is not documented and is not met on the recent Intel platforms. * The current algorithm is implemented in the for loop inspecting edx in mwait_play_dead(). For example, Intel's Sierra Forest report two cstates with two substates each in cpuid leaf 0x5: Name* target cstate target subcstate (mwait hint) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D C1 0x00 0x00 C1E 0x00 0x01 -- 0x10 ---- C6S 0x20 0x22 C6P 0x20 0x23 -- 0x30 ---- /* No more (sub)states all the way down to the end. */ =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D * Names of the cstates are not included in the CPUID leaf 0x5, they are taken from the product specific documentation. Notice that hints 0x20 and 0x21 are skipped entirely for the target cstate 0x20 (C6), being a cause of the problem for the current cpuid leaf 0x5 algorithm. Remove the old implementation of play_dead MWAIT hint calculation based on the CPUID leaf 0x5 in mwait_play_dead() and delegate calling of the mwait_play_dead_with_hint() to the idle driver. Signed-off-by: Patryk Wlazlyn Reviewed-by: Gautham R. Shenoy --- arch/x86/kernel/smpboot.c | 56 +++++---------------------------------- 1 file changed, 7 insertions(+), 49 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 8a3545c2cae9..82801137486d 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1272,6 +1272,10 @@ void play_dead_common(void) local_irq_disable(); } =20 +/* + * We need to flush the caches before going to sleep, lest we have + * dirty data in our caches when we come back up. + */ void __noreturn mwait_play_dead(unsigned int eax_hint) { struct mwait_cpu_dead *md =3D this_cpu_ptr(&mwait_cpu_dead); @@ -1317,52 +1321,6 @@ void __noreturn mwait_play_dead(unsigned int eax_hin= t) } } =20 -/* - * We need to flush the caches before going to sleep, lest we have - * dirty data in our caches when we come back up. - */ -static inline void mwait_play_dead_cpuid_hint(void) -{ - unsigned int eax, ebx, ecx, edx; - unsigned int highest_cstate =3D 0; - unsigned int highest_subcstate =3D 0; - int i; - - if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD || - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) - return; - if (!this_cpu_has(X86_FEATURE_MWAIT)) - return; - if (!this_cpu_has(X86_FEATURE_CLFLUSH)) - return; - if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) - return; - - eax =3D CPUID_MWAIT_LEAF; - ecx =3D 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - - /* - * eax will be 0 if EDX enumeration is not valid. - * Initialized below to cstate, sub_cstate value when EDX is valid. - */ - if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { - eax =3D 0; - } else { - edx >>=3D MWAIT_SUBSTATE_SIZE; - for (i =3D 0; i < 7 && edx; i++, edx >>=3D MWAIT_SUBSTATE_SIZE) { - if (edx & MWAIT_SUBSTATE_MASK) { - highest_cstate =3D i; - highest_subcstate =3D edx & MWAIT_SUBSTATE_MASK; - } - } - eax =3D (highest_cstate << MWAIT_SUBSTATE_SIZE) | - (highest_subcstate - 1); - } - - mwait_play_dead(eax); -} - /* * Kick all "offline" CPUs out of mwait on kexec(). See comment in * mwait_play_dead(). @@ -1413,9 +1371,9 @@ void native_play_dead(void) play_dead_common(); tboot_shutdown(TB_SHUTDOWN_WFS); =20 - mwait_play_dead_cpuid_hint(); - if (cpuidle_play_dead()) - hlt_play_dead(); + /* Below returns only on error. */ + cpuidle_play_dead(); + hlt_play_dead(); } =20 #else /* ... !CONFIG_HOTPLUG_CPU */ --=20 2.47.1