From nobody Thu Dec 26 15:26:17 2024 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 640681B95B for ; Fri, 29 Nov 2024 16:23:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732897386; cv=none; b=NBFLFeyiJ+5CnaqkeXH0dgJ6MIViwdxSHZd2xODmY7uLiMTcnYXf/mcTb+sic4wXG3BJssl7Ox6ItbTFvIYxEJiJMdpKiG04xDH6A81PXbAFj0b1GIRvrP43OgY7pSMEHaYslEqgh1/j8OkNq8PHIAlnxi6axcXjdcYFPevoTg0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732897386; c=relaxed/simple; bh=zzLfsOZGNd/bGy0NzCKpAp6U4D+u26d3cpbqhqEL30k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X1BaBxzJrWB6cLxzW+QW2E7eROChbu2CauEyTHxWtRTVjL9FyPTTeRBQhnuYjaAArqBeUoOwy5awcWqt5DJEM7imeh2ii/ou2WrOxM1pFdkrRzNQfLeCb2lZrrNVMd7RqpFhiHCPz8mTESktBGvZEWEJOAA+PhPD517rPysJcu0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=QKELbSkc; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="QKELbSkc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1732897384; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rErA3iZ6143HQltGFMlYu6o31C59/zsAsAqnyNO9lis=; b=QKELbSkcI7EKz/ZnjgiJfDAYQ5hMLNsbjWPG9TNqNXOnnuteps8GPONLMdV2VhWvsXbPKZ iCKQv5C6GXI6cGZO6D5BTSBcgujRQzW9n8zzf158QN0pQvWVBUWyozUlC5Wu2o4I/Q2vXJ jAl6sAckxx2f9Da0TgxALhipU9+UVTA= Received: from mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-536-8mlKJ0ziMCqNw6mcRe47Fw-1; Fri, 29 Nov 2024 11:22:58 -0500 X-MC-Unique: 8mlKJ0ziMCqNw6mcRe47Fw-1 X-Mimecast-MFC-AGG-ID: 8mlKJ0ziMCqNw6mcRe47Fw Received: from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 3C20D1936CCB; Fri, 29 Nov 2024 16:22:54 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.39.192.13]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id C4DEC1955F2F; Fri, 29 Nov 2024 16:22:50 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , David Airlie , Simona Vetter , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH 1/5] drm/i915/fbdev: Add intel_fbdev_getvaddr() Date: Fri, 29 Nov 2024 17:20:26 +0100 Message-ID: <20241129162232.7594-2-jfalempe@redhat.com> In-Reply-To: <20241129162232.7594-1-jfalempe@redhat.com> References: <20241129162232.7594-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Content-Type: text/plain; charset="utf-8" The vaddr of the fbdev framebuffer is private to the struct intel_fbdev, so this function is needed to access it for drm_panic. Signed-off-by: Jocelyn Falempe --- drivers/gpu/drm/i915/display/intel_fbdev.c | 5 +++++ drivers/gpu/drm/i915/display/intel_fbdev.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i= 915/display/intel_fbdev.c index 00852ff5b2470..9f4acc2d75601 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -695,3 +695,8 @@ struct intel_framebuffer *intel_fbdev_framebuffer(struc= t intel_fbdev *fbdev) =20 return to_intel_framebuffer(fbdev->helper.fb); } + +void *intel_fbdev_getvaddr(struct intel_fbdev *fbdev) +{ + return READ_ONCE(fbdev->vma->iomap); +} diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.h b/drivers/gpu/drm/i= 915/display/intel_fbdev.h index 08de2d5b34338..014fa5896af52 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.h +++ b/drivers/gpu/drm/i915/display/intel_fbdev.h @@ -17,6 +17,7 @@ struct intel_framebuffer; void intel_fbdev_setup(struct drm_i915_private *dev_priv); void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synch= ronous); struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbde= v); +void *intel_fbdev_getvaddr(struct intel_fbdev *fbdev); #else static inline void intel_fbdev_setup(struct drm_i915_private *dev_priv) { @@ -30,6 +31,10 @@ static inline struct intel_framebuffer *intel_fbdev_fram= ebuffer(struct intel_fbd { return NULL; } +static inline void *intel_fbdev_getvaddr(struct intel_fbdev *fbdev) +{ + return NULL; +} #endif =20 #endif /* __INTEL_FBDEV_H__ */ --=20 2.47.0 From nobody Thu Dec 26 15:26:17 2024 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF1E519D064 for ; Fri, 29 Nov 2024 16:23:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; 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Fri, 29 Nov 2024 16:22:58 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.39.192.13]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id DEAB91955F3A; Fri, 29 Nov 2024 16:22:54 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , David Airlie , Simona Vetter , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH 2/5] drm/i915/display/i9xx: Add a disable_tiling() for i9xx planes Date: Fri, 29 Nov 2024 17:20:27 +0100 Message-ID: <20241129162232.7594-3-jfalempe@redhat.com> In-Reply-To: <20241129162232.7594-1-jfalempe@redhat.com> References: <20241129162232.7594-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Content-Type: text/plain; charset="utf-8" drm_panic draws in linear framebuffer, so it's easier to re-use the current framebuffer, and disable tiling in the panic handler, to show the panic screen. Signed-off-by: Jocelyn Falempe --- drivers/gpu/drm/i915/display/i9xx_plane.c | 24 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 2 ++ 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i9= 15/display/i9xx_plane.c index 17a1e3801a85c..95a97b91d5cdc 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -848,6 +848,28 @@ static const struct drm_plane_funcs i8xx_plane_funcs = =3D { .format_mod_supported =3D i8xx_plane_format_mod_supported, }; =20 +static void i9xx_disable_tiling(struct intel_plane *plane) +{ + struct drm_i915_private *dev_priv =3D to_i915(plane->base.dev); + enum i9xx_plane_id i9xx_plane =3D plane->i9xx_plane; + struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->bas= e.state); + u32 dspcntr; + + dspcntr =3D intel_de_read_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); + dspcntr &=3D ~DISP_TILED; + intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); + + if (DISPLAY_VER(dev_priv) >=3D 4) { + u32 reg; + + reg =3D intel_de_read_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane)); + intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), reg); + + } else + intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), + intel_plane_ggtt_offset(plane_state)); +} + struct intel_plane * intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pi= pe) { @@ -973,6 +995,8 @@ intel_primary_plane_create(struct drm_i915_private *dev= _priv, enum pipe pipe) plane->disable_flip_done =3D ilk_primary_disable_flip_done; } =20 + plane->disable_tiling =3D i9xx_disable_tiling; + modifiers =3D intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILI= NG_X); =20 if (DISPLAY_VER(dev_priv) >=3D 5 || IS_G4X(dev_priv)) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/g= pu/drm/i915/display/intel_display_types.h index 2bb1fa64da2f1..0559b02569e49 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1482,6 +1482,8 @@ struct intel_plane { bool async_flip); void (*enable_flip_done)(struct intel_plane *plane); void (*disable_flip_done)(struct intel_plane *plane); + /* For drm_panic */ + void (*disable_tiling)(struct intel_plane *plane); }; =20 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state= , base) --=20 2.47.0 From nobody Thu Dec 26 15:26:17 2024 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC5F419CD1B for ; Fri, 29 Nov 2024 16:23:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732897391; cv=none; b=esfcM4eByWMqsWeJlw32bWW8G/4/gGomk5xGE4GoQcS+txkWLECT0rKHUsREIAJw4v8HLk3EgMo8va4lL40c9tM+7zi924j2EqWdeAhCFzSZxraKy4TRwsNYEUcuXdAxaTE2rYBPuTL8TC9nC+gwSgntEPVlGVaKKVA/vUW8Xao= ARC-Message-Signature: i=1; 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charset="utf-8" drm_panic draws in linear framebuffer, so it's easier to re-use the current framebuffer, and disable tiling in the panic handler, to show the panic screen. Signed-off-by: Jocelyn Falempe --- .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/g= pu/drm/i915/display/skl_universal_plane.c index a0a7ed01415a5..62aa40b6e2347 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2560,6 +2560,25 @@ static u8 skl_get_plane_caps(struct drm_i915_private= *i915, return caps; } =20 +static void skl_disable_tiling(struct intel_plane *plane) +{ + u32 plane_ctl; + struct intel_plane_state *state =3D to_intel_plane_state(plane->base.stat= e); + struct drm_i915_private *dev_priv =3D to_i915(plane->base.dev); + u32 stride =3D state->view.color_plane[0].scanout_stride / 64; + + plane_ctl =3D intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane->id)); + plane_ctl &=3D ~PLANE_CTL_TILED_MASK; + + intel_de_write_fw(dev_priv, PLANE_STRIDE(plane->pipe, plane->id), + PLANE_STRIDE_(stride)); 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charset="utf-8" Prepare the work for drm_panic support. They are used to map the current framebuffer, so the CPU can access it, and draws the panic screen. Signed-off-by: Jocelyn Falempe --- drivers/gpu/drm/i915/gem/i915_gem_object.h | 5 +++++ drivers/gpu/drm/i915/gem/i915_gem_pages.c | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i= 915/gem/i915_gem_object.h index 3dc61cbd2e11f..3f99d021f9221 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -694,6 +694,11 @@ i915_gem_object_unpin_pages(struct drm_i915_gem_object= *obj) int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj); int i915_gem_object_truncate(struct drm_i915_gem_object *obj); =20 +void *i915_gem_object_map_page(struct drm_i915_gem_object *obj, + enum i915_map_type type); +void *i915_gem_object_map_pfn(struct drm_i915_gem_object *obj, + enum i915_map_type type); + /** * i915_gem_object_pin_map - return a contiguous mapping of the entire obj= ect * @obj: the object to map into kernel address space diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i9= 15/gem/i915_gem_pages.c index 8780aa2431053..76c023d2fbb1f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -268,7 +268,7 @@ int __i915_gem_object_put_pages(struct drm_i915_gem_obj= ect *obj) } =20 /* The 'mapping' part of i915_gem_object_pin_map() below */ -static void *i915_gem_object_map_page(struct drm_i915_gem_object *obj, +void *i915_gem_object_map_page(struct drm_i915_gem_object *obj, enum i915_map_type type) { unsigned long n_pages =3D obj->base.size >> PAGE_SHIFT, i; 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Fri, 29 Nov 2024 16:23:09 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.39.192.13]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 5140D1955F41; Fri, 29 Nov 2024 16:23:06 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , David Airlie , Simona Vetter , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH 5/5] drm/i915: Add drm_panic support Date: Fri, 29 Nov 2024 17:20:30 +0100 Message-ID: <20241129162232.7594-6-jfalempe@redhat.com> In-Reply-To: <20241129162232.7594-1-jfalempe@redhat.com> References: <20241129162232.7594-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Content-Type: text/plain; charset="utf-8" This adds drm_panic support for a wide range of Intel GPU. I've tested it only on 3 laptops, haswell (with 128MB of eDRAM), cometlake and alderlake. * DPT: if I disable tiling on a framebuffer using DPT, then it displays some other memory location. As DPT is enabled only for tiled framebuffer, there might be some hardware limitations. * fbdev: On my haswell laptop, the fbdev framebuffer is configured with tiling enabled, but really it's linear, because fbcon don't know about tiling, and the panic screen is perfect when it's drawn as linear. Signed-off-by: Jocelyn Falempe --- .../gpu/drm/i915/display/intel_atomic_plane.c | 98 ++++++++++++++++++- 1 file changed, 97 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gp= u/drm/i915/display/intel_atomic_plane.c index b7e462075ded3..43dac5538a648 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -33,13 +33,17 @@ =20 #include #include +#include =20 #include #include +#include #include #include #include +#include =20 +#include "gem/i915_gem_object.h" #include "i915_config.h" #include "i9xx_plane_regs.h" #include "intel_atomic_plane.h" @@ -50,6 +54,7 @@ #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_pin.h" +#include "intel_fbdev.h" #include "skl_scaler.h" #include "skl_watermark.h" =20 @@ -1198,14 +1203,105 @@ intel_cleanup_plane_fb(struct drm_plane *plane, intel_plane_unpin_fb(old_plane_state); } =20 +/* Only used by drm_panic get_scanout_buffer() and panic_flush(), so it is + * protected by the drm panic spinlock + */ +static struct iosys_map panic_map; + +static void intel_panic_flush(struct drm_plane *plane) +{ + struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); + struct drm_i915_private *dev_priv =3D to_i915(plane->dev); + struct drm_framebuffer *fb =3D plane_state->hw.fb; + struct intel_plane *iplane =3D to_intel_plane(plane); + + /* Force a cache flush, otherwise the new pixels won't show up */ + drm_clflush_virt_range(panic_map.vaddr, fb->height * fb->pitches[0]); + + /* Don't disable tiling if it's the fbdev framebuffer.*/ + if (to_intel_framebuffer(fb) =3D=3D intel_fbdev_framebuffer(dev_priv->dis= play.fbdev.fbdev)) + return; + + if (fb->modifier && iplane->disable_tiling) + iplane->disable_tiling(iplane); +} + +static int intel_get_scanout_buffer(struct drm_plane *plane, + struct drm_scanout_buffer *sb) +{ + struct intel_plane_state *plane_state; + struct drm_gem_object *gem_obj; + struct drm_i915_gem_object *obj; + struct drm_framebuffer *fb; + struct drm_i915_private *dev_priv =3D to_i915(plane->dev); + void *ptr; + enum i915_map_type has_type; + + if (!plane->state || !plane->state->fb || !plane->state->visible) + return -ENODEV; + + plane_state =3D to_intel_plane_state(plane->state); + fb =3D plane_state->hw.fb; + gem_obj =3D intel_fb_bo(fb); + if (!gem_obj) + return -ENODEV; + + obj =3D to_intel_bo(gem_obj); + + if (to_intel_framebuffer(fb) =3D=3D intel_fbdev_framebuffer(dev_priv->dis= play.fbdev.fbdev)) { + ptr =3D intel_fbdev_getvaddr(dev_priv->display.fbdev.fbdev); + if (!ptr) + return -ENOMEM; + } else { + /* can't disable tiling if DPT is in use */ + if (fb->modifier && HAS_DPT(dev_priv)) + return -EOPNOTSUPP; + + /* Taken from i915_gem_object_pin_map() */ + ptr =3D page_unpack_bits(obj->mm.mapping, &has_type); + if (!ptr) { + if (i915_gem_object_has_struct_page(obj)) + ptr =3D i915_gem_object_map_page(obj, I915_MAP_WB); + else + ptr =3D i915_gem_object_map_pfn(obj, I915_MAP_WB); + if (IS_ERR(ptr)) + return -ENOMEM; + } + } + + if (i915_gem_object_has_iomem(obj)) + iosys_map_set_vaddr_iomem(&panic_map, ptr); + else + iosys_map_set_vaddr(&panic_map, ptr); + + sb->map[0] =3D panic_map; + sb->width =3D fb->width; + sb->height =3D fb->height; + sb->format =3D fb->format; + sb->pitch[0] =3D fb->pitches[0]; + + return 0; +} + static const struct drm_plane_helper_funcs intel_plane_helper_funcs =3D { .prepare_fb =3D intel_prepare_plane_fb, .cleanup_fb =3D intel_cleanup_plane_fb, }; =20 + +static const struct drm_plane_helper_funcs intel_primary_plane_helper_func= s =3D { + .prepare_fb =3D intel_prepare_plane_fb, + .cleanup_fb =3D intel_cleanup_plane_fb, + .get_scanout_buffer =3D intel_get_scanout_buffer, + .panic_flush =3D intel_panic_flush, +}; + void intel_plane_helper_add(struct intel_plane *plane) { - drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); + if (plane->base.type =3D=3D DRM_PLANE_TYPE_PRIMARY) + drm_plane_helper_add(&plane->base, &intel_primary_plane_helper_funcs); + else + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); } =20 void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_pla= ne_state, --=20 2.47.0