From nobody Thu Dec 26 23:38:21 2024 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3315C1A303C; Fri, 29 Nov 2024 15:36:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732894592; cv=none; b=NUlwNrSdFGjJ5OSSDCPeSMqZnQYDRCB2guFMkGeds4yNQ6xXiW7ppZzF2voPSqLJpc1b7CopudbjBBxQ0+3RUpmyewCbsRwIo7pZhAb9/pMo+vJVG2RlfelWFwzDmD9aZ1UMuBrgsKFsMrBpXSXEhA3tQ+QrOn8uUHg3BKBEq84= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732894592; c=relaxed/simple; bh=wx+0VTi2u/OFCG9JVhbaP7A8a7T5ghKhQAvoVlFunuk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lSbWCH3USDGgem0hBIWnXiiMc7SjM3s5Sbyr9yj+tmNs7cprvJRBRxr1/4RsbnlAGeduCra0E4OtGMOJibKF7eYvcMIrfDDc+nIZg5zcMsJxTY5C7hAQjrUX+GefP6PD+4LFD7Pt/jiDdHExwthljGoJLKbtRhn1IsC9ox74rvM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=MIawjqyF; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="MIawjqyF" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4ATBkQ13018141; Fri, 29 Nov 2024 10:36:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=AtUcu 51GFu76fVDjFsrCXIbOLmWVN24WzbFbRHGmNVw=; b=MIawjqyFxVlzoMzudLSJb wvUjfHR4rhhUulQRlZd32Kb7PNuC31nFhnSjqLsq07MxSifB6D+qLN/vmEcNDQm+ jMeZwqD95qibvSJAy4RyUmvbGIm+qWYazG8PI6oUsldXz/cPYHkoG/v10jd9LwlN fOTX1dGS8+A4w1maSrYR8bcA/hWiFNDpnmlPzibFBrz8VE0Jd9rmK9+J+k5vgHP4 W/Z8YoklG3v5hPiAcq5nqPXGnPcSRUss7823ulORtqk7eM5O8GtUTVs4yvQXVpj7 k2vc6GYbLt7KdTSpE4/r4jD0t+NigtkUscGsMERCHIsLpOwb4sd6z8u+fT6uWbV7 A== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 436715tj5e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 29 Nov 2024 10:36:23 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 4ATFaMue008910 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 29 Nov 2024 10:36:22 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 29 Nov 2024 10:36:22 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 29 Nov 2024 10:36:22 -0500 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.161]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 4ATFa0mB001167; Fri, 29 Nov 2024 10:36:18 -0500 From: Antoniu Miclaus To: , , , , , , , CC: Antoniu Miclaus Subject: [PATCH v7 8/8] iio: adc: ad4851: add ad485x driver Date: Fri, 29 Nov 2024 17:35:46 +0200 Message-ID: <20241129153546.63584-9-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241129153546.63584-1-antoniu.miclaus@analog.com> References: <20241129153546.63584-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: z0jd7CvOwBM0RsJs2eMSwrQtgiluOp42 X-Proofpoint-GUID: z0jd7CvOwBM0RsJs2eMSwrQtgiluOp42 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=999 suspectscore=0 mlxscore=0 bulkscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2411290127 Content-Type: text/plain; charset="utf-8" Add support for the AD485X a fully buffered, 8-channel simultaneous sampling, 16/20-bit, 1 MSPS data acquisition system (DAS) with differential, wide common-mode range inputs. Signed-off-by: Antoniu Miclaus --- changes in v7: - use new iio backend os enable/disable functions - implement separate scan_type for both signed and unsigned. - drop ext_scan_type for 16-bit chips - rework scan_index ordering. - add separate scales for diff/single-ended channels - parse iio channels via dts properties. drivers/iio/adc/Kconfig | 13 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad4851.c | 1346 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 1360 insertions(+) create mode 100644 drivers/iio/adc/ad4851.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 6c4e74420fd2..0d97cd760d90 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -61,6 +61,19 @@ config AD4695 To compile this driver as a module, choose M here: the module will be called ad4695. =20 +config AD4851 + tristate "Analog Device AD4851 DAS Driver" + depends on SPI + select REGMAP_SPI + select IIO_BACKEND + help + Say yes here to build support for Analog Devices AD4851, AD4852, + AD4853, AD4854, AD4855, AD4856, AD4857, AD4858, AD4858I high speed + data acquisition system (DAS). + + To compile this driver as a module, choose M here: the module will be + called ad4851. + config AD7091R tristate =20 diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 7b91cd98c0e0..d83df8b5925d 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_AD_SIGMA_DELTA) +=3D ad_sigma_delta.o obj-$(CONFIG_AD4000) +=3D ad4000.o obj-$(CONFIG_AD4130) +=3D ad4130.o obj-$(CONFIG_AD4695) +=3D ad4695.o +obj-$(CONFIG_AD4851) +=3D ad4851.o obj-$(CONFIG_AD7091R) +=3D ad7091r-base.o obj-$(CONFIG_AD7091R5) +=3D ad7091r5.o obj-$(CONFIG_AD7091R8) +=3D ad7091r8.o diff --git a/drivers/iio/adc/ad4851.c b/drivers/iio/adc/ad4851.c new file mode 100644 index 000000000000..e8e5c0def29e --- /dev/null +++ b/drivers/iio/adc/ad4851.c @@ -0,0 +1,1346 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices AD4851 DAS driver + * + * Copyright 2024 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define AD4851_REG_INTERFACE_CONFIG_A 0x00 +#define AD4851_REG_INTERFACE_CONFIG_B 0x01 +#define AD4851_REG_PRODUCT_ID_L 0x04 +#define AD4851_REG_PRODUCT_ID_H 0x05 +#define AD4851_REG_DEVICE_CTRL 0x25 +#define AD4851_REG_PACKET 0x26 +#define AD4851_REG_OVERSAMPLE 0x27 + +#define AD4851_REG_CH_CONFIG_BASE 0x2A +#define AD4851_REG_CHX_SOFTSPAN(ch) ((0x12 * (ch)) + AD4851_REG_CH_CONFIG_= BASE) +#define AD4851_REG_CHX_OFFSET(ch) (AD4851_REG_CHX_SOFTSPAN(ch) + 0x01) +#define AD4851_REG_CHX_OFFSET_LSB(ch) AD4851_REG_CHX_OFFSET(ch) +#define AD4851_REG_CHX_OFFSET_MID(ch) (AD4851_REG_CHX_OFFSET_LSB(ch) + 0x0= 1) +#define AD4851_REG_CHX_OFFSET_MSB(ch) (AD4851_REG_CHX_OFFSET_MID(ch) + 0x0= 1) +#define AD4851_REG_CHX_GAIN(ch) (AD4851_REG_CHX_OFFSET(ch) + 0x03) +#define AD4851_REG_CHX_GAIN_LSB(ch) AD4851_REG_CHX_GAIN(ch) +#define AD4851_REG_CHX_GAIN_MSB(ch) (AD4851_REG_CHX_GAIN(ch) + 0x01) +#define AD4851_REG_CHX_PHASE(ch) (AD4851_REG_CHX_GAIN(ch) + 0x02) +#define AD4851_REG_CHX_PHASE_LSB(ch) AD4851_REG_CHX_PHASE(ch) +#define AD4851_REG_CHX_PHASE_MSB(ch) (AD4851_REG_CHX_PHASE_LSB(ch) + 0x01) + +#define AD4851_REG_TESTPAT_0(c) (0x38 + (c) * 0x12) +#define AD4851_REG_TESTPAT_1(c) (0x39 + (c) * 0x12) +#define AD4851_REG_TESTPAT_2(c) (0x3A + (c) * 0x12) +#define AD4851_REG_TESTPAT_3(c) (0x3B + (c) * 0x12) + +#define AD4851_SW_RESET (BIT(7) | BIT(0)) +#define AD4851_SDO_ENABLE BIT(4) +#define AD4851_SINGLE_INSTRUCTION BIT(7) +#define AD4851_REFBUF_PD BIT(2) +#define AD4851_REFSEL_PD BIT(1) +#define AD4851_ECHO_CLOCK_MODE BIT(0) + +#define AD4851_PACKET_FORMAT_0 0 +#define AD4851_PACKET_FORMAT_1 1 +#define AD4851_PACKET_FORMAT_MASK GENMASK(1, 0) + +#define AD4851_OS_EN_MSK BIT(7) +#define AD4851_OS_RATIO_MSK GENMASK(3, 0) + +#define AD4851_TEST_PAT BIT(2) + +#define AD4858_PACKET_SIZE_20 0 +#define AD4858_PACKET_SIZE_24 1 +#define AD4858_PACKET_SIZE_32 2 + +#define AD4857_PACKET_SIZE_16 0 +#define AD4857_PACKET_SIZE_24 1 + +#define AD4851_TESTPAT_0_DEFAULT 0x2A +#define AD4851_TESTPAT_1_DEFAULT 0x3C +#define AD4851_TESTPAT_2_DEFAULT 0xCE +#define AD4851_TESTPAT_3_DEFAULT(c) (0x0A + (0x10 * (c))) + +#define AD4851_SOFTSPAN_0V_2V5 0 +#define AD4851_SOFTSPAN_N2V5_2V5 1 +#define AD4851_SOFTSPAN_0V_5V 2 +#define AD4851_SOFTSPAN_N5V_5V 3 +#define AD4851_SOFTSPAN_0V_6V25 4 +#define AD4851_SOFTSPAN_N6V25_6V25 5 +#define AD4851_SOFTSPAN_0V_10V 6 +#define AD4851_SOFTSPAN_N10V_10V 7 +#define AD4851_SOFTSPAN_0V_12V5 8 +#define AD4851_SOFTSPAN_N12V5_12V5 9 +#define AD4851_SOFTSPAN_0V_20V 10 +#define AD4851_SOFTSPAN_N20V_20V 11 +#define AD4851_SOFTSPAN_0V_25V 12 +#define AD4851_SOFTSPAN_N25V_25V 13 +#define AD4851_SOFTSPAN_0V_40V 14 +#define AD4851_SOFTSPAN_N40V_40V 15 + +#define AD4851_MAX_LANES 8 +#define AD4851_MAX_IODELAY 32 + +#define AD4851_T_CNVH_NS 40 + +#define AD4841_MAX_SCALE_AVAIL 8 + +#define AD4851_MAX_CH_NR 8 +#define AD4851_CH_START 0 + +struct ad4851_scale { + unsigned int scale_val; + u8 reg_val; +}; + +static const struct ad4851_scale ad4851_scale_table_se[] =3D { + { 2500, 0x0 }, + { 5000, 0x2 }, + { 6250, 0x4 }, + { 10000, 0x6 }, + { 12500, 0x8 }, + { 20000, 0xA }, + { 25000, 0xC }, + { 40000, 0xE }, +}; + +static const struct ad4851_scale ad4851_scale_table_diff[] =3D { + { 5000, 0x1 }, + { 10000, 0x3 }, + { 12500, 0x5 }, + { 20000, 0x7 }, + { 25000, 0x9 }, + { 40000, 0xB }, + { 50000, 0xD }, + { 80000, 0xF }, +}; + +static const unsigned int ad4851_scale_avail_se[] =3D { + 2500, + 5000, + 6250, + 10000, + 12500, + 20000, + 25000, + 40000, +}; + +static const unsigned int ad4851_scale_avail_diff[] =3D { + 5000, + 10000, + 12500, + 20000, + 25000, + 40000, + 50000, + 80000, +}; + +struct ad4851_chip_info { + const char *name; + unsigned int product_id; + int num_scales; + const struct iio_chan_spec *channels; + unsigned int num_channels; + unsigned long max_sample_rate_hz; + unsigned int resolution; + int (*parse_channels)(struct iio_dev *indio_dev); +}; + +enum { + AD4851_SCAN_TYPE_NORMAL, + AD4851_SCAN_TYPE_RESOLUTION_BOOST, +}; + +struct ad4851_state { + struct spi_device *spi; + struct pwm_device *cnv; + struct iio_backend *back; + /* + * Synchronize access to members the of driver state, and ensure + * atomicity of consecutive regmap operations. + */ + struct mutex lock; + struct regmap *regmap; + struct regulator *vrefbuf; + struct regulator *vrefio; + const struct ad4851_chip_info *info; + struct gpio_desc *pd_gpio; + bool resolution_boost_enabled; + unsigned long sampling_freq; + unsigned int scales_se[AD4841_MAX_SCALE_AVAIL][2]; + unsigned int scales_diff[AD4841_MAX_SCALE_AVAIL][2]; +}; + +static int ad4851_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int writeval, + unsigned int *readval) +{ + struct ad4851_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + if (readval) + return regmap_read(st->regmap, reg, readval); + + return regmap_write(st->regmap, reg, writeval); +} + +static int ad4851_set_sampling_freq(struct ad4851_state *st, unsigned int = freq) +{ + struct pwm_state cnv_state =3D { + .duty_cycle =3D AD4851_T_CNVH_NS, + .enabled =3D true, + }; + int ret; + + freq =3D clamp(freq, 1, st->info->max_sample_rate_hz); + + cnv_state.period =3D DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq); + + ret =3D pwm_apply_might_sleep(st->cnv, &cnv_state); + if (ret) + return ret; + + st->sampling_freq =3D freq; + + return 0; +} + +static const int ad4851_oversampling_ratios[] =3D { + 1, 2, 4, 8, 16, 32, 64, 128, + 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, + 65536, +}; + +static int ad4851_osr_to_regval(int ratio) +{ + int i; + + for (i =3D 1; i < ARRAY_SIZE(ad4851_oversampling_ratios); i++) + if (ratio =3D=3D ad4851_oversampling_ratios[i]) + return i - 1; + + return -EINVAL; +} + +static int ad4851_set_oversampling_ratio(struct ad4851_state *st, + const struct iio_chan_spec *chan, + unsigned int osr) +{ + unsigned int val; + int ret; + + guard(mutex)(&st->lock); + + if (osr =3D=3D 1) { + ret =3D regmap_clear_bits(st->regmap, AD4851_REG_OVERSAMPLE, + AD4851_OS_EN_MSK); + if (ret) + return ret; + + ret =3D iio_backend_oversampling_disable(st->back); + if (ret) + return ret; + } else { + val =3D ad4851_osr_to_regval(osr); + if (val < 0) + return -EINVAL; + + ret =3D regmap_set_bits(st->regmap, AD4851_REG_OVERSAMPLE, + AD4851_OS_EN_MSK); + if (ret) + return ret; + + ret =3D regmap_update_bits(st->regmap, AD4851_REG_OVERSAMPLE, + AD4851_OS_RATIO_MSK, val); + if (ret) + return ret; + + ret =3D iio_backend_oversampling_enable(st->back); + if (ret) + return ret; + } + + switch (chan->scan_type.realbits) { + case 20: + switch (osr) { + case 0: + return -EINVAL; + case 1: + val =3D 20; + break; + default: + val =3D 24; + break; + } + break; + case 16: + val =3D 16; + break; + default: + return -EINVAL; + } + + ret =3D iio_backend_data_size_set(st->back, val); + if (ret) + return ret; + + if (osr =3D=3D 1 || chan->scan_type.realbits =3D=3D 16) { + ret =3D regmap_clear_bits(st->regmap, AD4851_REG_PACKET, + AD4851_PACKET_FORMAT_MASK); + if (ret) + return ret; + + st->resolution_boost_enabled =3D false; + } else { + ret =3D regmap_update_bits(st->regmap, AD4851_REG_PACKET, + AD4851_PACKET_FORMAT_MASK, + FIELD_PREP(AD4851_PACKET_FORMAT_MASK, 1)); + if (ret) + return ret; + + st->resolution_boost_enabled =3D true; + } + + return 0; +} + +static int ad4851_get_oversampling_ratio(struct ad4851_state *st, unsigned= int *val) +{ + unsigned int osr; + int ret; + + guard(mutex)(&st->lock); + + ret =3D regmap_read(st->regmap, AD4851_REG_OVERSAMPLE, &osr); + if (ret) + return ret; + + if (!FIELD_GET(AD4851_OS_EN_MSK, osr)) + *val =3D 1; + else + *val =3D ad4851_oversampling_ratios[FIELD_GET(AD4851_OS_RATIO_MSK, osr)]; + + return IIO_VAL_INT; +} + +static void ad4851_reg_disable(void *data) +{ + regulator_disable(data); +} + +static void ad4851_pwm_disable(void *data) +{ + pwm_disable(data); +} + +static int ad4851_setup(struct ad4851_state *st) +{ + unsigned int product_id; + int ret; + + if (!IS_ERR(st->vrefbuf)) { + ret =3D regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL, + AD4851_REFBUF_PD); + if (ret) + return ret; + + ret =3D regulator_enable(st->vrefbuf); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(&st->spi->dev, ad4851_reg_disable, + st->vrefbuf); + if (ret) + return ret; + } + + if (!IS_ERR(st->vrefio)) { + ret =3D regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL, + AD4851_REFSEL_PD); + if (ret) + return ret; + + ret =3D regulator_enable(st->vrefio); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(&st->spi->dev, ad4851_reg_disable, + st->vrefio); + if (ret) + return ret; + } + + if (st->pd_gpio) { + /* To initiate a global reset, bring the PD pin high twice */ + gpiod_set_value(st->pd_gpio, 1); + fsleep(1); + gpiod_set_value(st->pd_gpio, 0); + fsleep(1); + gpiod_set_value(st->pd_gpio, 1); + fsleep(1); + gpiod_set_value(st->pd_gpio, 0); + fsleep(1000); + } else { + ret =3D regmap_set_bits(st->regmap, AD4851_REG_INTERFACE_CONFIG_A, + AD4851_SW_RESET); + if (ret) + return ret; + } + + ret =3D regmap_write(st->regmap, AD4851_REG_INTERFACE_CONFIG_B, + AD4851_SINGLE_INSTRUCTION); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4851_REG_INTERFACE_CONFIG_A, + AD4851_SDO_ENABLE); + if (ret) + return ret; + + ret =3D regmap_read(st->regmap, AD4851_REG_PRODUCT_ID_L, &product_id); + if (ret) + return ret; + + if (product_id !=3D st->info->product_id) + dev_info(&st->spi->dev, "Unknown product ID: 0x%02X\n", + product_id); + + ret =3D regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL, + AD4851_ECHO_CLOCK_MODE); + if (ret) + return ret; + + return regmap_write(st->regmap, AD4851_REG_PACKET, 0); +} + +static int ad4851_find_opt(bool *field, u32 size, u32 *ret_start) +{ + unsigned int i, cnt =3D 0, max_cnt =3D 0, max_start =3D 0; + int start; + + for (i =3D 0, start =3D -1; i < size; i++) { + if (field[i] =3D=3D 0) { + if (start =3D=3D -1) + start =3D i; + cnt++; + } else { + if (cnt > max_cnt) { + max_cnt =3D cnt; + max_start =3D start; + } + start =3D -1; + cnt =3D 0; + } + } + /* + * Find the longest consecutive sequence of false values from field + * and return starting index. + */ + if (cnt > max_cnt) { + max_cnt =3D cnt; + max_start =3D start; + } + + if (!max_cnt) + return -ENOENT; + + *ret_start =3D max_start; + + return max_cnt; +} + +static int ad4851_calibrate(struct ad4851_state *st) +{ + unsigned int opt_delay, num_lanes, delay, i, s, c; + enum iio_backend_interface_type interface_type; + DECLARE_BITMAP(pn_status, AD4851_MAX_LANES * AD4851_MAX_IODELAY); + bool status; + int ret; + + ret =3D iio_backend_interface_type_get(st->back, &interface_type); + if (ret) + return ret; + + switch (interface_type) { + case IIO_BACKEND_INTERFACE_SERIAL_CMOS: + num_lanes =3D st->info->num_channels / 2; + break; + case IIO_BACKEND_INTERFACE_SERIAL_LVDS: + num_lanes =3D 1; + break; + default: + return -EINVAL; + } + + if (st->info->resolution =3D=3D 16) { + ret =3D iio_backend_data_size_set(st->back, 24); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4851_REG_PACKET, + AD4851_TEST_PAT | AD4857_PACKET_SIZE_24); + if (ret) + return ret; + } else { + ret =3D iio_backend_data_size_set(st->back, 32); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4851_REG_PACKET, + AD4851_TEST_PAT | AD4858_PACKET_SIZE_32); + if (ret) + return ret; + } + + for (i =3D 0; i < st->info->num_channels / 2; i++) { + ret =3D regmap_write(st->regmap, AD4851_REG_TESTPAT_0(i), + AD4851_TESTPAT_0_DEFAULT); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4851_REG_TESTPAT_1(i), + AD4851_TESTPAT_1_DEFAULT); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4851_REG_TESTPAT_2(i), + AD4851_TESTPAT_2_DEFAULT); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4851_REG_TESTPAT_3(i), + AD4851_TESTPAT_3_DEFAULT(i)); + if (ret) + return ret; + + ret =3D iio_backend_chan_enable(st->back, i); + if (ret) + return ret; + } + + for (i =3D 0; i < num_lanes; i++) { + for (delay =3D 0; delay < AD4851_MAX_IODELAY; delay++) { + ret =3D iio_backend_iodelay_set(st->back, i, delay); + if (ret) + return ret; + + ret =3D iio_backend_chan_status(st->back, i, &status); + if (ret) + return ret; + + if (status) + set_bit(i * AD4851_MAX_IODELAY + delay, pn_status); + else + clear_bit(i * AD4851_MAX_IODELAY + delay, pn_status); + } + } + + for (i =3D 0; i < num_lanes; i++) { + status =3D test_bit(i * AD4851_MAX_IODELAY, pn_status); + c =3D ad4851_find_opt(&status, AD4851_MAX_IODELAY, &s); + if (c < 0) + return c; + + opt_delay =3D s + c / 2; + ret =3D iio_backend_iodelay_set(st->back, i, opt_delay); + if (ret) + return ret; + } + + for (i =3D 0; i < st->info->num_channels / 2; i++) { + ret =3D iio_backend_chan_disable(st->back, i); + if (ret) + return ret; + } + + ret =3D iio_backend_data_size_set(st->back, 20); + if (ret) + return ret; + + return regmap_write(st->regmap, AD4851_REG_PACKET, 0); +} + +static int ad4851_get_calibscale(struct ad4851_state *st, int ch, int *val= , int *val2) +{ + unsigned int reg_val; + int gain; + int ret; + + guard(mutex)(&st->lock); + + ret =3D regmap_read(st->regmap, AD4851_REG_CHX_GAIN_MSB(ch), ®_val); + if (ret) + return ret; + + gain =3D reg_val << 8; + + ret =3D regmap_read(st->regmap, AD4851_REG_CHX_GAIN_LSB(ch), ®_val); + if (ret) + return ret; + + gain |=3D reg_val; + + *val =3D gain; + *val2 =3D 32768; + + return IIO_VAL_FRACTIONAL; +} + +static int ad4851_set_calibscale(struct ad4851_state *st, int ch, int val, + int val2) +{ + u64 gain; + u8 buf[2]; + int ret; + + if (val < 0 || val2 < 0) + return -EINVAL; + + gain =3D val * MICRO + val2; + gain =3D DIV_U64_ROUND_CLOSEST(gain * 32768, MICRO); + + put_unaligned_be16(gain, buf); + + guard(mutex)(&st->lock); + + ret =3D regmap_write(st->regmap, AD4851_REG_CHX_GAIN_MSB(ch), buf[0]); + if (ret) + return ret; + + return regmap_write(st->regmap, AD4851_REG_CHX_GAIN_LSB(ch), buf[1]); +} + +static int ad4851_get_calibbias(struct ad4851_state *st, int ch, int *val) +{ + unsigned int lsb, mid, msb; + int ret; + + guard(mutex)(&st->lock); + + ret =3D regmap_read(st->regmap, AD4851_REG_CHX_OFFSET_MSB(ch), + &msb); + if (ret) + return ret; + + ret =3D regmap_read(st->regmap, AD4851_REG_CHX_OFFSET_MID(ch), + &mid); + if (ret) + return ret; + + ret =3D regmap_read(st->regmap, AD4851_REG_CHX_OFFSET_LSB(ch), + &lsb); + if (ret) + return ret; + + if (st->info->resolution =3D=3D 16) { + *val =3D msb << 8; + *val |=3D mid; + *val =3D sign_extend32(*val, 15); + } else { + *val =3D msb << 12; + *val |=3D mid << 4; + *val |=3D lsb >> 4; + *val =3D sign_extend32(*val, 19); + } + + return IIO_VAL_INT; +} + +static int ad4851_set_calibbias(struct ad4851_state *st, int ch, int val) +{ + u8 buf[3] =3D { 0 }; + int ret; + + if (val < 0) + return -EINVAL; + + if (st->info->resolution =3D=3D 16) + put_unaligned_be16(val, buf); + else + put_unaligned_be24(val << 4, buf); + + guard(mutex)(&st->lock); + + ret =3D regmap_write(st->regmap, AD4851_REG_CHX_OFFSET_LSB(ch), buf[2]); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4851_REG_CHX_OFFSET_MID(ch), buf[1]); + if (ret) + return ret; + + return regmap_write(st->regmap, AD4851_REG_CHX_OFFSET_MSB(ch), buf[0]); +} + +static void __ad4851_get_scale(struct ad4851_state *st, int scale_tbl, + unsigned int *val, unsigned int *val2) +{ + const struct ad4851_chip_info *info =3D st->info; + const struct iio_chan_spec *chan =3D &info->channels[0]; + unsigned int tmp; + + tmp =3D ((unsigned long long)scale_tbl * MICRO) >> chan->scan_type.realbi= ts; + *val =3D tmp / MICRO; + *val2 =3D tmp % MICRO; +} + +static int ad4851_set_scale(struct ad4851_state *st, + const struct iio_chan_spec *chan, int val, int val2) +{ + unsigned int scale_val[2]; + unsigned int i; + const struct ad4851_scale *scale_table; + size_t table_size; + + if (chan->differential) { + scale_table =3D ad4851_scale_table_diff; + table_size =3D ARRAY_SIZE(ad4851_scale_table_diff); + } else { + scale_table =3D ad4851_scale_table_se; + table_size =3D ARRAY_SIZE(ad4851_scale_table_se); + } + + for (i =3D 0; i < table_size; i++) { + __ad4851_get_scale(st, scale_table[i].scale_val, + &scale_val[0], &scale_val[1]); + if (scale_val[0] !=3D val || scale_val[1] !=3D val2) + continue; + + return regmap_write(st->regmap, + AD4851_REG_CHX_SOFTSPAN(chan->channel), + scale_table[i].reg_val); + } + + return -EINVAL; +} + +static int ad4851_get_scale(struct ad4851_state *st, + const struct iio_chan_spec *chan, int *val, + int *val2) +{ + int i, softspan_val; + int ret; + const struct ad4851_scale *scale_table; + size_t table_size; + + if (chan->differential) { + scale_table =3D ad4851_scale_table_diff; + table_size =3D ARRAY_SIZE(ad4851_scale_table_diff); + } else { + scale_table =3D ad4851_scale_table_se; + table_size =3D ARRAY_SIZE(ad4851_scale_table_se); + } + + ret =3D regmap_read(st->regmap, AD4851_REG_CHX_SOFTSPAN(chan->channel), + &softspan_val); + if (ret) + return ret; + + for (i =3D 0; i < table_size; i++) { + if (softspan_val =3D=3D scale_table[i].reg_val) + break; + } + + if (i =3D=3D table_size) + return -EIO; + + __ad4851_get_scale(st, scale_table[i].scale_val, val, val2); + + return IIO_VAL_INT_PLUS_MICRO; +} + +static int ad4851_scale_fill(struct ad4851_state *st) +{ + unsigned int i, val1, val2; + + for (i =3D 0; i < ARRAY_SIZE(ad4851_scale_avail_se); i++) { + __ad4851_get_scale(st, ad4851_scale_avail_se[i], &val1, &val2); + st->scales_se[i][0] =3D val1; + st->scales_se[i][1] =3D val2; + } + + for (i =3D 0; i < ARRAY_SIZE(ad4851_scale_avail_diff); i++) { + __ad4851_get_scale(st, ad4851_scale_avail_diff[i], &val1, &val2); + st->scales_diff[i][0] =3D val1; + st->scales_diff[i][1] =3D val2; + } + + return 0; +} + +static int ad4851_read_raw(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + int *val, int *val2, long info) +{ + struct ad4851_state *st =3D iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: + *val =3D st->sampling_freq; + return IIO_VAL_INT; + case IIO_CHAN_INFO_CALIBSCALE: + return ad4851_get_calibscale(st, chan->channel, val, val2); + case IIO_CHAN_INFO_SCALE: + return ad4851_get_scale(st, chan, val, val2); + case IIO_CHAN_INFO_CALIBBIAS: + return ad4851_get_calibbias(st, chan->channel, val); + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + return ad4851_get_oversampling_ratio(st, val); + default: + return -EINVAL; + } +} + +static int ad4851_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) +{ + struct ad4851_state *st =3D iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: + return ad4851_set_sampling_freq(st, val); + case IIO_CHAN_INFO_SCALE: + return ad4851_set_scale(st, chan, val, val2); + case IIO_CHAN_INFO_CALIBSCALE: + return ad4851_set_calibscale(st, chan->channel, val, val2); + case IIO_CHAN_INFO_CALIBBIAS: + return ad4851_set_calibbias(st, chan->channel, val); + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + return ad4851_set_oversampling_ratio(st, chan, val); + default: + return -EINVAL; + } +} + +static int ad4851_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct ad4851_state *st =3D iio_priv(indio_dev); + unsigned int c; + int ret; + + for (c =3D 0; c < st->info->num_channels / 2; c++) { + if (test_bit(c, scan_mask)) + ret =3D iio_backend_chan_enable(st->back, c); + else + ret =3D iio_backend_chan_disable(st->back, c); + if (ret) + return ret; + } + + return 0; +} + +static int ad4851_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + struct ad4851_state *st =3D iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + if (chan->differential) { + *vals =3D (const int *)st->scales_diff; + *type =3D IIO_VAL_INT_PLUS_MICRO; + /* Values are stored in a 2D matrix */ + *length =3D ARRAY_SIZE(ad4851_scale_avail_diff) * 2; + } else { + *vals =3D (const int *)st->scales_se; + *type =3D IIO_VAL_INT_PLUS_MICRO; + /* Values are stored in a 2D matrix */ + *length =3D ARRAY_SIZE(ad4851_scale_avail_se) * 2; + } + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *vals =3D ad4851_oversampling_ratios; + *length =3D ARRAY_SIZE(ad4851_oversampling_ratios); + *type =3D IIO_VAL_INT; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + +static const struct iio_scan_type ad4851_scan_type_16 =3D { + .sign =3D 's', + .realbits =3D 16, + .storagebits =3D 16, +}; + +static const struct iio_scan_type ad4851_scan_type_20_0[] =3D { + [AD4851_SCAN_TYPE_NORMAL] =3D { + .sign =3D 'u', + .realbits =3D 20, + .storagebits =3D 32, + }, + [AD4851_SCAN_TYPE_RESOLUTION_BOOST] =3D { + .sign =3D 'u', + .realbits =3D 24, + .storagebits =3D 32, + }, +}; + +static const struct iio_scan_type ad4851_scan_type_20_1[] =3D { + [AD4851_SCAN_TYPE_NORMAL] =3D { + .sign =3D 's', + .realbits =3D 20, + .storagebits =3D 32, + }, + [AD4851_SCAN_TYPE_RESOLUTION_BOOST] =3D { + .sign =3D 's', + .realbits =3D 24, + .storagebits =3D 32, + }, +}; + +static int ad4851_get_current_scan_type(const struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad4851_state *st =3D iio_priv(indio_dev); + + return st->resolution_boost_enabled ? AD4851_SCAN_TYPE_RESOLUTION_BOOST + : AD4851_SCAN_TYPE_NORMAL; +} + +#define AD4851_IIO_CHANNEL(index, ch, diff) \ + .type =3D IIO_VOLTAGE, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_CALIBSCALE) | \ + BIT(IIO_CHAN_INFO_CALIBBIAS) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all_available =3D \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SCALE), \ + .indexed =3D 1, \ + .differential =3D diff, \ + .channel =3D ch, \ + .channel2 =3D ch + (diff * 8), \ + .scan_index =3D index, \ + +#define AD4858_IIO_CHANNEL(index, ch, diff, bits) \ +{ \ + AD4851_IIO_CHANNEL(index, ch, diff) \ + .ext_scan_type =3D ad4851_scan_type_##bits##_##diff, \ + .num_ext_scan_type =3D ARRAY_SIZE(ad4851_scan_type_##bits##_##diff), \ +} + +#define AD4857_IIO_CHANNEL(index, ch, diff, bits) \ +{ \ + AD4851_IIO_CHANNEL(index, ch, diff) \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D bits, \ + .storagebits =3D bits, \ + }, \ +} + +static const struct iio_chan_spec ad4858_channels[] =3D { + AD4858_IIO_CHANNEL(0, 0, 0, 20), + AD4858_IIO_CHANNEL(1, 0, 1, 20), + AD4858_IIO_CHANNEL(2, 1, 0, 20), + AD4858_IIO_CHANNEL(3, 1, 1, 20), + AD4858_IIO_CHANNEL(4, 2, 0, 20), + AD4858_IIO_CHANNEL(5, 2, 1, 20), + AD4858_IIO_CHANNEL(6, 3, 0, 20), + AD4858_IIO_CHANNEL(7, 3, 1, 20), + AD4858_IIO_CHANNEL(8, 4, 0, 20), + AD4858_IIO_CHANNEL(9, 4, 1, 20), + AD4858_IIO_CHANNEL(10, 5, 0, 20), + AD4858_IIO_CHANNEL(11, 5, 1, 20), + AD4858_IIO_CHANNEL(12, 6, 0, 20), + AD4858_IIO_CHANNEL(13, 6, 1, 20), + AD4858_IIO_CHANNEL(14, 7, 0, 20), + AD4858_IIO_CHANNEL(15, 7, 1, 20), +}; + +static const struct iio_chan_spec ad4857_channels[] =3D { + AD4857_IIO_CHANNEL(0, 0, 0, 16), + AD4857_IIO_CHANNEL(1, 0, 1, 16), + AD4857_IIO_CHANNEL(2, 1, 0, 16), + AD4857_IIO_CHANNEL(3, 1, 1, 16), + AD4857_IIO_CHANNEL(4, 2, 0, 16), + AD4857_IIO_CHANNEL(5, 2, 1, 16), + AD4857_IIO_CHANNEL(6, 3, 0, 16), + AD4857_IIO_CHANNEL(7, 3, 1, 16), + AD4857_IIO_CHANNEL(8, 4, 0, 16), + AD4857_IIO_CHANNEL(9, 4, 1, 16), + AD4857_IIO_CHANNEL(10, 5, 0, 16), + AD4857_IIO_CHANNEL(11, 5, 1, 16), + AD4857_IIO_CHANNEL(12, 6, 0, 16), + AD4857_IIO_CHANNEL(13, 6, 1, 16), + AD4857_IIO_CHANNEL(14, 7, 0, 16), + AD4857_IIO_CHANNEL(15, 7, 1, 16), +}; + +static int ad4857_parse_channels(struct iio_dev *indio_dev) +{ + struct device *dev =3D indio_dev->dev.parent; + struct ad4851_state *st =3D iio_priv(indio_dev); + struct iio_chan_spec *ad4851_channels; + const struct iio_chan_spec ad4851_chan =3D AD4857_IIO_CHANNEL(0, 0, 0, 16= ); + const struct iio_chan_spec ad4851_chan_diff =3D AD4857_IIO_CHANNEL(0, 0, = 1, 16); + unsigned int num_channels, index =3D 0, reg; + int ret; + + num_channels =3D device_get_child_node_count(dev); + if (num_channels > AD4851_MAX_CH_NR) + return dev_err_probe(dev, -EINVAL, "Too many channels: %u\n", + num_channels); + + ad4851_channels =3D devm_kcalloc(dev, num_channels, + sizeof(*ad4851_channels), GFP_KERNEL); + if (!ad4851_channels) + return -ENOMEM; + + indio_dev->channels =3D ad4851_channels; + indio_dev->num_channels =3D num_channels; + + device_for_each_child_node_scoped(dev, child) { + ret =3D fwnode_property_read_u32(child, "reg", ®); + if (ret) + return dev_err_probe(dev, ret, + "Missing channel number\n"); + if (fwnode_property_present(child, "diff-channels")) { + *ad4851_channels =3D ad4851_chan_diff; + ad4851_channels->scan_index =3D index++; + ad4851_channels->channel =3D reg; + ad4851_channels->channel2 =3D reg + AD4851_MAX_CH_NR; + } else { + *ad4851_channels =3D ad4851_chan; + ad4851_channels->scan_index =3D index++; + ad4851_channels->channel =3D reg; + ret =3D regmap_write(st->regmap, AD4851_REG_CHX_SOFTSPAN(reg), + AD4851_SOFTSPAN_0V_40V); + if (ret) + return ret; + } + ad4851_channels++; + } + + return 0; +} + +static int ad4858_parse_channels(struct iio_dev *indio_dev) +{ + struct device *dev =3D indio_dev->dev.parent; + struct ad4851_state *st =3D iio_priv(indio_dev); + struct iio_chan_spec *ad4851_channels; + const struct iio_chan_spec ad4851_chan =3D AD4858_IIO_CHANNEL(0, 0, 0, 20= ); + const struct iio_chan_spec ad4851_chan_diff =3D AD4858_IIO_CHANNEL(0, 0, = 1, 20); + unsigned int num_channels, index =3D 0, reg; + int ret; + + num_channels =3D device_get_child_node_count(dev); + if (num_channels > AD4851_MAX_CH_NR) + return dev_err_probe(dev, -EINVAL, "Too many channels: %u\n", + num_channels); + + ad4851_channels =3D devm_kcalloc(dev, num_channels, + sizeof(*ad4851_channels), GFP_KERNEL); + if (!ad4851_channels) + return -ENOMEM; + + indio_dev->channels =3D ad4851_channels; + indio_dev->num_channels =3D num_channels; + + device_for_each_child_node_scoped(dev, child) { + ret =3D fwnode_property_read_u32(child, "reg", ®); + if (ret) + return dev_err_probe(dev, ret, + "Missing channel number\n"); + if (fwnode_property_present(child, "diff-channels")) { + *ad4851_channels =3D ad4851_chan_diff; + ad4851_channels->scan_index =3D index++; + ad4851_channels->channel =3D reg; + ad4851_channels->channel2 =3D reg + AD4851_MAX_CH_NR; + ad4851_channels->ext_scan_type =3D ad4851_scan_type_20_1; + ad4851_channels->num_ext_scan_type =3D ARRAY_SIZE(ad4851_scan_type_20_1= ); + + } else { + *ad4851_channels =3D ad4851_chan; + ad4851_channels->scan_index =3D index++; + ad4851_channels->channel =3D reg; + ad4851_channels->ext_scan_type =3D ad4851_scan_type_20_0; + ad4851_channels->num_ext_scan_type =3D ARRAY_SIZE(ad4851_scan_type_20_0= ); + ret =3D regmap_write(st->regmap, AD4851_REG_CHX_SOFTSPAN(reg), + AD4851_SOFTSPAN_0V_40V); + if (ret) + return ret; + } + ad4851_channels++; + } + + return 0; +} + +static const struct ad4851_chip_info ad4851_info =3D { + .name =3D "ad4851", + .product_id =3D 0x67, + .max_sample_rate_hz =3D 250 * KILO, + .resolution =3D 16, + .parse_channels =3D ad4857_parse_channels, +}; + +static const struct ad4851_chip_info ad4852_info =3D { + .name =3D "ad4852", + .product_id =3D 0x66, + .max_sample_rate_hz =3D 250 * KILO, + .resolution =3D 20, + .parse_channels =3D ad4858_parse_channels, +}; + +static const struct ad4851_chip_info ad4853_info =3D { + .name =3D "ad4853", + .product_id =3D 0x65, + .max_sample_rate_hz =3D 1 * MEGA, + .resolution =3D 16, + .parse_channels =3D ad4857_parse_channels, +}; + +static const struct ad4851_chip_info ad4854_info =3D { + .name =3D "ad4854", + .product_id =3D 0x64, + .max_sample_rate_hz =3D 1 * MEGA, + .resolution =3D 20, + .parse_channels =3D ad4858_parse_channels, +}; + +static const struct ad4851_chip_info ad4855_info =3D { + .name =3D "ad4855", + .product_id =3D 0x63, + .max_sample_rate_hz =3D 250 * KILO, + .resolution =3D 16, + .parse_channels =3D ad4857_parse_channels, +}; + +static const struct ad4851_chip_info ad4856_info =3D { + .name =3D "ad4856", + .product_id =3D 0x62, + .max_sample_rate_hz =3D 250 * KILO, + .resolution =3D 20, + .parse_channels =3D ad4858_parse_channels, +}; + +static const struct ad4851_chip_info ad4857_info =3D { + .name =3D "ad4857", + .product_id =3D 0x61, + .max_sample_rate_hz =3D 1 * MEGA, + .resolution =3D 16, + .channels =3D ad4857_channels, + .num_channels =3D ARRAY_SIZE(ad4857_channels), + .parse_channels =3D ad4857_parse_channels, +}; + +static const struct ad4851_chip_info ad4858_info =3D { + .name =3D "ad4858", + .product_id =3D 0x60, + .max_sample_rate_hz =3D 1 * MEGA, + .resolution =3D 20, + .parse_channels =3D ad4858_parse_channels, +}; + +static const struct ad4851_chip_info ad4858i_info =3D { + .name =3D "ad4858i", + .product_id =3D 0x6F, + .max_sample_rate_hz =3D 1 * MEGA, + .resolution =3D 20, + .parse_channels =3D ad4858_parse_channels, +}; + +static const struct iio_info ad4851_iio_info =3D { + .debugfs_reg_access =3D ad4851_reg_access, + .read_raw =3D ad4851_read_raw, + .write_raw =3D ad4851_write_raw, + .update_scan_mode =3D ad4851_update_scan_mode, + .get_current_scan_type =3D &ad4851_get_current_scan_type, + .read_avail =3D ad4851_read_avail, +}; + +static const struct regmap_config regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .read_flag_mask =3D BIT(7), +}; + +static const char * const ad4851_power_supplies[] =3D { + "vcc", "vdd", "vee", "vio", +}; + +static int ad4851_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct device *dev =3D &spi->dev; + struct ad4851_state *st; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + st->spi =3D spi; + + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + ret =3D devm_regulator_bulk_get_enable(dev, + ARRAY_SIZE(ad4851_power_supplies), + ad4851_power_supplies); + if (ret) + return dev_err_probe(dev, ret, + "failed to get and enable supplies\n"); + + ret =3D devm_regulator_get_enable_optional(dev, "vddh"); + if (ret < 0 && ret !=3D -ENODEV) + return dev_err_probe(dev, ret, "failed to enable vddh voltage\n"); + + ret =3D devm_regulator_get_enable_optional(dev, "vddl"); + if (ret < 0 && ret !=3D -ENODEV) + return dev_err_probe(dev, ret, "failed to enable vddl voltage\n"); + + st->vrefbuf =3D devm_regulator_get_optional(dev, "vrefbuf"); + if (IS_ERR(st->vrefbuf)) { + if (PTR_ERR(st->vrefbuf) !=3D -ENODEV) + return dev_err_probe(dev, PTR_ERR(st->vrefbuf), + "Failed to get vrefbuf regulator\n"); + } + + st->vrefio =3D devm_regulator_get_optional(dev, "vrefio"); + if (IS_ERR(st->vrefio)) { + if (PTR_ERR(st->vrefio) !=3D -ENODEV) + return dev_err_probe(dev, PTR_ERR(st->vrefio), + "Failed to get vrefio regulator\n"); + } + + st->pd_gpio =3D devm_gpiod_get_optional(dev, "pd", GPIOD_OUT_LOW); + if (IS_ERR(st->pd_gpio)) + return dev_err_probe(dev, PTR_ERR(st->pd_gpio), + "Error on requesting pd GPIO\n"); + + st->cnv =3D devm_pwm_get(dev, NULL); + if (IS_ERR(st->cnv)) + return dev_err_probe(dev, PTR_ERR(st->cnv), + "Error on requesting pwm\n"); + + ret =3D devm_add_action_or_reset(&st->spi->dev, ad4851_pwm_disable, + st->cnv); + if (ret) + return ret; + + st->info =3D spi_get_device_match_data(spi); + if (!st->info) + return -ENODEV; + + st->regmap =3D devm_regmap_init_spi(spi, ®map_config); + if (IS_ERR(st->regmap)) + return PTR_ERR(st->regmap); + + ret =3D ad4851_scale_fill(st); + if (ret) + return ret; + + ret =3D ad4851_set_sampling_freq(st, HZ_PER_MHZ); + if (ret) + return ret; + + ret =3D ad4851_setup(st); + if (ret) + return ret; + + indio_dev->name =3D st->info->name; + indio_dev->info =3D &ad4851_iio_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + + ret =3D st->info->parse_channels(indio_dev); + if (ret) + return ret; + + st->back =3D devm_iio_backend_get(dev, NULL); + if (IS_ERR(st->back)) + return PTR_ERR(st->back); + + ret =3D devm_iio_backend_request_buffer(dev, st->back, indio_dev); + if (ret) + return ret; + + ret =3D devm_iio_backend_enable(dev, st->back); + if (ret) + return ret; + + ret =3D ad4851_calibrate(st); + if (ret) + return ret; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id ad4851_of_match[] =3D { + { .compatible =3D "adi,ad4851", .data =3D &ad4851_info, }, + { .compatible =3D "adi,ad4852", .data =3D &ad4852_info, }, + { .compatible =3D "adi,ad4853", .data =3D &ad4853_info, }, + { .compatible =3D "adi,ad4854", .data =3D &ad4854_info, }, + { .compatible =3D "adi,ad4855", .data =3D &ad4855_info, }, + { .compatible =3D "adi,ad4856", .data =3D &ad4856_info, }, + { .compatible =3D "adi,ad4857", .data =3D &ad4857_info, }, + { .compatible =3D "adi,ad4858", .data =3D &ad4858_info, }, + { .compatible =3D "adi,ad4858i", .data =3D &ad4858i_info, }, + { } +}; + +static const struct spi_device_id ad4851_spi_id[] =3D { + { "ad4851", (kernel_ulong_t)&ad4851_info }, + { "ad4852", (kernel_ulong_t)&ad4852_info }, + { "ad4853", (kernel_ulong_t)&ad4853_info }, + { "ad4854", (kernel_ulong_t)&ad4854_info }, + { "ad4855", (kernel_ulong_t)&ad4855_info }, + { "ad4856", (kernel_ulong_t)&ad4856_info }, + { "ad4857", (kernel_ulong_t)&ad4857_info }, + { "ad4858", (kernel_ulong_t)&ad4858_info }, + { "ad4858i", (kernel_ulong_t)&ad4858i_info }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad4851_spi_id); + +static struct spi_driver ad4851_driver =3D { + .probe =3D ad4851_probe, + .driver =3D { + .name =3D "ad4851", + .of_match_table =3D ad4851_of_match, + }, + .id_table =3D ad4851_spi_id, +}; +module_spi_driver(ad4851_driver); + +MODULE_AUTHOR("Sergiu Cuciurean "); +MODULE_AUTHOR("Dragos Bogdan "); +MODULE_AUTHOR("Antoniu Miclaus "); +MODULE_DESCRIPTION("Analog Devices AD4851 DAS driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(IIO_BACKEND); --=20 2.47.1