From nobody Sat Feb 7 08:06:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 885DD1C1746 for ; Thu, 28 Nov 2024 22:30:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833032; cv=none; b=CfaewnPdz2vxUYnUgJsuv/bf7qTK+HQ8Oelw1hu2AJbW1SX6h50q7b04lv6gozmqHxKA2N12QqNuvGfFb09rGzMAZbxc1SezW5YOH+1mus2tO3Sx/CUgeY/LEgs+D1NAmvP4OgdTJGdVXp9rfNxTgBFo+6LVm8m6eYz2U+MT14E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833032; c=relaxed/simple; bh=ev+7f3XqezzZNKejjurqPHs4oJqNYrv9TjsB57237Co=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HrCnFJwFrqk3ARMHTE9iO0IZyFCOA2BE0gEY6VccCE1OqPfJ54njVFHnZaJjT/yn4F8Znb0frW7Dd6fnx8RESoCF657vcBrY6ptP3LP0AfcgIG8UoFDsumAqWGHBfhUp3syr4GW1EVTfXTbnxHnVuCtR/HYKLkhI7rZatS4a6KM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Vz5zQScp; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=dUv8NfVa; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Vz5zQScp"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="dUv8NfVa" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1732833028; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BQg3CW3cGobDuKEgm5hZjcozrchV1/YXtgAXrFR82H4=; b=Vz5zQScpk74mUyHiKg8mCQPAMb6IsXJ6jX9DRKCV+ftF9e6hkl55/qJa/vWN8AHRmfHatX mcZC/NXio3OBeoYzwNuBClOxSqq6wZhTOm0q55EDky+EZloePAgdS3qTkPVlWB/IadbBce V2LidWUaMtt7Fp743ty5xnKwLWhI6Y1eL0rU2fVM3vFekQOzP5liEffhBpqfSRaEUtKcb+ eX7x6qH2g9D8V8D7VxZaOkpQTrBDitzV0hz4SNC6gHxaahB0M8RxsV3YXuyXz5g/BGHcxD yhAWYjLLYYwNUX5p2TD5rmjgHH0oUHEPU1tvBZ2Qnfzln/6UXWowTq5mCnF4/w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1732833028; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BQg3CW3cGobDuKEgm5hZjcozrchV1/YXtgAXrFR82H4=; b=dUv8NfVamVikWRVN63mHxsE+1AsOfh3+e0RgKjqZszKWmxE3cDIH+EpX8vh9HZUReI90TO PPUJ7apWW/0H4RDA== To: Borislav Petkov , Dave Hansen , "H. Peter Anvin" Cc: Thomas Gleixner , John Ogness , linux-kernel@vger.kernel.org, x86@kernel.org, x86-cpuid@lists.linux.dev, "Ahmed S. Darwish" Subject: [PATCH v1 01/13] LICENSES: Add Creative Commons Zero v1.0 Universal Date: Thu, 28 Nov 2024 23:29:36 +0100 Message-ID: <20241128222948.579920-2-darwi@linutronix.de> In-Reply-To: <20241128222948.579920-1-darwi@linutronix.de> References: <20241128222948.579920-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A CSV file generated by the x86-cpuid-db project was recently merged to the kernel's kcpuid tool. The SPDX license of that file is CC0-1.0, "Creative Commons Zero v1.0 Universal". Fix spdxcheck failures by adding that license under LICENSES/deprecated. The license text is copied verbatim from: git https://github.com/spdx/license-list-data/ archive: 2dc9a03a1b8df042c683924bbd6b703ade448a0d [v3.22] file: text/CC0-1.0.txt md5sum: 65d3616852dbf7b1a6d4b53b00626032 The same text is available, in beautified form, at: https://spdx.org/licenses/CC0-1.0.html#licenseText Fixes: cbbd847d107f ("tools/x86/kcpuid: Introduce a complete cpuid bitfield= s CSV file") Signed-off-by: Ahmed S. Darwish Link: https://fsfe.org/freesoftware/legal/faq.html#public-domain Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.0/LICENSE.rst --- LICENSES/deprecated/CC0-1.0 | 129 ++++++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 LICENSES/deprecated/CC0-1.0 diff --git a/LICENSES/deprecated/CC0-1.0 b/LICENSES/deprecated/CC0-1.0 new file mode 100644 index 000000000000..d337c154b0b7 --- /dev/null +++ b/LICENSES/deprecated/CC0-1.0 @@ -0,0 +1,129 @@ +Valid-License-Identifier: CC0-1.0 +SPDX-URL: https://spdx.org/licenses/CC0-1.0.html +Usage-Guide: + This license is used for imported code or data files from other + projects; e.g. auto-generated code and data listings from the + x86-cpuid-db project. Such files have the SPDX license tag: + SPDX-License-Identifier: CC0-1.0 +License-Text: +Creative Commons Legal Code + +CC0 1.0 Universal + + CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE + LEGAL SERVICES. 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Affirmer understands and acknowledges that Creative Commons is not a + party to this document and has no duty or obligation with respect to + this CC0 or use of the Work. --=20 2.46.2 From nobody Sat Feb 7 08:06:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AEBE1C5798 for ; Thu, 28 Nov 2024 22:30:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833034; cv=none; b=XdohA2wv0H0bCdI4y5ZPty64sDpd9EslVCIkBQid/9TAR+lJxnf2md1HOD5eIdAVQj00Jpa4a4lg8XvM68R9qAgp7fLhBHuDe70h7FjiV0yiqCPU+Tt1o8mM0CqJc+cqLs7bsuVfB+wvsZNykck5cE1GHsvXwZlj4/sqnCSYvtM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833034; c=relaxed/simple; bh=Avvur6Ex2NLJQvM8ykCnYKgqxHEL1a5onJOEaGF4BHo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NhxJzpdbuQgCN78BGG30+benlnG6iKsYyhEO7twraYKDZIWEXIBamJCU3E422iliKpKQjshqyQz8TIKmozegGI2MLjdpZyyXghSEQkJYoiw8DtMBiKBGGTXVV234W0ZsDGiCyMIR9/ELQuHPwogqfr1xnkh4w3/wgMU6b+fhCbc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2lMIaMKF; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=CtbKSJG9; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2lMIaMKF"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="CtbKSJG9" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1732833031; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eBXjUsVkbzYkFgtSc46k/i7jvJ4SnHni3nR7hilZ96s=; b=2lMIaMKFWBDRlXH4rlJ3DjjEP7GMf7yaRLVSVvFS5YbzYnakZbyvhDHsesoP0S4rBV45IW sPCXaFtevGkYuZFCe9XQ7IXwrx/eT1HZSd1RX9NasW0ICJnFvqjdSsPH05z3R+pt8O9sJK MEy1bPCyf/JDlYv1CQL6DYgg7YVuH44QTtgP3zsl5FKf5mE/VNFYdeK5YvpI9/MAENuSea 1QI2dyBOHId7Ywrt5uDovqcYzmh4Bl1ExF+HYiuDqOZAgevd0VjzUItT+jOfvl6YJZFPJB 587C/Gs0iniynRQu67KVEQEUlGnvU7A4G2U/l0P8cbsy3ZaJE1LhdIVADP1myQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1732833031; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eBXjUsVkbzYkFgtSc46k/i7jvJ4SnHni3nR7hilZ96s=; b=CtbKSJG9GgW1+DKPgxg7tXcWqufQSmefzdE/ksD04s6TyNxfbn48nhrV9/pAFvp6kn37W6 kQqBtxTYAMRumsBA== To: Borislav Petkov , Dave Hansen , "H. Peter Anvin" Cc: Thomas Gleixner , John Ogness , linux-kernel@vger.kernel.org, x86@kernel.org, x86-cpuid@lists.linux.dev, "Ahmed S. Darwish" Subject: [PATCH v1 02/13] tools/x86/kcpuid: Reorder header includes Date: Thu, 28 Nov 2024 23:29:37 +0100 Message-ID: <20241128222948.579920-3-darwi@linutronix.de> In-Reply-To: <20241128222948.579920-1-darwi@linutronix.de> References: <20241128222948.579920-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for including more header files, reorder current kcpuid includes alphabetically. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 1b25c0a95d3f..62a77509a5b5 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 #define _GNU_SOURCE =20 -#include +#include #include +#include #include #include -#include =20 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) #define min(a, b) (((a) < (b)) ? (a) : (b)) --=20 2.46.2 From nobody Sat Feb 7 08:06:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3E4C1C6F43 for ; Thu, 28 Nov 2024 22:30:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833038; cv=none; b=PoYh2pYqv7G9vOoYHupw+TlKGHeU/mtxgdlK8FUsxnqTJhZezySsPMfRF6wD1CZdN+ilhfkR9JrMHvqir/26yVME83dNKf18UAcMocarliSR+9+gDhZH+MjqgqxD0GdkuAx8l01GYJmJFhvEezgjYpwFiHW/Ac7g0Mx9/8JtZ4M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833038; c=relaxed/simple; bh=et53JOXTJFJ5g5vIa2M9xdCwGZiKx9tOeM/e2fPpGB0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AoghhqZkBEvHB45ND/GLrZH6VrppGkPKOYcYScCR58fh7ZUnO5dKjmQkfk9CUAV7Ku//wS2EauA/NG9nJYNM4SgIDXS0tzQYTiFAA0n1b08f3OFcplUFXHWSabHlz/YpKzLVg3CsQ6lR/HtAOvVpKP8/UdIwkH1EgCxUPlBcvLQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=VapD0n1s; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=WwiCF1Md; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="VapD0n1s"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="WwiCF1Md" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1732833035; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=STB9Xp8RPHykOZtZUboSY9JLbUrK76OO1irMSu8LVzM=; b=VapD0n1sCaLqPkSNa3y3+ovhZliC9ifDShqRsRMEBNMOpiR/T+yK21SnGdqJET6M5jp+jW cOsK47UaBbOPslOxkFD/vw+1P48LXklCbhjmBa6XhJECw4/eMJdEwbYCS/wgS87IBXDeuf eJbOaFy//bs7b65VjdsCJvJ4aJvuk3MN5UljB8jaEsaBt0JhR4cb9DEpd9A72joUz6Q0Ri scCSofKK3GV8Ov5fvjqOhnJl6zzagt2pKBE4HMMzvEdr1M+SgRk0a3HbRQKMHVljbSrsA7 Q0yYlLmIWXeKFlNC8gpNWJjjN8KKaGTvLbHgXvUGjm9l/NEKf323cjVdKKFbpA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1732833035; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=STB9Xp8RPHykOZtZUboSY9JLbUrK76OO1irMSu8LVzM=; b=WwiCF1MdemDbTxJ4oD3BYYDYVWXHeZUdIsZBQczNqn9nRHwZc7tRVUFLpJisHg71kc1QYS tGwBmLSld2b5/1Dg== To: Borislav Petkov , Dave Hansen , "H. Peter Anvin" Cc: Thomas Gleixner , John Ogness , linux-kernel@vger.kernel.org, x86@kernel.org, x86-cpuid@lists.linux.dev, "Ahmed S. Darwish" Subject: [PATCH v1 03/13] tools/x86/kcpuid: Fix error handling Date: Thu, 28 Nov 2024 23:29:38 +0100 Message-ID: <20241128222948.579920-4-darwi@linutronix.de> In-Reply-To: <20241128222948.579920-1-darwi@linutronix.de> References: <20241128222948.579920-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Error handling in kcpuid is unreliable: - on malloc() failures, the code prints an error then just goes on. - Error messages are printed to standard output, and thus getting mixed with cpuid flags listings. Introduce pr_err() and pr_warn() to automatically direct error and warning messages to standard error. Use such macros throughout the code. Introduce pr_err_exit(), which is like pr_err(), but with the addition of process termination through exit(3). Use pr_err_exit() in case of malloc() failures; further commits will utilize it further. Fixes: c6b2f240bf8d ("tools/x86: Add a kcpuid tool to show raw CPU features= ") Reported-by: Remington Brasga Closes: https://lkml.kernel.org/r/20240926223557.2048-1-rbrasga@uci.edu Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 54 +++++++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 11 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 62a77509a5b5..1ec60c892206 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 #define _GNU_SOURCE =20 +#include #include +#include #include #include #include @@ -111,6 +113,36 @@ static inline bool has_subleafs(u32 f) return false; } =20 +/** + * pr_err - Print passed error message to stderr + */ +static void pr_err(const char *fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + vfprintf(stderr, fmt, ap); + va_end(ap); +} + +/** + * pr_warn - Print passed warning message to stderr + */ +#define pr_warn(...) pr_err(__VA_ARGS__) + +/** + * pr_err_exit - Print passed error message to stderr, then exit + * + * @ecode: One-byte exit code. errno can be passed here as + * the passed value is quickly cached. + */ +#define pr_err_exit(ecode, ...) do { \ + int __ecode =3D (ecode); \ + \ + pr_err(__VA_ARGS__); \ + exit(__ecode); \ +} while (0) + static void leaf_print_raw(struct subleaf *leaf) { if (has_subleafs(leaf->index)) { @@ -145,14 +177,14 @@ static bool cpuid_store(struct cpuid_range *range, u3= 2 f, int subleaf, if (!func->leafs) { func->leafs =3D malloc(sizeof(struct subleaf)); if (!func->leafs) - perror("malloc func leaf"); + pr_err_exit(errno, "malloc func leaf"); =20 func->nr =3D 1; } else { s =3D func->nr; func->leafs =3D realloc(func->leafs, (s + 1) * sizeof(*leaf)); if (!func->leafs) - perror("realloc f->leafs"); + pr_err_exit(errno, "realloc f->leafs"); =20 func->nr++; } @@ -211,7 +243,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) =20 range =3D malloc(sizeof(struct cpuid_range)); if (!range) - perror("malloc range"); + pr_err_exit(errno, "malloc range"); =20 if (input_eax & 0x80000000) range->is_ext =3D true; @@ -220,7 +252,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) =20 range->funcs =3D malloc(sizeof(struct cpuid_func) * idx_func); if (!range->funcs) - perror("malloc range->funcs"); + pr_err_exit(errno, "malloc range->funcs"); =20 range->nr =3D idx_func; memset(range->funcs, 0, sizeof(struct cpuid_func) * idx_func); @@ -395,8 +427,8 @@ static int parse_line(char *line) return 0; =20 err_exit: - printf("Warning: wrong line format:\n"); - printf("\tline[%d]: %s\n", flines, line); + pr_warn("Warning: wrong line format:\n" + "\tline[%d]: %s\n", flines, line); return -1; } =20 @@ -419,7 +451,7 @@ static void parse_text(void) } =20 if (!file) { - printf("Fail to open '%s'\n", filename); + pr_err("Fail to open '%s'\n", filename); return; } =20 @@ -530,7 +562,7 @@ static inline struct cpuid_func *index_to_func(u32 inde= x) func_idx =3D index & 0xffff; =20 if ((func_idx + 1) > (u32)range->nr) { - printf("ERR: invalid input index (0x%x)\n", index); + pr_err("ERR: invalid input index (0x%x)\n", index); return NULL; } return &range->funcs[func_idx]; @@ -562,7 +594,7 @@ static void show_info(void) return; } =20 - printf("ERR: invalid input subleaf (0x%x)\n", user_sub); + pr_err("ERR: invalid input subleaf (0x%x)\n", user_sub); } =20 show_func(func); @@ -593,7 +625,7 @@ static void setup_platform_cpuid(void) =20 static void usage(void) { - printf("kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n" + pr_err("kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n" "\t-a|--all Show both bit flags and complex bit fields info\= n" "\t-b|--bitflags Show boolean flags only\n" "\t-d|--detail Show details of the flag/fields (default)\n" @@ -652,7 +684,7 @@ static int parse_options(int argc, char *argv[]) user_sub =3D strtoul(optarg, NULL, 0); break; default: - printf("%s: Invalid option '%c'\n", argv[0], optopt); + pr_err("%s: Invalid option '%c'\n", argv[0], optopt); return -1; } =20 --=20 2.46.2 From nobody Sat Feb 7 08:06:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FF5C1C4A3B for ; Thu, 28 Nov 2024 22:30:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Peter Anvin" Cc: Thomas Gleixner , John Ogness , linux-kernel@vger.kernel.org, x86@kernel.org, x86-cpuid@lists.linux.dev, "Ahmed S. Darwish" Subject: [PATCH v1 04/13] tools/x86/kcpuid: Remove unused local variable Date: Thu, 28 Nov 2024 23:29:39 +0100 Message-ID: <20241128222948.579920-5-darwi@linutronix.de> In-Reply-To: <20241128222948.579920-1-darwi@linutronix.de> References: <20241128222948.579920-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The local variable "index" is not used anywhere; remove it. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 1ec60c892206..201382da07c3 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -211,10 +211,6 @@ static void raw_dump_range(struct cpuid_range *range) =20 for (f =3D 0; (int)f < range->nr; f++) { struct cpuid_func *func =3D &range->funcs[f]; - u32 index =3D f; - - if (range->is_ext) - index +=3D 0x80000000; =20 /* Skip leaf without valid items */ if (!func->nr) --=20 2.46.2 From nobody Sat Feb 7 08:06:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29F3F1C9B66 for ; Thu, 28 Nov 2024 22:30:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833044; cv=none; b=TOvaoqnXibiyMxlGk9XQg5Gey6XGSpV1PB4OTI3sqxBZHVavKQ2fyz0lD9V9oomwWFfrxO65VRy7DjBGpys6XJ+0RJFzVXVD3fVIDwKA0ZYG3IwbRDA0wWBhYwjDFKgQsfnJYqgWQMIsqO1D2JOYswq0A0yeVNUExwrh75+3+n4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833044; c=relaxed/simple; bh=UZUGHTREonvFODoUi497eBP4JXHixDrArur8hUqjDt0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PX7+QslrvOYJd2joM2UFgaTsqgE0aiKWQyzpvwC3wFoJFosVrtleLy8NMpCLGqUqEI/nMQYFGK5tS2SQ+vV83Ah1UDm12L9GWsq24oTZR3WVyw5XH2n9PeUmqLig0IpzaJI5FZzU65m9rr6jZx72aW35N5WeyE2HsRYsjMj2aBY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=E7GKgru3; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=LuykBEmc; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="E7GKgru3"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="LuykBEmc" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1732833041; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UVk9Zx/OXlVTKxLRwmbKwDdTtB+nJJdTviCnYZ9iVe0=; b=E7GKgru3sjzx5nvdcr3GtObfKG5LMAPBK7oWOd7By00QxPV51FLI1yNeoHw+yNzkWxNXt/ VCkCts+s10oj8XrGeKQNJvz8l58qkktq9KGwcZEgj/21bYRRv4IHkQGYhevECx1VqTSA4Y DJXGmJLUotmqtWmlllUrOO5P5v6eJxNq7ndeytGtqhmjKthwE2OgPX5pnP6T3ObQooWPsd G8ioaLzi5zagHkRjWmj/3Buqc7AvDwxH0xBNdvH7qQsyjb9WXsrAP+QEFKfDQpfRs+QNJ9 SU617jFzGZcZ9BtAmKkz7J1KreaODsILxd0+UjaxqCRbcvPOXl4A+Op5J7BG1Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1732833041; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UVk9Zx/OXlVTKxLRwmbKwDdTtB+nJJdTviCnYZ9iVe0=; b=LuykBEmclyxlrKrMViTYe1eJtciblEe1YNugqdGEOqXcw8OyWZNjylzFsGHNAt2HkfaCEB sybWttvND8jhnKBA== To: Borislav Petkov , Dave Hansen , "H. Peter Anvin" Cc: Thomas Gleixner , John Ogness , linux-kernel@vger.kernel.org, x86@kernel.org, x86-cpuid@lists.linux.dev, "Ahmed S. Darwish" Subject: [PATCH v1 05/13] tools/x86/kcpuid: Remove unused global variable Date: Thu, 28 Nov 2024 23:29:40 +0100 Message-ID: <20241128222948.579920-6-darwi@linutronix.de> In-Reply-To: <20241128222948.579920-1-darwi@linutronix.de> References: <20241128222948.579920-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The global variable "is_amd" is not used anywhere; remove it. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 201382da07c3..ac8fdfdc4844 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -79,7 +79,6 @@ struct cpuid_range { */ struct cpuid_range *leafs_basic, *leafs_ext; =20 -static bool is_amd; static bool show_details; static bool show_raw; static bool show_flags_only =3D true; @@ -604,16 +603,6 @@ static void show_info(void) =20 static void setup_platform_cpuid(void) { - u32 eax, ebx, ecx, edx; - - /* Check vendor */ - eax =3D ebx =3D ecx =3D edx =3D 0; - cpuid(&eax, &ebx, &ecx, &edx); - - /* "htuA" */ - if (ebx =3D=3D 0x68747541) - is_amd =3D true; - /* Setup leafs for the basic and extended range */ leafs_basic =3D setup_cpuid_range(0x0); leafs_ext =3D setup_cpuid_range(0x80000000); --=20 2.46.2 From nobody Sat Feb 7 08:06:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DC2D1CB310 for ; Thu, 28 Nov 2024 22:30:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833047; cv=none; b=plZW/uFOLdH0G60s1dxxRH+G4IBQfYcE2HY8mUdF6PRQ819ezgcWwW5g+n8NRLb0kiOw6gcvCH21IF90weDBll1en+AiA/ksarcJ73eHCGtrlzkBzfmEANFtqnwyp+QRRWfMy6/QjgdaCGmXMSto5exLYSNRqYvs9uQ3lzo7BD8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833047; c=relaxed/simple; bh=hwGAJMLIEMvhV5pONSw35zuE2YThvMX9dCmE6oHPmiw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=o/uLUVNNF8JbhU6EEpmqh8vuarJ/4/aq9qyh9aBWu6ulOfg2wOMTNb3qAfgJr1WmaSTvw6Dk4W1Lrg/FvoyAE+Yzb/DygMZKzVf7jxbhk18+lBPGlPwcdEYr5RuzAsu8Ozj6YugfWmWdfUJPDfo7I6eOA9zPTcxshqXJpXoRBno= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=BZm6Mnww; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=G0yjPTMs; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="BZm6Mnww"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="G0yjPTMs" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1732833045; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qjNTHolP58a0KrsdLGdWmYpxO/AhmCfcO4oFNjtSLVU=; b=BZm6MnwwdYq7Gt54czS3v4JIP2iAXdkdPLxsYHFUKSlrANTEtIteC34v8TvEsoW0o3WdmN yFvd8sxgUxIMe2rcxEtpZL5J/1X/tABbn4hXeeOw4clOyrqVIpFrn7Rn7xtXX3V7hHnu6y IQk6V7Rrj0X4/UaXLNqjk7Sh2fZv5ymCCaHKnrXAkI3Ect/E9xbASDLwGzEpluMRBXw3au LSVoUUJx3dr1SppL7mHZhATAxBrSfxODSUsgH12lQeem89EbYOGWJHwbJvjXO1XmmCgd6G W9pu44NhOrum/dvblTnqK9D3Z1JtZ4JWnBDLoymK6+enmPAfVLfIDmaV3J6Oqg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1732833045; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qjNTHolP58a0KrsdLGdWmYpxO/AhmCfcO4oFNjtSLVU=; b=G0yjPTMsBROFGgLh3ctXtNQmsovETZiI130rwsmhFkXXYQUiQyKz4OCCQebza2OpNUhJcO /088PW+JgnB/lfDQ== To: Borislav Petkov , Dave Hansen , "H. Peter Anvin" Cc: Thomas Gleixner , John Ogness , linux-kernel@vger.kernel.org, x86@kernel.org, x86-cpuid@lists.linux.dev, "Ahmed S. Darwish" Subject: [PATCH v1 06/13] tools/x86/kcpuid: Simplify usage() handling Date: Thu, 28 Nov 2024 23:29:41 +0100 Message-ID: <20241128222948.579920-7-darwi@linutronix.de> In-Reply-To: <20241128222948.579920-1-darwi@linutronix.de> References: <20241128222948.579920-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Modify usage() to take a process exit_code parameter and directly call exit() after printing the usage string. This simplifies the callers' code paths. Remove the manual "Invalid option" error message at option parsing, since getopt_long(3) already prints sensible error messages by default. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index ac8fdfdc4844..c0f2eae0d694 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -11,6 +11,7 @@ =20 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) #define min(a, b) (((a) < (b)) ? (a) : (b)) +#define __noreturn __attribute__((__noreturn__)) =20 typedef unsigned int u32; typedef unsigned long long u64; @@ -608,9 +609,9 @@ static void setup_platform_cpuid(void) leafs_ext =3D setup_cpuid_range(0x80000000); } =20 -static void usage(void) +static void __noreturn usage(int exit_code) { - pr_err("kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n" + pr_err_exit(exit_code, "kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n" "\t-a|--all Show both bit flags and complex bit fields info\= n" "\t-b|--bitflags Show boolean flags only\n" "\t-d|--detail Show details of the flag/fields (default)\n" @@ -634,7 +635,7 @@ static struct option opts[] =3D { { NULL, 0, NULL, 0 } }; =20 -static int parse_options(int argc, char *argv[]) +static void parse_options(int argc, char *argv[]) { int c; =20 @@ -654,9 +655,7 @@ static int parse_options(int argc, char *argv[]) user_csv =3D optarg; break; case 'h': - usage(); - exit(1); - break; + usage(EXIT_SUCCESS); case 'l': /* main leaf */ user_index =3D strtoul(optarg, NULL, 0); @@ -669,11 +668,8 @@ static int parse_options(int argc, char *argv[]) user_sub =3D strtoul(optarg, NULL, 0); break; default: - pr_err("%s: Invalid option '%c'\n", argv[0], optopt); - return -1; - } - - return 0; + usage(EXIT_FAILURE); + } } =20 /* @@ -686,8 +682,7 @@ static int parse_options(int argc, char *argv[]) */ int main(int argc, char *argv[]) { - if (parse_options(argc, argv)) - return -1; + parse_options(argc, argv); =20 /* Setup the cpuid leafs of current platform */ setup_platform_cpuid(); --=20 2.46.2 From nobody Sat Feb 7 08:06:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73AF51CB9F2 for ; Thu, 28 Nov 2024 22:30:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833051; cv=none; b=O/x3jFdYlUQbcKUhuczHqQfiuQcCTYIMXQGbHQa04LbjNvBpUS+UQTye3y6K01JuaoTjkxg/vXd+bICs2AMwY11M33xnigcNHlawFtU9jrU/mvExtBnV9U3FJya61qavQV0r7tTz15Lh8BkHXPl4gjl47vWHo99t5pM9rnts9KU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833051; c=relaxed/simple; bh=2PInAe0s2nXQvmCvznhiKMoMdy+J1+CUdqPCCSLw2m0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QPHghDERnqVQaGImmIikx455URy4bluApnGaZxBoZRti5lgqN3NXMeh2AWCLQ1GHhPnxNSCsq/26gza0PSShdZ92PXUh5OCXAcSMJTH5Lp6JN7+C8kcfnCgL918TtWdOapzBIhWPl1e4loJjeI59jYdqlbAMT5zkFO9K+GATcXI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=jx87NKgh; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=cA2ImbZE; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="jx87NKgh"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="cA2ImbZE" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1732833048; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tvpZknr9BPOwYD8XZjsn0WZm5TwM0F8t2Y6GRW2245A=; b=jx87NKghxQBAXBiLc/Nfq+JvCKr9QHs/MPH5SWhhswunPve6afuD6S7CYsACfwRdp9Ce4s gwDb7D2Fv5hB1IOA87y8VufaEU0s802iiXChnZ4wn250cFuo0faNYFTNroHJyG+hiFLK5D NffN8EUgqOrWlnOUBgOkFG+X7XsKQZK/2ffHCcphRvocABjwLrUazyEiEOvq+OgefxYhed O6491F0yEJnAy51B52awLr2eDJuGi0a/WOOWGgezqj9kCVPrVmLXekMcoOT8ar+6HIuB7q n1KfBOM0ZfCzO8YhIzEYBnWbRNCU92lB8kxDktYeRazAsUdiLzAD8jXOp8N89Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1732833048; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tvpZknr9BPOwYD8XZjsn0WZm5TwM0F8t2Y6GRW2245A=; b=cA2ImbZEx1KxOKV0FwjhgmWxOutHCI9pRn5LXwL23Gg08jvQcmMRgBePpagp0Tq7DhIBUv MB4/lHoTfeT6MXAQ== To: Borislav Petkov , Dave Hansen , "H. Peter Anvin" Cc: Thomas Gleixner , John Ogness , linux-kernel@vger.kernel.org, x86@kernel.org, x86-cpuid@lists.linux.dev, "Ahmed S. Darwish" Subject: [PATCH v1 07/13] tools/x86/kcpuid: Prepare for more index ranges Date: Thu, 28 Nov 2024 23:29:42 +0100 Message-ID: <20241128222948.579920-8-darwi@linutronix.de> In-Reply-To: <20241128222948.579920-1-darwi@linutronix.de> References: <20241128222948.579920-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The kcpuid code assumes only two CPUID index ranges: standard functions (0x0...), and extended ones (0x80000000...). Since more cpuid index ranges will be added in the future, promote ranges selection from an "is_ext" boolean to enum-based classification. Collect all cpuid ranges in an array, now only two ranges, and introduce helpers to traverse that array or find a specific range withint it. Use such helpers throughout the kcpuid code. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 103 ++++++++++++++++++++------------- 1 file changed, 62 insertions(+), 41 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index c0f2eae0d694..245f55aa3170 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -66,19 +66,52 @@ struct cpuid_func { int nr; }; =20 +enum range_index { + RANGE_STD =3D 0, /* Standard */ + RANGE_EXT =3D 0x80000000, /* Extended */ +}; + +#define CPUID_INDEX_MASK 0x80000000 +#define CPUID_FUNCTION_MASK (~CPUID_INDEX_MASK) + struct cpuid_range { /* array of main leafs */ struct cpuid_func *funcs; /* number of valid leafs */ int nr; - bool is_ext; + enum range_index index; }; =20 -/* - * basic: basic functions range: [0... ] - * ext: extended functions range: [0x80000000... ] - */ -struct cpuid_range *leafs_basic, *leafs_ext; +static struct cpuid_range ranges[] =3D { + { .index =3D RANGE_STD, }, + { .index =3D RANGE_EXT, }, +}; + +static char *range_to_str(struct cpuid_range *range) +{ + switch (range->index) { + case RANGE_STD: return "Standard"; + case RANGE_EXT: return "Extended"; + default: return NULL; + } +} + +#define for_each_cpuid_range(range) \ + for (unsigned int i =3D 0; \ + i < ARRAY_SIZE(ranges) && ((range) =3D &ranges[i]); \ + i++) + +struct cpuid_range *index_to_cpuid_range(u32 index) +{ + struct cpuid_range *range; + + for_each_cpuid_range(range) { + if (range->index =3D=3D (index & CPUID_INDEX_MASK)) + return range; + } + + return NULL; +} =20 static bool show_details; static bool show_raw; @@ -206,7 +239,7 @@ static void raw_dump_range(struct cpuid_range *range) u32 f; int i; =20 - printf("%s Leafs :\n", range->is_ext ? "Extended" : "Basic"); + printf("%s Leafs :\n", range_to_str(range)); printf("=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"); =20 for (f =3D 0; (int)f < range->nr; f++) { @@ -223,29 +256,19 @@ static void raw_dump_range(struct cpuid_range *range) } =20 #define MAX_SUBLEAF_NUM 64 -struct cpuid_range *setup_cpuid_range(u32 input_eax) +void setup_cpuid_range(struct cpuid_range *range) { u32 max_func, idx_func, subleaf, max_subleaf; - u32 eax, ebx, ecx, edx, f =3D input_eax; - struct cpuid_range *range; + u32 eax, ebx, ecx, edx, f; bool allzero; =20 - eax =3D input_eax; + eax =3D f =3D range->index; ebx =3D ecx =3D edx =3D 0; =20 cpuid(&eax, &ebx, &ecx, &edx); max_func =3D eax; idx_func =3D (max_func & 0xffff) + 1; =20 - range =3D malloc(sizeof(struct cpuid_range)); - if (!range) - pr_err_exit(errno, "malloc range"); - - if (input_eax & 0x80000000) - range->is_ext =3D true; - else - range->is_ext =3D false; - range->funcs =3D malloc(sizeof(struct cpuid_func) * idx_func); if (!range->funcs) pr_err_exit(errno, "malloc range->funcs"); @@ -296,8 +319,6 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) } =20 } - - return range; } =20 /* @@ -356,13 +377,13 @@ static int parse_line(char *line) /* index/main-leaf */ index =3D strtoull(tokens[0], NULL, 0); =20 - if (index & 0x80000000) - range =3D leafs_ext; - else - range =3D leafs_basic; + /* Skip line parsing if it's not covered by known ranges */ + range =3D index_to_cpuid_range(index); + if (!range) + return -1; =20 - index &=3D 0x7FFFFFFF; /* Skip line parsing for non-existing indexes */ + index &=3D CPUID_FUNCTION_MASK; if ((int)index >=3D range->nr) return -1; =20 @@ -554,24 +575,28 @@ static inline struct cpuid_func *index_to_func(u32 in= dex) struct cpuid_range *range; u32 func_idx; =20 - range =3D (index & 0x80000000) ? leafs_ext : leafs_basic; - func_idx =3D index & 0xffff; + range =3D index_to_cpuid_range(index); + if (!range) + return NULL; =20 + func_idx =3D index & 0xffff; if ((func_idx + 1) > (u32)range->nr) { pr_err("ERR: invalid input index (0x%x)\n", index); return NULL; } + return &range->funcs[func_idx]; } =20 static void show_info(void) { + struct cpuid_range *range; struct cpuid_func *func; =20 if (show_raw) { /* Show all of the raw output of 'cpuid' instr */ - raw_dump_range(leafs_basic); - raw_dump_range(leafs_ext); + for_each_cpuid_range(range) + raw_dump_range(range); return; } =20 @@ -598,15 +623,8 @@ static void show_info(void) } =20 printf("CPU features:\n=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n\n"); - show_range(leafs_basic); - show_range(leafs_ext); -} - -static void setup_platform_cpuid(void) -{ - /* Setup leafs for the basic and extended range */ - leafs_basic =3D setup_cpuid_range(0x0); - leafs_ext =3D setup_cpuid_range(0x80000000); + for_each_cpuid_range(range) + show_range(range); } =20 static void __noreturn usage(int exit_code) @@ -682,10 +700,13 @@ static void parse_options(int argc, char *argv[]) */ int main(int argc, char *argv[]) { + struct cpuid_range *range; + parse_options(argc, argv); =20 /* Setup the cpuid leafs of current platform */ - setup_platform_cpuid(); + for_each_cpuid_range(range) + setup_cpuid_range(range); =20 /* Read and parse the 'cpuid.csv' */ parse_text(); --=20 2.46.2 From nobody Sat Feb 7 08:06:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97EAC1CBE97 for ; Thu, 28 Nov 2024 22:30:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833054; cv=none; b=Vced6YDxCV9i5pCg980T26a0yjp0kvqXthUSuKmZSWmtGFKC+95sRlAkpcUA2moi2g/5WlBUsNIwFlPDC4bxo6XtRT3Y3Z6j310sRnx2hdTzF5+bZ4C5CqeyJpF3dEl0aLA+QQg9l/+1hEwQWN6ZO3p5b+SMhvRCyy98mHux1mc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833054; c=relaxed/simple; bh=94WGLjzC4kHI0/O239FkrTbi4VOi0Cp4g9z4/scvzwk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bRDuhLckOwOripgWd5kPFOYZ7wpFCnWxmeuCkrDQAqm/zDXWEhrhn5f29zrG4okH33M+2CHpiv51Uf3A+Z9CPVVTTNDzrXCPxpEBWvb+VpSGwV6BKz7RsCzUVzXWOqYACvxm6qfIjWPQANHxC5xP1tgdosmzs0fBwU6KMuuBG0I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=aPsUkd6n; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=9yIzsKJP; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="aPsUkd6n"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="9yIzsKJP" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1732833051; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6FamdnxzWzyBduKaDhUirDNdvHzFku3acofJxSAPgSI=; b=aPsUkd6nBHwSzniTJnDo600OvPMy+swXwvxd1YEnM/KkEK3mLVAl1QmcrFpwmx7i/YK0yp qr0K9nmzr/XbW5MCUeDOArzl/tYDEUmaT/LClVUiyP/pt6gOGZoCrUZlw0VyTkamR9hSGf XR+NE74jlz7vIQYIPc+Rk0CXQVeCa/LsSNq0JaJ/uVOk3UfPRhaeCMNSkUB8S3vTw4pwrk 6+ov72VngRltO+dpyR4vD7xdwB35AUqDYpEjrWwNPuEqV+7lhrKw6rLRC78A81jNKQHhTx +J+aAdovAME0JEIaa05JrGmes2uesJRJagXbKyn3iIuB9BAQtprFHqr7I+DWgA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1732833051; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6FamdnxzWzyBduKaDhUirDNdvHzFku3acofJxSAPgSI=; b=9yIzsKJPjsdhLD/9h+MWujAXuT7UoWIV2LPrZSVb7NWKROoB309fAqbYz9XZ4aAYYvMiKu o6LYMPdxlUZP9QDQ== To: Borislav Petkov , Dave Hansen , "H. Peter Anvin" Cc: Thomas Gleixner , John Ogness , linux-kernel@vger.kernel.org, x86@kernel.org, x86-cpuid@lists.linux.dev, "Ahmed S. Darwish" Subject: [PATCH v1 08/13] tools/x86/kcpuid: Extend index mask macro Date: Thu, 28 Nov 2024 23:29:43 +0100 Message-ID: <20241128222948.579920-9-darwi@linutronix.de> In-Reply-To: <20241128222948.579920-1-darwi@linutronix.de> References: <20241128222948.579920-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the cpuid index mask macro from 0x80000000 to 0xffff0000, as Centaur indices in the range (0x80860000+) will be later added to the CSV file. This automatically sets the cpuid function mask macro to 0x0000ffff, its negation, which is the more correct value in general. Use that function mask macro in other places in the code as needed. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 245f55aa3170..bf0b4dd5b4e3 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -71,7 +71,7 @@ enum range_index { RANGE_EXT =3D 0x80000000, /* Extended */ }; =20 -#define CPUID_INDEX_MASK 0x80000000 +#define CPUID_INDEX_MASK 0xffff0000 #define CPUID_FUNCTION_MASK (~CPUID_INDEX_MASK) =20 struct cpuid_range { @@ -205,7 +205,7 @@ static bool cpuid_store(struct cpuid_range *range, u32 = f, int subleaf, * Cut off vendor-prefix from CPUID function as we're using it as an * index into ->funcs. */ - func =3D &range->funcs[f & 0xffff]; + func =3D &range->funcs[f & CPUID_FUNCTION_MASK]; =20 if (!func->leafs) { func->leafs =3D malloc(sizeof(struct subleaf)); @@ -267,7 +267,7 @@ void setup_cpuid_range(struct cpuid_range *range) =20 cpuid(&eax, &ebx, &ecx, &edx); max_func =3D eax; - idx_func =3D (max_func & 0xffff) + 1; + idx_func =3D (max_func & CPUID_FUNCTION_MASK) + 1; =20 range->funcs =3D malloc(sizeof(struct cpuid_func) * idx_func); if (!range->funcs) @@ -579,7 +579,7 @@ static inline struct cpuid_func *index_to_func(u32 inde= x) if (!range) return NULL; =20 - func_idx =3D index & 0xffff; + func_idx =3D index & CPUID_FUNCTION_MASK; if ((func_idx + 1) > (u32)range->nr) { pr_err("ERR: invalid input index (0x%x)\n", index); return NULL; --=20 2.46.2 From nobody Sat Feb 7 08:06:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0F3F1CC153 for ; Thu, 28 Nov 2024 22:30:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833057; cv=none; b=AdZQNjJhB42PBa65ViB7rxXqnRE0W/lcBV3wagJ4O7qwG99qNEjixwdtTIQ7qHhPsxCZqx/nfb0CtGE6WE5jVddid7vooP3DMXIjeT/F11u+k4gYx/kcwmW1h0V8tX8jsIzTa/DqPgqsIi0zU40QiNZ/Mg2ZCPc7Am3hfHi6S6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833057; c=relaxed/simple; bh=eqphXXU+ajFLQ1I7gs5mjYwNZpiP0dQe89Xps7S3jNM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jS2OCIJYpjx7AZlaCaDVqKDutKrjz8EMsg6WKJRnuw1k88GfUh3+eA7kZ1ETTtEFO6ug2MRyyQeVLGeCuEhpRaqQVmqtQdUDE2k7TYgtTfWAvhALHjp/Y/1mY1MHNkTswf5vCidpz5bWpuPNwQgVP2uw4NQ8neOs3NzT9aqpVR8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=JHmElYwh; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=EMisl4iG; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="JHmElYwh"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="EMisl4iG" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1732833054; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=L4HSzWjbm/ROpXvi8MiJFtw09jlE1Tgz+SQql+ft5cY=; b=JHmElYwhMca9i24kniYvOQTWpMt2DvCFf+JsS/kt5CiVKhlyDrl+scm4GYq+XVcYiHMNYO Eqg+cGOc9A/1ih8QUmaOohtPftzrLDgIOMXaPAMxEEgIo1crCnivoZ0x5qVj8Ot8teMB2v 5DtRZ2PwLS3RV9bxDKn+li5qylv+J5U3o8VViD/Y6Dq3kbCGs8B5KBTiiV3u8j8ok8xvoP oeHQLj1wbaqUnZsQ3ZD/d/JsGucLdJ6GmQn4BWIb6dicZQ11865pphz58rc6/WOD3gA5Oz 4gUmaUIdjbaXnOGYlEftuXSW0MukbyknIYnnLJvS3JvMlf2pQx0DkloYntVzoQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1732833054; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=L4HSzWjbm/ROpXvi8MiJFtw09jlE1Tgz+SQql+ft5cY=; b=EMisl4iGHjaU0mWT4yPHfA2YU05srnJ1zMXz3UqOOyN9QOTSC4TwZNBoV6FbqO2iMl/itj 9yM7CEhN7iawm9Dg== To: Borislav Petkov , Dave Hansen , "H. Peter Anvin" Cc: Thomas Gleixner , John Ogness , linux-kernel@vger.kernel.org, x86@kernel.org, x86-cpuid@lists.linux.dev, "Ahmed S. Darwish" Subject: [PATCH v1 09/13] tools/x86/kcpuid: Add rudimentary vendors detection Date: Thu, 28 Nov 2024 23:29:44 +0100 Message-ID: <20241128222948.579920-10-darwi@linutronix.de> In-Reply-To: <20241128222948.579920-1-darwi@linutronix.de> References: <20241128222948.579920-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CSV file will be updated with indices that are only valid for vendors like Centaur or Transmeta. Thus, introduce rudimentary x86 vendor detection to kcpuid. For each known cpuid index range, list its compatible CPU vendors in a bitmask. Define vendor markers for Intel, AMD, Centaur, and Transmeta. Since fine-grained vendor classification is not needed, cover Hygons under AMD, and Zhaoxins under Centaur. Define a fallback marker for unknown vendors. Mark standard (0x0) and extended (0x80000000) index ranges as valid for all vendors, including unknown. This ensures that kcpuid still works in case of x86 vendor detection failure. Save the result of vendor detection at a "this_cpu_vendor" global, which will be utilized in further commits. Note, vendor detection is done only through leaf 0x0 EDX register, "CPU vendor ID string bytes 4 - 7". This is to avoid needlessly complicating the code. Complete x86 vendor detection can be later added as needed. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 65 +++++++++++++++++++++++++++++++--- 1 file changed, 61 insertions(+), 4 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index bf0b4dd5b4e3..9769da3e4494 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -9,12 +9,16 @@ #include #include =20 +typedef unsigned int u32; +typedef unsigned long long u64; + #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define BIT(x) (1UL << (x)) #define min(a, b) (((a) < (b)) ? (a) : (b)) #define __noreturn __attribute__((__noreturn__)) =20 -typedef unsigned int u32; -typedef unsigned long long u64; +#define fourcc(a, b, c, d) \ + ((u32)(a) | ((u32)(b) << 8) | ((u32)(c) << 16) | ((u32)(d) << 24)) =20 char *def_csv =3D "/usr/share/misc/cpuid.csv"; char *user_csv; @@ -66,6 +70,17 @@ struct cpuid_func { int nr; }; =20 +enum cpu_vendor { + VENDOR_INTEL =3D BIT(0), + VENDOR_AMD =3D BIT(1), /* includes Hygon */ + VENDOR_CENTAUR =3D BIT(2), /* includes Zhaoxin */ + VENDOR_TRANSMETA =3D BIT(3), + VENDOR_UNKNOWN =3D BIT(15), + VENDOR_ALL =3D ~0UL, +}; + +static enum cpu_vendor this_cpu_vendor; + enum range_index { RANGE_STD =3D 0, /* Standard */ RANGE_EXT =3D 0x80000000, /* Extended */ @@ -80,11 +95,17 @@ struct cpuid_range { /* number of valid leafs */ int nr; enum range_index index; + /* compatible cpu vendors */ + enum cpu_vendor vendors; }; =20 static struct cpuid_range ranges[] =3D { - { .index =3D RANGE_STD, }, - { .index =3D RANGE_EXT, }, + { .index =3D RANGE_STD, + .vendors =3D VENDOR_ALL, + }, + { .index =3D RANGE_EXT, + .vendors =3D VENDOR_ALL, + }, }; =20 static char *range_to_str(struct cpuid_range *range) @@ -146,6 +167,40 @@ static inline bool has_subleafs(u32 f) return false; } =20 +/* + * Leaf 0x0 EDX output, CPU vendor ID string bytes 4 - 7. + */ +enum { + EDX_INTEL =3D fourcc('i', 'n', 'e', 'I'), /* Genu_ineI_ntel */ + EDX_AMD =3D fourcc('e', 'n', 't', 'i'), /* Auth_enti_cAMD */ + EDX_HYGON =3D fourcc('n', 'G', 'e', 'n'), /* Hygo_nGen_uine */ + EDX_TRANSMETA =3D fourcc('i', 'n', 'e', 'T'), /* Genu_ineT_Mx86 */ + EDX_CENTAUR =3D fourcc('a', 'u', 'r', 'H'), /* Cent_aurH_auls */ + EDX_ZHAOXIN =3D fourcc('a', 'n', 'g', 'h'), /* Sh_angh_ai */ +}; + +static enum cpu_vendor identify_cpu_vendor(void) +{ + u32 eax =3D 0, ebx, ecx =3D 0, edx; + + cpuid(&eax, &ebx, &ecx, &edx); + + switch (edx) { + case EDX_INTEL: + return VENDOR_INTEL; + case EDX_AMD: + case EDX_HYGON: + return VENDOR_AMD; + case EDX_TRANSMETA: + return VENDOR_TRANSMETA; + case EDX_CENTAUR: + case EDX_ZHAOXIN: + return VENDOR_CENTAUR; + default: + return VENDOR_UNKNOWN; + } +} + /** * pr_err - Print passed error message to stderr */ @@ -704,6 +759,8 @@ int main(int argc, char *argv[]) =20 parse_options(argc, argv); =20 + this_cpu_vendor =3D identify_cpu_vendor(); + /* Setup the cpuid leafs of current platform */ for_each_cpuid_range(range) setup_cpuid_range(range); --=20 2.46.2 From nobody Sat Feb 7 08:06:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15DBC1C760A for ; Thu, 28 Nov 2024 22:30:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833060; cv=none; b=AKj5/OEMstfhBN/STiA+nBN3JfGZa2IpOpJJaOcjXMPzE6pXpBE12sIOoCDSMffRLmmCvdxpSt9Oh9GBYE3IqhucLoYmf9Zms83W7Qeftil8xhnL4LnS/50spmmsVOnUem085e8ocANuttt/0vRk9o5y+Am40D4zAWBGXVOcUK4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833060; c=relaxed/simple; bh=7yfsx9umgJEwmzn7IyrywWo5n0hNfH4QCALT0PYiz4g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tO/ju0lmLvJh2Ve67oqUBAHhUe+uPnwQ0sNMt03juiSVAXDnasM2k0wzmXHRuSh3YSDOsm1JJv/nhTWp/3wZEkiwDbetIhuuTDjkk2SEXFXhPkWZlZrGMWU9WoBxS1GTESz+2x1Gwt4sOEDRbCMbdHYeSCx7uB7Dj2kLjSkkOyU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=j0xU6yN2; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=iZDIssCT; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="j0xU6yN2"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="iZDIssCT" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1732833057; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=D06RX2KzUMmEivATJHBJLOB3vqBKk+5nvdsg+oOA1+k=; b=j0xU6yN2YFSq1AoUgq8mcO5YaXsR023+trmXQaRnM5hO42nyjedSPS2XgfSlSqP3nIy4Uh Z8Wi5ZzENXRGZOgZW3CHwbedZ4/hPSim3x8rf0D433atNf4qwAFZFsaNPLPb3hacy3saS6 OXePDjht5UNXkS6zezzeLEvzrOstSN8U88/S46iCDECcNxVU2KRd+YGpkeVMlavXtCGOD3 Ni27EauO7s7IZBAqviJJWOr5dmQUss75QAxz+RyRVxBDEwrXd7iiiQVREhJ8ZBTCqjbp0E ORBrloZMDLN8AimLRdXpWGHde3P+B86N4uiPHCdQ+ggDa5peYBh2mKpWyGkSXA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1732833057; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=D06RX2KzUMmEivATJHBJLOB3vqBKk+5nvdsg+oOA1+k=; b=iZDIssCT+vPDApigcQELkkpLrNA2uhSWnJZX9eJPsWVuPuJYzk11AQVNJICIezkdh/2g2F /2mD+6MZUVcHI4Bw== To: Borislav Petkov , Dave Hansen , "H. Peter Anvin" Cc: Thomas Gleixner , John Ogness , linux-kernel@vger.kernel.org, x86@kernel.org, x86-cpuid@lists.linux.dev, "Ahmed S. Darwish" Subject: [PATCH v1 10/13] tools/x86/kcpuid: Scan valid cpuid ranges only Date: Thu, 28 Nov 2024 23:29:45 +0100 Message-ID: <20241128222948.579920-11-darwi@linutronix.de> In-Reply-To: <20241128222948.579920-1-darwi@linutronix.de> References: <20241128222948.579920-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" kcpuid works in two runs: one run for invoking cpuid instructions and saving all output in-memory, and another run for parsing that in-memory output using the CSV bitfields specification. CPU vendor detection was just added in previous commits. In both kcpuid runs, it makes no sense to deal with cpuid ranges that are not valid for the current CPU. Avoid ugly "is range valid for CPU?" conditionals throughout the code by modifying the for_each_cpuid_range() macro to iterate over cpuid ranges that are only known to be valid for the current CPU. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 9769da3e4494..f798c909c7b2 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -119,7 +119,9 @@ static char *range_to_str(struct cpuid_range *range) =20 #define for_each_cpuid_range(range) \ for (unsigned int i =3D 0; \ - i < ARRAY_SIZE(ranges) && ((range) =3D &ranges[i]); \ + i < ARRAY_SIZE(ranges) && \ + ((range) =3D &ranges[i]) && \ + (range->vendors & this_cpu_vendor); \ i++) =20 struct cpuid_range *index_to_cpuid_range(u32 index) --=20 2.46.2 From nobody Sat Feb 7 08:06:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 114DA1CC8A4 for ; Thu, 28 Nov 2024 22:31:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833063; cv=none; b=aiDvmuF9nz5GsxLiRds4KhHBcTV9rIEqcb32Dm61xjmiVaBIu49kkxvevurRiYgIYk4YwPKwHYW2KhXYteqtUJThJztCt6nVe0cTD8HFcBgcb5tKMAk+cgX+rFw68L8/mesqujQXKvLuBMsNy6KYeBJMM0hkEsq09gpypkr29U8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833063; c=relaxed/simple; bh=Z+9+UJ9mnckjuCxjROuK/seexi3WJPPqYlKCwsAo8gs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JzMYdx+umN/iIhAUmrx9rzsYaZXGwI7ziiAlxzJeL91tblcteLQqKjE7hBaElL+Tl2LeXSh6NF/GHj+QwwiM7P8iE71UVgDqLbJWustrrkv/4Mq1cZbGkkoBMhDKfS+PhRTRTsOdbARKsDhSmqdUn7mLf1ORYs30sW38CgfiQvw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Sz6sGFUI; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=yF2EJ4/k; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Sz6sGFUI"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="yF2EJ4/k" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1732833060; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DsSTFWrpgkoFqZy5HCPvPri/uIHQpajPEHBfRC46xw4=; b=Sz6sGFUI0BZ+tOGR6B01MGWrXkvEl/GccLQvPnje4gPOVHo1Zi+N6NyuRa6e3l1/tuDVWl 46UBOOdun1DJEM25l8FGsEZ8kSurXqTHN7hCbojqo2IhZokVQlWaUTPSUZlATbS0dawomL pauGBV8GBoz4cfbNaKmN3K9glVpsRMdtNEpZSgN0YIJTHyZqI44OktJiv3UcrbFMyev0S1 Q4M8b80P/qa2gGfKy5U7TmaY/EiQti7I/tfulZKxgJVxxSf4lMjPz7mzmZRF/weTr/TSo6 Rlda7X8Y/C/nAjhb7XJBG6FFgIFb2rs3mNAnwp+HVttxsn3H5UJ0JFHa619N7w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1732833060; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DsSTFWrpgkoFqZy5HCPvPri/uIHQpajPEHBfRC46xw4=; b=yF2EJ4/k1FdMagcDRlaFUWZ/X5iAETlEio6+TckR2WopjORcAXhDSdbvlNU1MV885U6yuY exaoViNSu2aam4BQ== To: Borislav Petkov , Dave Hansen , "H. Peter Anvin" Cc: Thomas Gleixner , John Ogness , linux-kernel@vger.kernel.org, x86@kernel.org, x86-cpuid@lists.linux.dev, "Ahmed S. Darwish" Subject: [PATCH v1 11/13] tools/x86/kcpuid: Add Transmeta and Centaur ranges Date: Thu, 28 Nov 2024 23:29:46 +0100 Message-ID: <20241128222948.579920-12-darwi@linutronix.de> In-Reply-To: <20241128222948.579920-1-darwi@linutronix.de> References: <20241128222948.579920-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Transmeta (0x80860000) and Centaur/Zhaoxin (0xc0000000) leaf index ranges, as the CSV file will be updated with exclusive entries for each. Note, without explicitly adding such ranges, their respective indices will get skipped during CSV bitfield parsing. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index f798c909c7b2..5656571f6066 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -84,6 +84,8 @@ static enum cpu_vendor this_cpu_vendor; enum range_index { RANGE_STD =3D 0, /* Standard */ RANGE_EXT =3D 0x80000000, /* Extended */ + RANGE_TSM =3D 0x80860000, /* Transmeta */ + RANGE_CTR =3D 0xc0000000, /* Centaur/Zhaoxin */ }; =20 #define CPUID_INDEX_MASK 0xffff0000 @@ -106,6 +108,12 @@ static struct cpuid_range ranges[] =3D { { .index =3D RANGE_EXT, .vendors =3D VENDOR_ALL, }, + { .index =3D RANGE_TSM, + .vendors =3D VENDOR_TRANSMETA, + }, + { .index =3D RANGE_CTR, + .vendors =3D VENDOR_CENTAUR, + }, }; =20 static char *range_to_str(struct cpuid_range *range) @@ -113,6 +121,8 @@ static char *range_to_str(struct cpuid_range *range) switch (range->index) { case RANGE_STD: return "Standard"; case RANGE_EXT: return "Extended"; + case RANGE_TSM: return "Transmeta"; + case RANGE_CTR: return "Centaur"; default: return NULL; } } --=20 2.46.2 From nobody Sat Feb 7 08:06:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9629D1CCB2E for ; Thu, 28 Nov 2024 22:31:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833068; cv=none; b=WRAyc20qZlMohz9+dCiJqX2iIMztkLUqnGNN8h8+jFOIcehMM/qt3BM7f9J1VqAeL9UdWlzft6++oYlYSPAoM7B1AB9U+hfC4LMAlobA/L//5A7XgfXn+zg0Zle4+X2xA5XNZYRFAq06oMLJ4Y1qKTJ2J0GLuMaJqkchrB8LzUI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732833068; c=relaxed/simple; bh=9Sh+HymjyxNI1SF7R9LZnzcyQu8fNll7tSY2HkcQAW0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MZ67zlZCyAhUISldP9HJcwoWUtv0d5N7XjaCq7W6KzF87PKM3DcMfReDsuvqzv1kztSr937RKyz790CRRDDEzwcZaDqG0mag9yos+Uh6JqbFixwt4XaQSYef3waEcR2MSeR2Ht9W1U++yrpHGUKfXZBiUq8BB+ANy8vGq/gQwkA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=uA5izby3; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=+iYp0QrF; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="uA5izby3"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="+iYp0QrF" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1732833064; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=N4dO8vJW38ocH+YeH7zA9cpgyw832YvkCPKtCeZShPU=; b=uA5izby34bHulI2aX4mkS8m8DSm02X1LD59B/4C4OxlWqsqM66o33fxjGLo7e74Thhm/Y0 vlwXCn+Sxprz9Buip9zkPKxlSACQhDLPqtqoj+xJ6McDZtTXHJk956UCKGdvP0BoTsheOg hskmEegWv83MKkJGlO72/YRCPEeZ1CawuL9252e7olWRbqFlN83R78J/ig7piTe7tTQtRx DbsllTcw1wNY26IyH24uvnr/ZwuFlEQYvPP86VjOE6VzlDcn5RO8OC90Q3/SYXVL3zWfcC /tuGNWo9AP8Q9EF7J7tAbN6b5UWHJWmSNjnAbW+xvl1dN/w78COCCZjqX0BBUA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1732833064; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=N4dO8vJW38ocH+YeH7zA9cpgyw832YvkCPKtCeZShPU=; b=+iYp0QrF5CYhrBho4sKhTerafIcbKozDhgbWgKXFv6Op5Yzd/EJXve5TQF4GI2pvhTxq6+ Ql6yjSjN6ZFcyvBA== To: Borislav Petkov , Dave Hansen , "H. Peter Anvin" Cc: Thomas Gleixner , John Ogness , linux-kernel@vger.kernel.org, x86@kernel.org, x86-cpuid@lists.linux.dev, "Ahmed S. Darwish" Subject: [PATCH v1 12/13] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.0 Date: Thu, 28 Nov 2024 23:29:47 +0100 Message-ID: <20241128222948.579920-13-darwi@linutronix.de> In-Reply-To: <20241128222948.579920-1-darwi@linutronix.de> References: <20241128222948.579920-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update kcpuid's bitfields CSV file to version v2.0, as generated by the x86-cpuid-db project. Changes summary: * Prefix the IDs of leaves 0x0 to 0x9 with `0x` to maintain consistency with the rest of the file. * Introduce the bitfields: - Leaf 0x7, subleaf 1, bit 20: `nmi_src` (NMI-source reporting with FRED event data). Thanks to Sohil Mehta / Intel. - Leaf 0x80000001, bits 2 and 23: `e_base_type` (Base CPU Type / Transmeta), and `e_mmx` (MMX instructions / Transmeta.) * Update the section headers for leaves 0x80000000 and 0x80000005 to indicate they're also valid for Transmeta CPUs. * Introduce the leaves: - Leaf 0x3, Transmeta Processor serial number - Leaf 0x80860000, Transmeta max leaf number + CPU vendor ID - Leaf 0x80860001, Transmeta extended CPU information - Leaf 0x80860002, Transmeta Code Morphing Software enumeration - Leaves 0x80860003 =3D> 0x80860006, Transmeta CPU information string - Leaf 0x80860007, Transmeta live CPU information - Leaf 0xc0000000, Centaur/Zhaoxin's max leaf number - Leaf 0xc0000001, Centaur/Zhaoxin's extended CPU features Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db Link: https://lore.kernel.org/x86-cpuid/ZwU0HtmCTj2rF2T8@lx-t490 --- tools/arch/x86/kcpuid/cpuid.csv | 648 +++++++++++++++++++------------- 1 file changed, 382 insertions(+), 266 deletions(-) diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.= csv index d751eb8585d0..d0f7159f99ba 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,5 +1,5 @@ # SPDX-License-Identifier: CC0-1.0 -# Generator: x86-cpuid-db v1.0 +# Generator: x86-cpuid-db v2.0 =20 # # Auto-generated file. @@ -12,297 +12,306 @@ # Leaf 0H # Maximum standard leaf number + CPU vendor string =20 - 0, 0, eax, 31:0, max_std_leaf , Highest = cpuid standard leaf supported - 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vend= or ID string bytes 0 - 3 - 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vend= or ID string bytes 8 - 11 - 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vend= or ID string bytes 4 - 7 + 0x0, 0, eax, 31:0, max_std_leaf , Highest = cpuid standard leaf supported + 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vend= or ID string bytes 0 - 3 + 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vend= or ID string bytes 8 - 11 + 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vend= or ID string bytes 4 - 7 =20 # Leaf 1H # CPU FMS (Family/Model/Stepping) + standard feature flags =20 - 1, 0, eax, 3:0, stepping , Stepping= ID - 1, 0, eax, 7:4, base_model , Base CPU= model ID - 1, 0, eax, 11:8, base_family_id , Base CPU= family ID - 1, 0, eax, 13:12, cpu_type , CPU type - 1, 0, eax, 19:16, ext_model , Extended= CPU model ID - 1, 0, eax, 27:20, ext_family , Extended= CPU family ID - 1, 0, ebx, 7:0, brand_id , Brand in= dex - 1, 0, ebx, 15:8, clflush_size , CLFLUSH = instruction cache line size - 1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU (HW threads) count - 1, 0, ebx, 31:24, local_apic_id , Initial = local APIC physical ID - 1, 0, ecx, 0, pni , Streamin= g SIMD Extensions 3 (SSE3) - 1, 0, ecx, 1, pclmulqdq , PCLMULQD= Q instruction support - 1, 0, ecx, 2, dtes64 , 64-bit D= S save area - 1, 0, ecx, 3, monitor , MONITOR/= MWAIT support - 1, 0, ecx, 4, ds_cpl , CPL Qual= ified Debug Store - 1, 0, ecx, 5, vmx , Virtual = Machine Extensions - 1, 0, ecx, 6, smx , Safer Mo= de Extensions - 1, 0, ecx, 7, est , Enhanced= Intel SpeedStep - 1, 0, ecx, 8, tm2 , Thermal = Monitor 2 - 1, 0, ecx, 9, ssse3 , Suppleme= ntal SSE3 - 1, 0, ecx, 10, cid , L1 Conte= xt ID - 1, 0, ecx, 11, sdbg , Sillicon= Debug - 1, 0, ecx, 12, fma , FMA exte= nsions using YMM state - 1, 0, ecx, 13, cx16 , CMPXCHG1= 6B instruction support - 1, 0, ecx, 14, xtpr , xTPR Upd= ate Control - 1, 0, ecx, 15, pdcm , Perfmon = and Debug Capability - 1, 0, ecx, 17, pcid , Process-= context identifiers - 1, 0, ecx, 18, dca , Direct C= ache Access - 1, 0, ecx, 19, sse4_1 , SSE4.1 - 1, 0, ecx, 20, sse4_2 , SSE4.2 - 1, 0, ecx, 21, x2apic , X2APIC s= upport - 1, 0, ecx, 22, movbe , MOVBE in= struction support - 1, 0, ecx, 23, popcnt , POPCNT i= nstruction support - 1, 0, ecx, 24, tsc_deadline_timer , APIC tim= er one-shot operation - 1, 0, ecx, 25, aes , AES inst= ructions - 1, 0, ecx, 26, xsave , XSAVE (a= nd related instructions) support - 1, 0, ecx, 27, osxsave , XSAVE (a= nd related instructions) are enabled by OS - 1, 0, ecx, 28, avx , AVX inst= ructions support - 1, 0, ecx, 29, f16c , Half-pre= cision floating-point conversion support - 1, 0, ecx, 30, rdrand , RDRAND i= nstruction support - 1, 0, ecx, 31, guest_status , System i= s running as guest; (para-)virtualized system - 1, 0, edx, 0, fpu , Floating= -Point Unit on-chip (x87) - 1, 0, edx, 1, vme , Virtual-= 8086 Mode Extensions - 1, 0, edx, 2, de , Debuggin= g Extensions - 1, 0, edx, 3, pse , Page Siz= e Extension - 1, 0, edx, 4, tsc , Time Sta= mp Counter - 1, 0, edx, 5, msr , Model-Sp= ecific Registers (RDMSR and WRMSR support) - 1, 0, edx, 6, pae , Physical= Address Extensions - 1, 0, edx, 7, mce , Machine = Check Exception - 1, 0, edx, 8, cx8 , CMPXCHG8= B instruction - 1, 0, edx, 9, apic , APIC on-= chip - 1, 0, edx, 11, sep , SYSENTER= , SYSEXIT, and associated MSRs - 1, 0, edx, 12, mtrr , Memory T= ype Range Registers - 1, 0, edx, 13, pge , Page Glo= bal Extensions - 1, 0, edx, 14, mca , Machine = Check Architecture - 1, 0, edx, 15, cmov , Conditio= nal Move Instruction - 1, 0, edx, 16, pat , Page Att= ribute Table - 1, 0, edx, 17, pse36 , Page Siz= e Extension (36-bit) - 1, 0, edx, 18, pn , Processo= r Serial Number - 1, 0, edx, 19, clflush , CLFLUSH = instruction - 1, 0, edx, 21, dts , Debug St= ore - 1, 0, edx, 22, acpi , Thermal = monitor and clock control - 1, 0, edx, 23, mmx , MMX inst= ructions - 1, 0, edx, 24, fxsr , FXSAVE a= nd FXRSTOR instructions - 1, 0, edx, 25, sse , SSE inst= ructions - 1, 0, edx, 26, sse2 , SSE2 ins= tructions - 1, 0, edx, 27, ss , Self Sno= op - 1, 0, edx, 28, ht , Hyper-th= reading - 1, 0, edx, 29, tm , Thermal = Monitor - 1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now resreved - 1, 0, edx, 31, pbe , Pending = Break Enable + 0x1, 0, eax, 3:0, stepping , Stepping= ID + 0x1, 0, eax, 7:4, base_model , Base CPU= model ID + 0x1, 0, eax, 11:8, base_family_id , Base CPU= family ID + 0x1, 0, eax, 13:12, cpu_type , CPU type + 0x1, 0, eax, 19:16, ext_model , Extended= CPU model ID + 0x1, 0, eax, 27:20, ext_family , Extended= CPU family ID + 0x1, 0, ebx, 7:0, brand_id , Brand in= dex + 0x1, 0, ebx, 15:8, clflush_size , CLFLUSH = instruction cache line size + 0x1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU (HW threads) count + 0x1, 0, ebx, 31:24, local_apic_id , Initial = local APIC physical ID + 0x1, 0, ecx, 0, pni , Streamin= g SIMD Extensions 3 (SSE3) + 0x1, 0, ecx, 1, pclmulqdq , PCLMULQD= Q instruction support + 0x1, 0, ecx, 2, dtes64 , 64-bit D= S save area + 0x1, 0, ecx, 3, monitor , MONITOR/= MWAIT support + 0x1, 0, ecx, 4, ds_cpl , CPL Qual= ified Debug Store + 0x1, 0, ecx, 5, vmx , Virtual = Machine Extensions + 0x1, 0, ecx, 6, smx , Safer Mo= de Extensions + 0x1, 0, ecx, 7, est , Enhanced= Intel SpeedStep + 0x1, 0, ecx, 8, tm2 , Thermal = Monitor 2 + 0x1, 0, ecx, 9, ssse3 , Suppleme= ntal SSE3 + 0x1, 0, ecx, 10, cid , L1 Conte= xt ID + 0x1, 0, ecx, 11, sdbg , Sillicon= Debug + 0x1, 0, ecx, 12, fma , FMA exte= nsions using YMM state + 0x1, 0, ecx, 13, cx16 , CMPXCHG1= 6B instruction support + 0x1, 0, ecx, 14, xtpr , xTPR Upd= ate Control + 0x1, 0, ecx, 15, pdcm , Perfmon = and Debug Capability + 0x1, 0, ecx, 17, pcid , Process-= context identifiers + 0x1, 0, ecx, 18, dca , Direct C= ache Access + 0x1, 0, ecx, 19, sse4_1 , SSE4.1 + 0x1, 0, ecx, 20, sse4_2 , SSE4.2 + 0x1, 0, ecx, 21, x2apic , X2APIC s= upport + 0x1, 0, ecx, 22, movbe , MOVBE in= struction support + 0x1, 0, ecx, 23, popcnt , POPCNT i= nstruction support + 0x1, 0, ecx, 24, tsc_deadline_timer , APIC tim= er one-shot operation + 0x1, 0, ecx, 25, aes , AES inst= ructions + 0x1, 0, ecx, 26, xsave , XSAVE (a= nd related instructions) support + 0x1, 0, ecx, 27, osxsave , XSAVE (a= nd related instructions) are enabled by OS + 0x1, 0, ecx, 28, avx , AVX inst= ructions support + 0x1, 0, ecx, 29, f16c , Half-pre= cision floating-point conversion support + 0x1, 0, ecx, 30, rdrand , RDRAND i= nstruction support + 0x1, 0, ecx, 31, guest_status , System i= s running as guest; (para-)virtualized system + 0x1, 0, edx, 0, fpu , Floating= -Point Unit on-chip (x87) + 0x1, 0, edx, 1, vme , Virtual-= 8086 Mode Extensions + 0x1, 0, edx, 2, de , Debuggin= g Extensions + 0x1, 0, edx, 3, pse , Page Siz= e Extension + 0x1, 0, edx, 4, tsc , Time Sta= mp Counter + 0x1, 0, edx, 5, msr , Model-Sp= ecific Registers (RDMSR and WRMSR support) + 0x1, 0, edx, 6, pae , Physical= Address Extensions + 0x1, 0, edx, 7, mce , Machine = Check Exception + 0x1, 0, edx, 8, cx8 , CMPXCHG8= B instruction + 0x1, 0, edx, 9, apic , APIC on-= chip + 0x1, 0, edx, 11, sep , SYSENTER= , SYSEXIT, and associated MSRs + 0x1, 0, edx, 12, mtrr , Memory T= ype Range Registers + 0x1, 0, edx, 13, pge , Page Glo= bal Extensions + 0x1, 0, edx, 14, mca , Machine = Check Architecture + 0x1, 0, edx, 15, cmov , Conditio= nal Move Instruction + 0x1, 0, edx, 16, pat , Page Att= ribute Table + 0x1, 0, edx, 17, pse36 , Page Siz= e Extension (36-bit) + 0x1, 0, edx, 18, pn , Processo= r Serial Number + 0x1, 0, edx, 19, clflush , CLFLUSH = instruction + 0x1, 0, edx, 21, dts , Debug St= ore + 0x1, 0, edx, 22, acpi , Thermal = monitor and clock control + 0x1, 0, edx, 23, mmx , MMX inst= ructions + 0x1, 0, edx, 24, fxsr , FXSAVE a= nd FXRSTOR instructions + 0x1, 0, edx, 25, sse , SSE inst= ructions + 0x1, 0, edx, 26, sse2 , SSE2 ins= tructions + 0x1, 0, edx, 27, ss , Self Sno= op + 0x1, 0, edx, 28, ht , Hyper-th= reading + 0x1, 0, edx, 29, tm , Thermal = Monitor + 0x1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now resreved + 0x1, 0, edx, 31, pbe , Pending = Break Enable =20 # Leaf 2H # Intel cache and TLB information one-byte descriptors =20 - 2, 0, eax, 7:0, iteration_count , Number o= f times this CPUD leaf must be queried - 2, 0, eax, 15:8, desc1 , Descript= or #1 - 2, 0, eax, 23:16, desc2 , Descript= or #2 - 2, 0, eax, 30:24, desc3 , Descript= or #3 - 2, 0, eax, 31, eax_invalid , Descript= ors 1-3 are invalid if set - 2, 0, ebx, 7:0, desc4 , Descript= or #4 - 2, 0, ebx, 15:8, desc5 , Descript= or #5 - 2, 0, ebx, 23:16, desc6 , Descript= or #6 - 2, 0, ebx, 30:24, desc7 , Descript= or #7 - 2, 0, ebx, 31, ebx_invalid , Descript= ors 4-7 are invalid if set - 2, 0, ecx, 7:0, desc8 , Descript= or #8 - 2, 0, ecx, 15:8, desc9 , Descript= or #9 - 2, 0, ecx, 23:16, desc10 , Descript= or #10 - 2, 0, ecx, 30:24, desc11 , Descript= or #11 - 2, 0, ecx, 31, ecx_invalid , Descript= ors 8-11 are invalid if set - 2, 0, edx, 7:0, desc12 , Descript= or #12 - 2, 0, edx, 15:8, desc13 , Descript= or #13 - 2, 0, edx, 23:16, desc14 , Descript= or #14 - 2, 0, edx, 30:24, desc15 , Descript= or #15 - 2, 0, edx, 31, edx_invalid , Descript= ors 12-15 are invalid if set + 0x2, 0, eax, 7:0, iteration_count , Number o= f times this CPUD leaf must be queried + 0x2, 0, eax, 15:8, desc1 , Descript= or #1 + 0x2, 0, eax, 23:16, desc2 , Descript= or #2 + 0x2, 0, eax, 30:24, desc3 , Descript= or #3 + 0x2, 0, eax, 31, eax_invalid , Descript= ors 1-3 are invalid if set + 0x2, 0, ebx, 7:0, desc4 , Descript= or #4 + 0x2, 0, ebx, 15:8, desc5 , Descript= or #5 + 0x2, 0, ebx, 23:16, desc6 , Descript= or #6 + 0x2, 0, ebx, 30:24, desc7 , Descript= or #7 + 0x2, 0, ebx, 31, ebx_invalid , Descript= ors 4-7 are invalid if set + 0x2, 0, ecx, 7:0, desc8 , Descript= or #8 + 0x2, 0, ecx, 15:8, desc9 , Descript= or #9 + 0x2, 0, ecx, 23:16, desc10 , Descript= or #10 + 0x2, 0, ecx, 30:24, desc11 , Descript= or #11 + 0x2, 0, ecx, 31, ecx_invalid , Descript= ors 8-11 are invalid if set + 0x2, 0, edx, 7:0, desc12 , Descript= or #12 + 0x2, 0, edx, 15:8, desc13 , Descript= or #13 + 0x2, 0, edx, 23:16, desc14 , Descript= or #14 + 0x2, 0, edx, 30:24, desc15 , Descript= or #15 + 0x2, 0, edx, 31, edx_invalid , Descript= ors 12-15 are invalid if set + +# Leaf 3H +# Transmeta Processor Serial Number (PSN) + + 0x3, 0, eax, 31:0, cpu_psn_0 , Processo= r Serial Number bytes 0 - 3 + 0x3, 0, ebx, 31:0, cpu_psn_1 , Processo= r Serial Number bytes 4 - 7 + 0x3, 0, ecx, 31:0, cpu_psn_2 , Processo= r Serial Number bytes 8 - 11 + 0x3, 0, edx, 31:0, cpu_psn_3 , Processo= r Serial Number bytes 12 - 15 =20 # Leaf 4H # Intel deterministic cache parameters =20 - 4, 31:0, eax, 4:0, cache_type , Cache ty= pe field - 4, 31:0, eax, 7:5, cache_level , Cache le= vel (1-based) - 4, 31:0, eax, 8, cache_self_init , Self-ini= tialializing cache level - 4, 31:0, eax, 9, fully_associative , Fully-as= sociative cache - 4, 31:0, eax, 25:14, num_threads_sharing , Number l= ogical CPUs sharing this cache - 4, 31:0, eax, 31:26, num_cores_on_die , Number o= f cores in the physical package - 4, 31:0, ebx, 11:0, cache_linesize , System c= oherency line size (0-based) - 4, 31:0, ebx, 21:12, cache_npartitions , Physical= line partitions (0-based) - 4, 31:0, ebx, 31:22, cache_nways , Ways of = associativity (0-based) - 4, 31:0, ecx, 30:0, cache_nsets , Cache nu= mber of sets (0-based) - 4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/I= NVD not guaranteed for Remote Lower-Level caches - 4, 31:0, edx, 1, ll_inclusive , Cache is= inclusive of Lower-Level caches - 4, 31:0, edx, 2, complex_indexing , Not a di= rect-mapped cache (complex function) + 0x4, 31:0, eax, 4:0, cache_type , Cache ty= pe field + 0x4, 31:0, eax, 7:5, cache_level , Cache le= vel (1-based) + 0x4, 31:0, eax, 8, cache_self_init , Self-ini= tialializing cache level + 0x4, 31:0, eax, 9, fully_associative , Fully-as= sociative cache + 0x4, 31:0, eax, 25:14, num_threads_sharing , Number l= ogical CPUs sharing this cache + 0x4, 31:0, eax, 31:26, num_cores_on_die , Number o= f cores in the physical package + 0x4, 31:0, ebx, 11:0, cache_linesize , System c= oherency line size (0-based) + 0x4, 31:0, ebx, 21:12, cache_npartitions , Physical= line partitions (0-based) + 0x4, 31:0, ebx, 31:22, cache_nways , Ways of = associativity (0-based) + 0x4, 31:0, ecx, 30:0, cache_nsets , Cache nu= mber of sets (0-based) + 0x4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/I= NVD not guaranteed for Remote Lower-Level caches + 0x4, 31:0, edx, 1, ll_inclusive , Cache is= inclusive of Lower-Level caches + 0x4, 31:0, edx, 2, complex_indexing , Not a di= rect-mapped cache (complex function) =20 # Leaf 5H # MONITOR/MWAIT instructions enumeration =20 - 5, 0, eax, 15:0, min_mon_size , Smallest= monitor-line size, in bytes - 5, 0, ebx, 15:0, max_mon_size , Largest = monitor-line size, in bytes - 5, 0, ecx, 0, mwait_ext , Enumerat= ion of MONITOR/MWAIT extensions is supported - 5, 0, ecx, 1, mwait_irq_break , Interrup= ts as a break-event for MWAIT is supported - 5, 0, edx, 3:0, n_c0_substates , Number o= f C0 sub C-states supported using MWAIT - 5, 0, edx, 7:4, n_c1_substates , Number o= f C1 sub C-states supported using MWAIT - 5, 0, edx, 11:8, n_c2_substates , Number o= f C2 sub C-states supported using MWAIT - 5, 0, edx, 15:12, n_c3_substates , Number o= f C3 sub C-states supported using MWAIT - 5, 0, edx, 19:16, n_c4_substates , Number o= f C4 sub C-states supported using MWAIT - 5, 0, edx, 23:20, n_c5_substates , Number o= f C5 sub C-states supported using MWAIT - 5, 0, edx, 27:24, n_c6_substates , Number o= f C6 sub C-states supported using MWAIT - 5, 0, edx, 31:28, n_c7_substates , Number o= f C7 sub C-states supported using MWAIT + 0x5, 0, eax, 15:0, min_mon_size , Smallest= monitor-line size, in bytes + 0x5, 0, ebx, 15:0, max_mon_size , Largest = monitor-line size, in bytes + 0x5, 0, ecx, 0, mwait_ext , Enumerat= ion of MONITOR/MWAIT extensions is supported + 0x5, 0, ecx, 1, mwait_irq_break , Interrup= ts as a break-event for MWAIT is supported + 0x5, 0, edx, 3:0, n_c0_substates , Number o= f C0 sub C-states supported using MWAIT + 0x5, 0, edx, 7:4, n_c1_substates , Number o= f C1 sub C-states supported using MWAIT + 0x5, 0, edx, 11:8, n_c2_substates , Number o= f C2 sub C-states supported using MWAIT + 0x5, 0, edx, 15:12, n_c3_substates , Number o= f C3 sub C-states supported using MWAIT + 0x5, 0, edx, 19:16, n_c4_substates , Number o= f C4 sub C-states supported using MWAIT + 0x5, 0, edx, 23:20, n_c5_substates , Number o= f C5 sub C-states supported using MWAIT + 0x5, 0, edx, 27:24, n_c6_substates , Number o= f C6 sub C-states supported using MWAIT + 0x5, 0, edx, 31:28, n_c7_substates , Number o= f C7 sub C-states supported using MWAIT =20 # Leaf 6H # Thermal and Power Management enumeration =20 - 6, 0, eax, 0, dtherm , Digital = temprature sensor - 6, 0, eax, 1, turbo_boost , Intel Tu= rbo Boost - 6, 0, eax, 2, arat , Always-R= unning APIC Timer (not affected by p-state) - 6, 0, eax, 4, pln , Power Li= mit Notification (PLN) event - 6, 0, eax, 5, ecmd , Clock mo= dulation duty cycle extension - 6, 0, eax, 6, pts , Package = thermal management - 6, 0, eax, 7, hwp , HWP (Har= dware P-states) base registers are supported - 6, 0, eax, 8, hwp_notify , HWP noti= fication (IA32_HWP_INTERRUPT MSR) - 6, 0, eax, 9, hwp_act_window , HWP acti= vity window (IA32_HWP_REQUEST[bits 41:32]) supported - 6, 0, eax, 10, hwp_epp , HWP Ener= gy Performance Preference - 6, 0, eax, 11, hwp_pkg_req , HWP Pack= age Level Request - 6, 0, eax, 13, hdc_base_regs , HDC base= registers are supported - 6, 0, eax, 14, turbo_boost_3_0 , Intel Tu= rbo Boost Max 3.0 - 6, 0, eax, 15, hwp_capabilities , HWP High= est Performance change - 6, 0, eax, 16, hwp_peci_override , HWP PECI= override - 6, 0, eax, 17, hwp_flexible , Flexible= HWP - 6, 0, eax, 18, hwp_fast , IA32_HWP= _REQUEST MSR fast access mode - 6, 0, eax, 19, hfi , HW_FEEDB= ACK MSRs supported - 6, 0, eax, 20, hwp_ignore_idle , Ignoring= idle logical CPU HWP req is supported - 6, 0, eax, 23, thread_director , Intel th= read director support - 6, 0, eax, 24, therm_interrupt_bit25 , IA32_THE= RM_INTERRUPT MSR bit 25 is supported - 6, 0, ebx, 3:0, n_therm_thresholds , Digital = thermometer thresholds - 6, 0, ecx, 0, aperfmperf , MPERF/AP= ERF MSRs (effective frequency interface) - 6, 0, ecx, 3, epb , IA32_ENE= RGY_PERF_BIAS MSR support - 6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director - 6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting - 6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting - 6, 0, edx, 11:8, feedback_sz , HW feedb= ack interface struct size, in 4K pages - 6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU index @ HW feedback struct, 0-based + 0x6, 0, eax, 0, dtherm , Digital = temprature sensor + 0x6, 0, eax, 1, turbo_boost , Intel Tu= rbo Boost + 0x6, 0, eax, 2, arat , Always-R= unning APIC Timer (not affected by p-state) + 0x6, 0, eax, 4, pln , Power Li= mit Notification (PLN) event + 0x6, 0, eax, 5, ecmd , Clock mo= dulation duty cycle extension + 0x6, 0, eax, 6, pts , Package = thermal management + 0x6, 0, eax, 7, hwp , HWP (Har= dware P-states) base registers are supported + 0x6, 0, eax, 8, hwp_notify , HWP noti= fication (IA32_HWP_INTERRUPT MSR) + 0x6, 0, eax, 9, hwp_act_window , HWP acti= vity window (IA32_HWP_REQUEST[bits 41:32]) supported + 0x6, 0, eax, 10, hwp_epp , HWP Ener= gy Performance Preference + 0x6, 0, eax, 11, hwp_pkg_req , HWP Pack= age Level Request + 0x6, 0, eax, 13, hdc_base_regs , HDC base= registers are supported + 0x6, 0, eax, 14, turbo_boost_3_0 , Intel Tu= rbo Boost Max 3.0 + 0x6, 0, eax, 15, hwp_capabilities , HWP High= est Performance change + 0x6, 0, eax, 16, hwp_peci_override , HWP PECI= override + 0x6, 0, eax, 17, hwp_flexible , Flexible= HWP + 0x6, 0, eax, 18, hwp_fast , IA32_HWP= _REQUEST MSR fast access mode + 0x6, 0, eax, 19, hfi , HW_FEEDB= ACK MSRs supported + 0x6, 0, eax, 20, hwp_ignore_idle , Ignoring= idle logical CPU HWP req is supported + 0x6, 0, eax, 23, thread_director , Intel th= read director support + 0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THE= RM_INTERRUPT MSR bit 25 is supported + 0x6, 0, ebx, 3:0, n_therm_thresholds , Digital = thermometer thresholds + 0x6, 0, ecx, 0, aperfmperf , MPERF/AP= ERF MSRs (effective frequency interface) + 0x6, 0, ecx, 3, epb , IA32_ENE= RGY_PERF_BIAS MSR support + 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director + 0x6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting + 0x6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting + 0x6, 0, edx, 11:8, feedback_sz , HW feedb= ack interface struct size, in 4K pages + 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU index @ HW feedback struct, 0-based =20 # Leaf 7H # Extended CPU features enumeration =20 - 7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f cpuid 0x7 subleaves - 7, 0, ebx, 0, fsgsbase , FSBASE/G= SBASE read/write support - 7, 0, ebx, 1, tsc_adjust , IA32_TSC= _ADJUST MSR supported - 7, 0, ebx, 2, sgx , Intel SG= X (Software Guard Extensions) - 7, 0, ebx, 3, bmi1 , Bit mani= pulation extensions group 1 - 7, 0, ebx, 4, hle , Hardware= Lock Elision - 7, 0, ebx, 5, avx2 , AVX2 ins= truction set - 7, 0, ebx, 6, fdp_excptn_only , FPU Data= Pointer updated only on x87 exceptions - 7, 0, ebx, 7, smep , Supervis= or Mode Execution Protection - 7, 0, ebx, 8, bmi2 , Bit mani= pulation extensions group 2 - 7, 0, ebx, 9, erms , Enhanced= REP MOVSB/STOSB - 7, 0, ebx, 10, invpcid , INVPCID = instruction (Invalidate Processor Context ID) - 7, 0, ebx, 11, rtm , Intel re= stricted transactional memory - 7, 0, ebx, 12, cqm , Intel RD= T-CMT / AMD Platform-QoS cache monitoring - 7, 0, ebx, 13, zero_fcs_fds , Deprecat= ed FPU CS/DS (stored as zero) - 7, 0, ebx, 14, mpx , Intel me= mory protection extensions - 7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcemeent - 7, 0, ebx, 16, avx512f , AVX-512 = foundation instructions - 7, 0, ebx, 17, avx512dq , AVX-512 = double/quadword instructions - 7, 0, ebx, 18, rdseed , RDSEED i= nstruction - 7, 0, ebx, 19, adx , ADCX/ADO= X instructions - 7, 0, ebx, 20, smap , Supervis= or mode access prevention - 7, 0, ebx, 21, avx512ifma , AVX-512 = integer fused multiply add - 7, 0, ebx, 23, clflushopt , CLFLUSHO= PT instruction - 7, 0, ebx, 24, clwb , CLWB ins= truction - 7, 0, ebx, 25, intel_pt , Intel pr= ocessor trace - 7, 0, ebx, 26, avx512pf , AVX-512 = prefetch instructions - 7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instrs - 7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instrs - 7, 0, ebx, 29, sha_ni , SHA/SHA2= 56 instructions - 7, 0, ebx, 30, avx512bw , AVX-512 = BW (byte/word granular) instructions - 7, 0, ebx, 31, avx512vl , AVX-512 = VL (128/256 vector length) extensions - 7, 0, ecx, 0, prefetchwt1 , PREFETCH= WT1 (Intel Xeon Phi only) - 7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instrs - 7, 0, ecx, 2, umip , User mod= e instruction protection - 7, 0, ecx, 3, pku , Protecti= on keys for user-space - 7, 0, ecx, 4, ospke , OS prote= ction keys enable - 7, 0, ecx, 5, waitpkg , WAITPKG = instructions - 7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instrs group 2 - 7, 0, ecx, 7, cet_ss , CET shad= ow stack features - 7, 0, ecx, 8, gfni , Galois f= ield new instructions - 7, 0, ecx, 9, vaes , Vector A= ES instrs - 7, 0, ecx, 10, vpclmulqdq , VPCLMULQ= DQ 256-bit instruction support - 7, 0, ecx, 11, avx512_vnni , Vector n= eural network instructions - 7, 0, ecx, 12, avx512_bitalg , AVX-512 = bit count/shiffle - 7, 0, ecx, 13, tme , Intel to= tal memory encryption - 7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DW/QW - 7, 0, ecx, 16, la57 , 57-bit l= inear addreses (five-level paging) - 7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/B= NDSTX MAWAU value in 64-bit mode - 7, 0, ecx, 22, rdpid , RDPID in= struction - 7, 0, ecx, 23, key_locker , Intel ke= y locker support - 7, 0, ecx, 24, bus_lock_detect , OS bus-l= ock detection - 7, 0, ecx, 25, cldemote , CLDEMOTE= instruction - 7, 0, ecx, 27, movdiri , MOVDIRI = instruction - 7, 0, ecx, 28, movdir64b , MOVDIR64= B instruction - 7, 0, ecx, 29, enqcmd , Enqueue = stores supported (ENQCMD{,S}) - 7, 0, ecx, 30, sgx_lc , Intel SG= X launch configuration - 7, 0, ecx, 31, pks , Protecti= on keys for supervisor-mode pages - 7, 0, edx, 1, sgx_keys , Intel SG= X attestation services - 7, 0, edx, 2, avx512_4vnniw , AVX-512 = neural network instructions - 7, 0, edx, 3, avx512_4fmaps , AVX-512 = multiply accumulation single precision - 7, 0, edx, 4, fsrm , Fast sho= rt REP MOV - 7, 0, edx, 5, uintr , CPU supp= orts user interrupts - 7, 0, edx, 8, avx512_vp2intersect , VP2INTER= SECT{D,Q} instructions - 7, 0, edx, 9, srdbs_ctrl , SRBDS mi= tigation MSR available - 7, 0, edx, 10, md_clear , VERW MD_= CLEAR microcode support - 7, 0, edx, 11, rtm_always_abort , XBEGIN (= RTM transaction) always aborts - 7, 0, edx, 13, tsx_force_abort , MSR TSX_= FORCE_ABORT, RTM_ABORT bit, supported - 7, 0, edx, 14, serialize , SERIALIZ= E instruction - 7, 0, edx, 15, hybrid_cpu , The CPU = is identified as a 'hybrid part' - 7, 0, edx, 16, tsxldtrk , TSX susp= end/resume load address tracking - 7, 0, edx, 18, pconfig , PCONFIG = instruction - 7, 0, edx, 19, arch_lbr , Intel ar= chitectural LBRs - 7, 0, edx, 20, ibt , CET indi= rect branch tracking - 7, 0, edx, 22, amx_bf16 , AMX-BF16= : tile bfloat16 support - 7, 0, edx, 23, avx512_fp16 , AVX-512 = FP16 instructions - 7, 0, edx, 24, amx_tile , AMX-TILE= : tile architecture support - 7, 0, edx, 25, amx_int8 , AMX-INT8= : tile 8-bit integer support - 7, 0, edx, 26, spec_ctrl , Speculat= ion Control (IBRS/IBPB: indirect branch restrictions) - 7, 0, edx, 27, intel_stibp , Single t= hread indirect branch predictors - 7, 0, edx, 28, flush_l1d , FLUSH L1= D cache: IA32_FLUSH_CMD MSR - 7, 0, edx, 29, arch_capabilities , Intel IA= 32_ARCH_CAPABILITIES MSR - 7, 0, edx, 30, core_capabilities , IA32_COR= E_CAPABILITIES MSR - 7, 0, edx, 31, spec_ctrl_ssbd , Speculat= ive store bypass disable - 7, 1, eax, 4, avx_vnni , AVX-VNNI= instructions - 7, 1, eax, 5, avx512_bf16 , AVX-512 = bFloat16 instructions - 7, 1, eax, 6, lass , Linear a= ddress space separation - 7, 1, eax, 7, cmpccxadd , CMPccXAD= D instructions - 7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: CPUID leaf 0x23 is supported - 7, 1, eax, 10, fzrm , Fast zer= o-length REP MOVSB - 7, 1, eax, 11, fsrs , Fast sho= rt REP STOSB - 7, 1, eax, 12, fsrc , Fast Sho= rt REP CMPSB/SCASB - 7, 1, eax, 17, fred , FRED: Fl= exible return and event delivery transitions - 7, 1, eax, 18, lkgs , LKGS: Lo= ad 'kernel' (userspace) GS - 7, 1, eax, 19, wrmsrns , WRMSRNS = instr (WRMSR-non-serializing) - 7, 1, eax, 21, amx_fp16 , AMX-FP16= : FP16 tile operations - 7, 1, eax, 22, hreset , History = reset support - 7, 1, eax, 23, avx_ifma , Integer = fused multiply add - 7, 1, eax, 26, lam , Linear a= ddress masking - 7, 1, eax, 27, rd_wr_msrlist , RDMSRLIS= T/WRMSRLIST instructions - 7, 1, ebx, 0, intel_ppin , Protecte= d processor inventory number (PPIN{,_CTL} MSRs) - 7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI= -INT8 instructions - 7, 1, edx, 5, avx_ne_convert , AVX-NE-C= ONVERT instructions - 7, 1, edx, 8, amx_complex , AMX-COMP= LEX instructions (starting from Granite Rapids) - 7, 1, edx, 14, prefetchit_0_1 , PREFETCH= IT0/1 instructions - 7, 1, edx, 18, cet_sss , CET supe= rvisor shadow stacks safe to use - 7, 2, edx, 0, intel_psfd , Intel pr= edictive store forward disable - 7, 2, edx, 1, ipred_ctrl , MSR bits= IA32_SPEC_CTRL.IPRED_DIS_{U,S} - 7, 2, edx, 2, rrsba_ctrl , MSR bits= IA32_SPEC_CTRL.RRSBA_DIS_{U,S} - 7, 2, edx, 3, ddp_ctrl , MSR bit = IA32_SPEC_CTRL.DDPD_U - 7, 2, edx, 4, bhi_ctrl , MSR bit = IA32_SPEC_CTRL.BHI_DIS_S - 7, 2, edx, 5, mcdt_no , MCDT mit= igation not needed - 7, 2, edx, 6, uclock_disable , UC-lock = disable is supported + 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f cpuid 0x7 subleaves + 0x7, 0, ebx, 0, fsgsbase , FSBASE/G= SBASE read/write support + 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC= _ADJUST MSR supported + 0x7, 0, ebx, 2, sgx , Intel SG= X (Software Guard Extensions) + 0x7, 0, ebx, 3, bmi1 , Bit mani= pulation extensions group 1 + 0x7, 0, ebx, 4, hle , Hardware= Lock Elision + 0x7, 0, ebx, 5, avx2 , AVX2 ins= truction set + 0x7, 0, ebx, 6, fdp_excptn_only , FPU Data= Pointer updated only on x87 exceptions + 0x7, 0, ebx, 7, smep , Supervis= or Mode Execution Protection + 0x7, 0, ebx, 8, bmi2 , Bit mani= pulation extensions group 2 + 0x7, 0, ebx, 9, erms , Enhanced= REP MOVSB/STOSB + 0x7, 0, ebx, 10, invpcid , INVPCID = instruction (Invalidate Processor Context ID) + 0x7, 0, ebx, 11, rtm , Intel re= stricted transactional memory + 0x7, 0, ebx, 12, cqm , Intel RD= T-CMT / AMD Platform-QoS cache monitoring + 0x7, 0, ebx, 13, zero_fcs_fds , Deprecat= ed FPU CS/DS (stored as zero) + 0x7, 0, ebx, 14, mpx , Intel me= mory protection extensions + 0x7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcemeent + 0x7, 0, ebx, 16, avx512f , AVX-512 = foundation instructions + 0x7, 0, ebx, 17, avx512dq , AVX-512 = double/quadword instructions + 0x7, 0, ebx, 18, rdseed , RDSEED i= nstruction + 0x7, 0, ebx, 19, adx , ADCX/ADO= X instructions + 0x7, 0, ebx, 20, smap , Supervis= or mode access prevention + 0x7, 0, ebx, 21, avx512ifma , AVX-512 = integer fused multiply add + 0x7, 0, ebx, 23, clflushopt , CLFLUSHO= PT instruction + 0x7, 0, ebx, 24, clwb , CLWB ins= truction + 0x7, 0, ebx, 25, intel_pt , Intel pr= ocessor trace + 0x7, 0, ebx, 26, avx512pf , AVX-512 = prefetch instructions + 0x7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instrs + 0x7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instrs + 0x7, 0, ebx, 29, sha_ni , SHA/SHA2= 56 instructions + 0x7, 0, ebx, 30, avx512bw , AVX-512 = BW (byte/word granular) instructions + 0x7, 0, ebx, 31, avx512vl , AVX-512 = VL (128/256 vector length) extensions + 0x7, 0, ecx, 0, prefetchwt1 , PREFETCH= WT1 (Intel Xeon Phi only) + 0x7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instrs + 0x7, 0, ecx, 2, umip , User mod= e instruction protection + 0x7, 0, ecx, 3, pku , Protecti= on keys for user-space + 0x7, 0, ecx, 4, ospke , OS prote= ction keys enable + 0x7, 0, ecx, 5, waitpkg , WAITPKG = instructions + 0x7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instrs group 2 + 0x7, 0, ecx, 7, cet_ss , CET shad= ow stack features + 0x7, 0, ecx, 8, gfni , Galois f= ield new instructions + 0x7, 0, ecx, 9, vaes , Vector A= ES instrs + 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQ= DQ 256-bit instruction support + 0x7, 0, ecx, 11, avx512_vnni , Vector n= eural network instructions + 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 = bit count/shiffle + 0x7, 0, ecx, 13, tme , Intel to= tal memory encryption + 0x7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DW/QW + 0x7, 0, ecx, 16, la57 , 57-bit l= inear addreses (five-level paging) + 0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/B= NDSTX MAWAU value in 64-bit mode + 0x7, 0, ecx, 22, rdpid , RDPID in= struction + 0x7, 0, ecx, 23, key_locker , Intel ke= y locker support + 0x7, 0, ecx, 24, bus_lock_detect , OS bus-l= ock detection + 0x7, 0, ecx, 25, cldemote , CLDEMOTE= instruction + 0x7, 0, ecx, 27, movdiri , MOVDIRI = instruction + 0x7, 0, ecx, 28, movdir64b , MOVDIR64= B instruction + 0x7, 0, ecx, 29, enqcmd , Enqueue = stores supported (ENQCMD{,S}) + 0x7, 0, ecx, 30, sgx_lc , Intel SG= X launch configuration + 0x7, 0, ecx, 31, pks , Protecti= on keys for supervisor-mode pages + 0x7, 0, edx, 1, sgx_keys , Intel SG= X attestation services + 0x7, 0, edx, 2, avx512_4vnniw , AVX-512 = neural network instructions + 0x7, 0, edx, 3, avx512_4fmaps , AVX-512 = multiply accumulation single precision + 0x7, 0, edx, 4, fsrm , Fast sho= rt REP MOV + 0x7, 0, edx, 5, uintr , CPU supp= orts user interrupts + 0x7, 0, edx, 8, avx512_vp2intersect , VP2INTER= SECT{D,Q} instructions + 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mi= tigation MSR available + 0x7, 0, edx, 10, md_clear , VERW MD_= CLEAR microcode support + 0x7, 0, edx, 11, rtm_always_abort , XBEGIN (= RTM transaction) always aborts + 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_= FORCE_ABORT, RTM_ABORT bit, supported + 0x7, 0, edx, 14, serialize , SERIALIZ= E instruction + 0x7, 0, edx, 15, hybrid_cpu , The CPU = is identified as a 'hybrid part' + 0x7, 0, edx, 16, tsxldtrk , TSX susp= end/resume load address tracking + 0x7, 0, edx, 18, pconfig , PCONFIG = instruction + 0x7, 0, edx, 19, arch_lbr , Intel ar= chitectural LBRs + 0x7, 0, edx, 20, ibt , CET indi= rect branch tracking + 0x7, 0, edx, 22, amx_bf16 , AMX-BF16= : tile bfloat16 support + 0x7, 0, edx, 23, avx512_fp16 , AVX-512 = FP16 instructions + 0x7, 0, edx, 24, amx_tile , AMX-TILE= : tile architecture support + 0x7, 0, edx, 25, amx_int8 , AMX-INT8= : tile 8-bit integer support + 0x7, 0, edx, 26, spec_ctrl , Speculat= ion Control (IBRS/IBPB: indirect branch restrictions) + 0x7, 0, edx, 27, intel_stibp , Single t= hread indirect branch predictors + 0x7, 0, edx, 28, flush_l1d , FLUSH L1= D cache: IA32_FLUSH_CMD MSR + 0x7, 0, edx, 29, arch_capabilities , Intel IA= 32_ARCH_CAPABILITIES MSR + 0x7, 0, edx, 30, core_capabilities , IA32_COR= E_CAPABILITIES MSR + 0x7, 0, edx, 31, spec_ctrl_ssbd , Speculat= ive store bypass disable + 0x7, 1, eax, 4, avx_vnni , AVX-VNNI= instructions + 0x7, 1, eax, 5, avx512_bf16 , AVX-512 = bFloat16 instructions + 0x7, 1, eax, 6, lass , Linear a= ddress space separation + 0x7, 1, eax, 7, cmpccxadd , CMPccXAD= D instructions + 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: CPUID leaf 0x23 is supported + 0x7, 1, eax, 10, fzrm , Fast zer= o-length REP MOVSB + 0x7, 1, eax, 11, fsrs , Fast sho= rt REP STOSB + 0x7, 1, eax, 12, fsrc , Fast Sho= rt REP CMPSB/SCASB + 0x7, 1, eax, 17, fred , FRED: Fl= exible return and event delivery transitions + 0x7, 1, eax, 18, lkgs , LKGS: Lo= ad 'kernel' (userspace) GS + 0x7, 1, eax, 19, wrmsrns , WRMSRNS = instr (WRMSR-non-serializing) + 0x7, 1, eax, 20, nmi_src , NMI-sour= ce reporting with FRED event data + 0x7, 1, eax, 21, amx_fp16 , AMX-FP16= : FP16 tile operations + 0x7, 1, eax, 22, hreset , History = reset support + 0x7, 1, eax, 23, avx_ifma , Integer = fused multiply add + 0x7, 1, eax, 26, lam , Linear a= ddress masking + 0x7, 1, eax, 27, rd_wr_msrlist , RDMSRLIS= T/WRMSRLIST instructions + 0x7, 1, ebx, 0, intel_ppin , Protecte= d processor inventory number (PPIN{,_CTL} MSRs) + 0x7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI= -INT8 instructions + 0x7, 1, edx, 5, avx_ne_convert , AVX-NE-C= ONVERT instructions + 0x7, 1, edx, 8, amx_complex , AMX-COMP= LEX instructions (starting from Granite Rapids) + 0x7, 1, edx, 14, prefetchit_0_1 , PREFETCH= IT0/1 instructions + 0x7, 1, edx, 18, cet_sss , CET supe= rvisor shadow stacks safe to use + 0x7, 2, edx, 0, intel_psfd , Intel pr= edictive store forward disable + 0x7, 2, edx, 1, ipred_ctrl , MSR bits= IA32_SPEC_CTRL.IPRED_DIS_{U,S} + 0x7, 2, edx, 2, rrsba_ctrl , MSR bits= IA32_SPEC_CTRL.RRSBA_DIS_{U,S} + 0x7, 2, edx, 3, ddp_ctrl , MSR bit = IA32_SPEC_CTRL.DDPD_U + 0x7, 2, edx, 4, bhi_ctrl , MSR bit = IA32_SPEC_CTRL.BHI_DIS_S + 0x7, 2, edx, 5, mcdt_no , MCDT mit= igation not needed + 0x7, 2, edx, 6, uclock_disable , UC-lock = disable is supported =20 # Leaf 9H # Intel DCA (Direct Cache Access) enumeration =20 - 9, 0, eax, 0, dca_enabled_in_bios , DCA is e= nabled in BIOS + 0x9, 0, eax, 0, dca_enabled_in_bios , DCA is e= nabled in BIOS =20 # Leaf AH # Intel PMU (Performance Monitoring Unit) enumeration @@ -623,7 +632,7 @@ 0x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervis= or ID string bytes 8 - 11 =20 # Leaf 80000000H -# Maximum extended leaf number + CPU vendor string (AMD) +# Maximum extended leaf number + AMD/Transmeta CPU vendor string =20 0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum = extended cpuid leaf supported 0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor I= D string bytes 0 - 3 @@ -636,6 +645,7 @@ 0x80000001, 0, eax, 3:0, e_stepping_id , Stepping= ID 0x80000001, 0, eax, 7:4, e_base_model , Base pro= cessor model 0x80000001, 0, eax, 11:8, e_base_family , Base pro= cessor family +0x80000001, 0, eax, 13:12, e_base_type , Base pro= cessor type (Transmeta) 0x80000001, 0, eax, 19:16, e_ext_model , Extended= processor model 0x80000001, 0, eax, 27:20, e_ext_family , Extended= processor family 0x80000001, 0, ebx, 15:0, brand_id , Brand ID @@ -687,6 +697,7 @@ 0x80000001, 0, edx, 19, mp , Out-of-s= pec AMD Multiprocessing bit 0x80000001, 0, edx, 20, nx , No-execu= te page protection 0x80000001, 0, edx, 22, mmxext , AMD MMX = extensions +0x80000001, 0, edx, 23, e_mmx , MMX inst= ructions (Transmeta) 0x80000001, 0, edx, 24, e_fxsr , FXSAVE a= nd FXRSTOR instructions 0x80000001, 0, edx, 25, fxsr_opt , FXSAVE a= nd FXRSTOR optimizations 0x80000001, 0, edx, 26, pdpe1gb , 1-GB lar= ge page support @@ -720,7 +731,7 @@ 0x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU bran= d ID string, bytes 44 - 47 =20 # Leaf 80000005H -# AMD L1 cache and L1 TLB enumeration +# AMD/Transmeta L1 cache and L1 TLB enumeration =20 0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB = #entires, 2M and 4M pages 0x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB = associativity, 2M and 4M pages @@ -1051,3 +1062,108 @@ 0x80000026, 3:0, ecx, 7:0, domain_level , This dom= ain level (subleaf ID) 0x80000026, 3:0, ecx, 15:8, domain_type , This dom= ain type 0x80000026, 3:0, edx, 31:0, x2apic_id , x2APIC I= D of current logical CPU + +# Leaf 80860000H +# Maximum Transmeta leaf number + CPU vendor ID string + +0x80860000, 0, eax, 31:0, max_tra_leaf , Maximum = supported Transmeta leaf number +0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmet= a Vendor ID string bytes 0 - 3 +0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmet= a Vendor ID string bytes 8 - 11 +0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmet= a Vendor ID string bytes 4 - 7 + +# Leaf 80860001H +# Transmeta extended CPU information + +0x80860001, 0, eax, 3:0, stepping , Stepping= ID +0x80860001, 0, eax, 7:4, base_model , Base CPU= model ID +0x80860001, 0, eax, 11:8, base_family_id , Base CPU= family ID +0x80860001, 0, eax, 13:12, cpu_type , CPU type +0x80860001, 0, ebx, 7:0, cpu_rev_mask_minor , CPU revi= sion ID, mask minor +0x80860001, 0, ebx, 15:8, cpu_rev_mask_major , CPU revi= sion ID, mask major +0x80860001, 0, ebx, 23:16, cpu_rev_minor , CPU revi= sion ID, minor +0x80860001, 0, ebx, 31:24, cpu_rev_major , CPU revi= sion ID, major +0x80860001, 0, ecx, 31:0, cpu_base_mhz , CPU nomi= nal frequency, in MHz +0x80860001, 0, edx, 0, recovery , Recovery= CMS is active (after bad flush) +0x80860001, 0, edx, 1, longrun , LongRun = power management capabilities +0x80860001, 0, edx, 3, lrti , LongRun = Table Interface + +# Leaf 80860002H +# Transmeta Code Morphing Software (CMS) enumeration + +0x80860002, 0, eax, 31:0, cpu_rev_id , CPU revi= sion ID +0x80860002, 0, ebx, 7:0, cms_rev_mask_2 , CMS revi= sion ID, mask component 2 +0x80860002, 0, ebx, 15:8, cms_rev_mask_1 , CMS revi= sion ID, mask component 1 +0x80860002, 0, ebx, 23:16, cms_rev_minor , CMS revi= sion ID, minor +0x80860002, 0, ebx, 31:24, cms_rev_major , CMS revi= sion ID, major +0x80860002, 0, ecx, 31:0, cms_rev_mask_3 , CMS revi= sion ID, mask component 3 + +# Leaf 80860003H +# Transmeta CPU information string, bytes 0 - 15 + +0x80860003, 0, eax, 31:0, cpu_info_0 , CPU info= string bytes 0 - 3 +0x80860003, 0, ebx, 31:0, cpu_info_1 , CPU info= string bytes 4 - 7 +0x80860003, 0, ecx, 31:0, cpu_info_2 , CPU info= string bytes 8 - 11 +0x80860003, 0, edx, 31:0, cpu_info_3 , CPU info= string bytes 12 - 15 + +# Leaf 80860004H +# Transmeta CPU information string, bytes 16 - 31 + +0x80860004, 0, eax, 31:0, cpu_info_4 , CPU info= string bytes 16 - 19 +0x80860004, 0, ebx, 31:0, cpu_info_5 , CPU info= string bytes 20 - 23 +0x80860004, 0, ecx, 31:0, cpu_info_6 , CPU info= string bytes 24 - 27 +0x80860004, 0, edx, 31:0, cpu_info_7 , CPU info= string bytes 28 - 31 + +# Leaf 80860005H +# Transmeta CPU information string, bytes 32 - 47 + +0x80860005, 0, eax, 31:0, cpu_info_8 , CPU info= string bytes 32 - 35 +0x80860005, 0, ebx, 31:0, cpu_info_9 , CPU info= string bytes 36 - 39 +0x80860005, 0, ecx, 31:0, cpu_info_10 , CPU info= string bytes 40 - 43 +0x80860005, 0, edx, 31:0, cpu_info_11 , CPU info= string bytes 44 - 47 + +# Leaf 80860006H +# Transmeta CPU information string, bytes 48 - 63 + +0x80860006, 0, eax, 31:0, cpu_info_12 , CPU info= string bytes 48 - 51 +0x80860006, 0, ebx, 31:0, cpu_info_13 , CPU info= string bytes 52 - 55 +0x80860006, 0, ecx, 31:0, cpu_info_14 , CPU info= string bytes 56 - 59 +0x80860006, 0, edx, 31:0, cpu_info_15 , CPU info= string bytes 60 - 63 + +# Leaf 80860007H +# Transmeta live CPU information + +0x80860007, 0, eax, 31:0, cpu_cur_mhz , Current = CPU frequency, in MHz +0x80860007, 0, ebx, 31:0, cpu_cur_voltage , Current = CPU voltage, in millivolts +0x80860007, 0, ecx, 31:0, cpu_cur_perf_pctg , Current = CPU performance percentage, 0 - 100d +0x80860007, 0, edx, 31:0, cpu_cur_gate_delay , Current = CPU gate delay, in femtoseconds + +# Leaf C0000000H +# Maximum Centaur/Zhaoxin leaf number + +0xc0000000, 0, eax, 31:0, max_cntr_leaf , Maximum = Centaur/Zhaoxin leaf number + +# Leaf C0000001H +# Centaur/Zhaoxin extended CPU features + +0xc0000001, 0, edx, 0, ccs_sm2 , CCS SM2 = instructions +0xc0000001, 0, edx, 1, ccs_sm2_en , CCS SM2 = enabled +0xc0000001, 0, edx, 2, xstore , Random N= umber Generator +0xc0000001, 0, edx, 3, xstore_en , RNG enab= led +0xc0000001, 0, edx, 4, ccs_sm3_sm4 , CCS SM3 = and SM4 instructions +0xc0000001, 0, edx, 5, ccs_sm3_sm4_en , CCS SM3/= SM4 enabled +0xc0000001, 0, edx, 6, ace , Advanced= Cryptography Engine +0xc0000001, 0, edx, 7, ace_en , ACE enab= led +0xc0000001, 0, edx, 8, ace2 , Advanced= Cryptography Engine v2 +0xc0000001, 0, edx, 9, ace2_en , ACE v2 e= nabled +0xc0000001, 0, edx, 10, phe , PadLock = Hash Engine +0xc0000001, 0, edx, 11, phe_en , PHE enab= led +0xc0000001, 0, edx, 12, pmm , PadLock = Montgomery Multiplier +0xc0000001, 0, edx, 13, pmm_en , PMM enab= led +0xc0000001, 0, edx, 16, parallax , Parallax= auto adjust processor voltage +0xc0000001, 0, edx, 17, parallax_en , Parallax= enabled +0xc0000001, 0, edx, 20, tm3 , Thermal = Monitor v3 +0xc0000001, 0, edx, 21, tm3_en , TM v3 en= abled +0xc0000001, 0, edx, 25, phe2 , PadLock = Hash Engine v2 (SHA384/SHA512) +0xc0000001, 0, edx, 26, phe2_en , PHE v2 e= nabled +0xc0000001, 0, edx, 27, rsa , RSA inst= ructions (XMODEXP/MONTMUL2) +0xc0000001, 0, edx, 28, rsa_en , RSA inst= ructions enabled --=20 2.46.2 From nobody Sat Feb 7 08:06:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C7941CC8B0 for ; Thu, 28 Nov 2024 22:31:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; 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Peter Anvin" Cc: Thomas Gleixner , John Ogness , linux-kernel@vger.kernel.org, x86@kernel.org, x86-cpuid@lists.linux.dev, "Ahmed S. Darwish" Subject: [PATCH v1 13/13] MAINTAINERS: Include kcpuid under X86 CPUID entry Date: Thu, 28 Nov 2024 23:29:48 +0100 Message-ID: <20241128222948.579920-14-darwi@linutronix.de> In-Reply-To: <20241128222948.579920-1-darwi@linutronix.de> References: <20241128222948.579920-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The kcpuid tool ships a cpuid bitfields CSV file which is covered by the "X86 CPUID DATABASE" maintainers entry. Recent patches have shown that changes to this CSV may require updates to the kcpuid code. Include the entire kcpuid tool under the same maintainers entry. This will also ensure that myself and the x86-cpuid mailing list are CCed on any future kcpuid patches. Signed-off-by: Ahmed S. Darwish --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index b878ddc99f94..3b95d6fe8e3b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25093,7 +25093,7 @@ R: Ahmed S. Darwish L: x86-cpuid@lists.linux.dev S: Maintained W: https://x86-cpuid.org -F: tools/arch/x86/kcpuid/cpuid.csv +F: tools/arch/x86/kcpuid/ =20 X86 ENTRY CODE M: Andy Lutomirski --=20 2.46.2