From nobody Sat Feb 7 13:41:13 2026 Received: from smtp-fw-6002.amazon.com (smtp-fw-6002.amazon.com [52.95.49.90]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C709145323 for ; Thu, 28 Nov 2024 20:10:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=52.95.49.90 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732824636; cv=none; b=qzB259oeW4t6Sg8kvlPNxFv4imfYC1crLL4DBisM64g7X2XXt7C7E3ZmgE5aYOHOlQRCmCqsTcRQN/X5DzEqx0VZDYT1Q0nlgadx44guhCI7dRL5maItiVNJGdQVEMAQl+3Q9cq5FSJHnxeMDfptL7twTxyCLJVv6Jgcn1lwUO0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732824636; c=relaxed/simple; bh=5KiG7zzYxYkrromkp9tKIw2W1gcyJFCJQG6c3Bcn4Y0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ledIldsMCj++Fa86k6qRskHR8N9mijFqkWkwOeSNaYgBzmtP+NZ+wqO6Td0kn1lp8NbAKtHF/yJ4tFNL31FPmpK9ATTxgvyFbr6asRBf3MJFtNVexoB+NREh2fByBvbkWtV0Bg5DjyQk2PDpLfOWfXrl/Z2Ps+0+1ce2ZmEqpY4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.com; spf=pass smtp.mailfrom=amazon.com; dkim=pass (1024-bit key) header.d=amazon.com header.i=@amazon.com header.b=AKhLWFHd; arc=none smtp.client-ip=52.95.49.90 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amazon.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amazon.com header.i=@amazon.com header.b="AKhLWFHd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1732824635; x=1764360635; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l86XJw2zl5RMCsAJYGRzrxx2y2yPBRK+02pPUOrN8FA=; b=AKhLWFHd9zp9x6teXuPyZNyMnlif1agOoJDjWozGUv32bXemu0LBojzJ 8xN2xBFgaCeJDHBCu+NJu46JSp+GDwRjljvXaAeh1Snsd2XFcN982ftvK kP1/e/tvAwaGeAjunJLVSzCpWs35KeTyVqgVPXpZh/NqMeDo76jsTYOwU 8=; X-IronPort-AV: E=Sophos;i="6.12,193,1728950400"; d="scan'208";a="452016254" Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.124.125.6]) by smtp-border-fw-6002.iad6.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2024 20:10:30 +0000 Received: from EX19MTAUWA001.ant.amazon.com [10.0.7.35:54823] by smtpin.naws.us-west-2.prod.farcaster.email.amazon.dev [10.0.22.41:2525] with esmtp (Farcaster) id 7d845fb6-a2a4-4ba0-b994-ec63e5a88ad3; Thu, 28 Nov 2024 20:10:29 +0000 (UTC) X-Farcaster-Flow-ID: 7d845fb6-a2a4-4ba0-b994-ec63e5a88ad3 Received: from EX19D013UWA001.ant.amazon.com (10.13.138.253) by EX19MTAUWA001.ant.amazon.com (10.250.64.204) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1258.34; Thu, 28 Nov 2024 20:10:28 +0000 Received: from EX19MTAUWC001.ant.amazon.com (10.250.64.145) by EX19D013UWA001.ant.amazon.com (10.13.138.253) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1258.34; Thu, 28 Nov 2024 20:10:28 +0000 Received: from email-imr-corp-prod-iad-all-1a-6ea42a62.us-east-1.amazon.com (10.25.36.210) by mail-relay.amazon.com (10.250.64.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1258.34 via Frontend Transport; Thu, 28 Nov 2024 20:10:28 +0000 Received: from dev-dsk-farbere-1a-46ecabed.eu-west-1.amazon.com (dev-dsk-farbere-1a-46ecabed.eu-west-1.amazon.com [172.19.116.181]) by email-imr-corp-prod-iad-all-1a-6ea42a62.us-east-1.amazon.com (Postfix) with ESMTP id 82B3F40490; Thu, 28 Nov 2024 20:10:27 +0000 (UTC) Received: by dev-dsk-farbere-1a-46ecabed.eu-west-1.amazon.com (Postfix, from userid 14301484) id 421392481; Thu, 28 Nov 2024 20:10:27 +0000 (UTC) From: Eliav Farber To: , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v3 1/2] kexec: Consolidate machine_kexec_mask_interrupts() implementation Date: Thu, 28 Nov 2024 20:10:26 +0000 Message-ID: <20241128201027.10396-2-farbere@amazon.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20241128201027.10396-1-farbere@amazon.com> References: <20241128201027.10396-1-farbere@amazon.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the machine_kexec_mask_interrupts function to a common location in kernel/kexec_core.c, removing duplicate implementations from architecture specific files (arch/arm, arch/arm64, arch/powerpc, and arch/riscv). This consolidation reduces code duplication and improves maintainability. The unified function includes an architecture-specific behavior for CONFIG_ARM64 by conditionally clearing the active interrupt state before handling other interrupt masking operations. Signed-off-by: Eliav Farber --- V2 -> V3: This patch is new and didn't exist in V2. arch/arm/kernel/machine_kexec.c | 23 ---------------------- arch/arm64/kernel/machine_kexec.c | 31 ------------------------------ arch/powerpc/include/asm/kexec.h | 1 - arch/powerpc/kexec/core.c | 22 --------------------- arch/riscv/kernel/machine_kexec.c | 23 ---------------------- include/linux/kexec.h | 2 ++ kernel/kexec_core.c | 32 +++++++++++++++++++++++++++++++ 7 files changed, 34 insertions(+), 100 deletions(-) diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexe= c.c index 80ceb5bd2680..dd430477e7c1 100644 --- a/arch/arm/kernel/machine_kexec.c +++ b/arch/arm/kernel/machine_kexec.c @@ -127,29 +127,6 @@ void crash_smp_send_stop(void) cpus_stopped =3D 1; } =20 -static void machine_kexec_mask_interrupts(void) -{ - unsigned int i; - struct irq_desc *desc; - - for_each_irq_desc(i, desc) { - struct irq_chip *chip; - - chip =3D irq_desc_get_chip(desc); - if (!chip) - continue; - - if (chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data)) - chip->irq_eoi(&desc->irq_data); - - if (chip->irq_mask) - chip->irq_mask(&desc->irq_data); - - if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data)) - chip->irq_disable(&desc->irq_data); - } -} - void machine_crash_shutdown(struct pt_regs *regs) { local_irq_disable(); diff --git a/arch/arm64/kernel/machine_kexec.c b/arch/arm64/kernel/machine_= kexec.c index 82e2203d86a3..6f121a0164a4 100644 --- a/arch/arm64/kernel/machine_kexec.c +++ b/arch/arm64/kernel/machine_kexec.c @@ -207,37 +207,6 @@ void machine_kexec(struct kimage *kimage) BUG(); /* Should never get here. */ } =20 -static void machine_kexec_mask_interrupts(void) -{ - unsigned int i; - struct irq_desc *desc; - - for_each_irq_desc(i, desc) { - struct irq_chip *chip; - int ret; - - chip =3D irq_desc_get_chip(desc); - if (!chip) - continue; - - /* - * First try to remove the active state. If this - * fails, try to EOI the interrupt. - */ - ret =3D irq_set_irqchip_state(i, IRQCHIP_STATE_ACTIVE, false); - - if (ret && irqd_irq_inprogress(&desc->irq_data) && - chip->irq_eoi) - chip->irq_eoi(&desc->irq_data); - - if (chip->irq_mask) - chip->irq_mask(&desc->irq_data); - - if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data)) - chip->irq_disable(&desc->irq_data); - } -} - /** * machine_crash_shutdown - shutdown non-crashing cpus and save registers */ diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/ke= xec.h index 270ee93a0f7d..601e569303e1 100644 --- a/arch/powerpc/include/asm/kexec.h +++ b/arch/powerpc/include/asm/kexec.h @@ -61,7 +61,6 @@ struct pt_regs; extern void kexec_smp_wait(void); /* get and clear naca physid, wait for master to copy new code to 0 */ extern void default_machine_kexec(struct kimage *image); -extern void machine_kexec_mask_interrupts(void); =20 void relocate_new_kernel(unsigned long indirection_page, unsigned long reb= oot_code_buffer, unsigned long start_address) __noreturn; diff --git a/arch/powerpc/kexec/core.c b/arch/powerpc/kexec/core.c index b8333a49ea5d..58a930a47422 100644 --- a/arch/powerpc/kexec/core.c +++ b/arch/powerpc/kexec/core.c @@ -22,28 +22,6 @@ #include #include =20 -void machine_kexec_mask_interrupts(void) { - unsigned int i; - struct irq_desc *desc; - - for_each_irq_desc(i, desc) { - struct irq_chip *chip; - - chip =3D irq_desc_get_chip(desc); - if (!chip) - continue; - - if (chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data)) - chip->irq_eoi(&desc->irq_data); - - if (chip->irq_mask) - chip->irq_mask(&desc->irq_data); - - if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data)) - chip->irq_disable(&desc->irq_data); - } -} - #ifdef CONFIG_CRASH_DUMP void machine_crash_shutdown(struct pt_regs *regs) { diff --git a/arch/riscv/kernel/machine_kexec.c b/arch/riscv/kernel/machine_= kexec.c index 3c830a6f7ef4..2306ce3e5f22 100644 --- a/arch/riscv/kernel/machine_kexec.c +++ b/arch/riscv/kernel/machine_kexec.c @@ -114,29 +114,6 @@ void machine_shutdown(void) #endif } =20 -static void machine_kexec_mask_interrupts(void) -{ - unsigned int i; - struct irq_desc *desc; - - for_each_irq_desc(i, desc) { - struct irq_chip *chip; - - chip =3D irq_desc_get_chip(desc); - if (!chip) - continue; - - if (chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data)) - chip->irq_eoi(&desc->irq_data); - - if (chip->irq_mask) - chip->irq_mask(&desc->irq_data); - - if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data)) - chip->irq_disable(&desc->irq_data); - } -} - /* * machine_crash_shutdown - Prepare to kexec after a kernel crash * diff --git a/include/linux/kexec.h b/include/linux/kexec.h index f0e9f8eda7a3..9dac0524c0be 100644 --- a/include/linux/kexec.h +++ b/include/linux/kexec.h @@ -375,6 +375,8 @@ extern void machine_kexec(struct kimage *image); extern int machine_kexec_prepare(struct kimage *image); extern void machine_kexec_cleanup(struct kimage *image); extern int kernel_kexec(void); +extern void machine_kexec_mask_interrupts(void); + extern struct page *kimage_alloc_control_pages(struct kimage *image, unsigned int order); =20 diff --git a/kernel/kexec_core.c b/kernel/kexec_core.c index c0caa14880c3..6e1e420946e0 100644 --- a/kernel/kexec_core.c +++ b/kernel/kexec_core.c @@ -1072,3 +1072,35 @@ int kernel_kexec(void) kexec_unlock(); return error; } + +void machine_kexec_mask_interrupts(void) +{ + unsigned int i; + struct irq_desc *desc; + + for_each_irq_desc(i, desc) { + struct irq_chip *chip; + int check_eoi =3D 1; + + chip =3D irq_desc_get_chip(desc); + if (!chip) + continue; + + if (IS_ENABLED(CONFIG_ARM64)) { + /* + * First try to remove the active state. If this fails, try to EOI the + * interrupt. + */ + check_eoi =3D irq_set_irqchip_state(i, IRQCHIP_STATE_ACTIVE, false); + } + + if (check_eoi && chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data)) + chip->irq_eoi(&desc->irq_data); + + if (chip->irq_mask) + chip->irq_mask(&desc->irq_data); + + if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data)) + chip->irq_disable(&desc->irq_data); + } +} --=20 2.40.1 From nobody Sat Feb 7 13:41:13 2026 Received: from smtp-fw-33001.amazon.com (smtp-fw-33001.amazon.com [207.171.190.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A096E1C1F37 for ; Thu, 28 Nov 2024 20:10:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=207.171.190.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732824643; cv=none; b=U3GXTsNqDtQxLNkd9orHLb5Ae8L9M706ba6JV+NO1vhKVfUvvs4uJbJjlZDhgUkWxJ64VVV2CQj7AgvGBmbYexIPOH18OloD1+tFLyO96DzFwd9SRXYMFKz4Vkc9/ZZojTc+HLnWFfKkcC3OzzU4fi+sggTNFBu18NBYec4fzKY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732824643; c=relaxed/simple; bh=wd7sHuGqD71XU3EqKfVudmyiNj/L85zfthfw5eOF9hI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VxOl7a9qH+LcFRNFW4q2+b07v63pCFVPlmI9FcpdJt7l988mbh0drPdZ8hqTtOhTM9mRqWkpeUuAsmNnMjFkc6nl34h99Ih8x4H3Sv4VA1/qOxHtc3dlMvZBMxZjlCnvGbxRrViykA8KsWh228mx2RjgRTiSJjoK7KAAXP7DMcY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.com; spf=pass smtp.mailfrom=amazon.com; dkim=pass (1024-bit key) header.d=amazon.com header.i=@amazon.com header.b=kj3tTnG+; arc=none smtp.client-ip=207.171.190.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amazon.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amazon.com header.i=@amazon.com header.b="kj3tTnG+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1732824641; x=1764360641; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pAFdRwFKfNDF1JqGR+n1qcumP19pBTl1wsynLPrMwbI=; b=kj3tTnG+Boa2ahx9ob+204des1kHZtbiUMj6BT70e0SNpUCZkj/xsFWw 1NDdxIXPVofNCYhn3GG7T33YILUEz8pFnxJjwZFwO3ijKyqTco6FTTUle iVcWfSGORj1whGpoLPUfXmTbNntKgw5JlFYqWKPf8npe4ir+2oTqjarXc 8=; X-IronPort-AV: E=Sophos;i="6.12,193,1728950400"; d="scan'208";a="389147585" Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.25.36.210]) by smtp-border-fw-33001.sea14.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2024 20:10:33 +0000 Received: from EX19MTAEUB001.ant.amazon.com [10.0.17.79:6662] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.32.206:2525] with esmtp (Farcaster) id 535754cd-d852-4ac9-99b0-bacfdd30cbc2; Thu, 28 Nov 2024 20:10:32 +0000 (UTC) X-Farcaster-Flow-ID: 535754cd-d852-4ac9-99b0-bacfdd30cbc2 Received: from EX19D018EUC003.ant.amazon.com (10.252.51.231) by EX19MTAEUB001.ant.amazon.com (10.252.51.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1258.34; Thu, 28 Nov 2024 20:10:29 +0000 Received: from EX19MTAUEC001.ant.amazon.com (10.252.135.222) by EX19D018EUC003.ant.amazon.com (10.252.51.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1258.34; Thu, 28 Nov 2024 20:10:28 +0000 Received: from email-imr-corp-prod-pdx-all-2b-22fa938e.us-west-2.amazon.com (10.124.125.6) by mail-relay.amazon.com (10.252.135.200) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1258.34 via Frontend Transport; Thu, 28 Nov 2024 20:10:28 +0000 Received: from dev-dsk-farbere-1a-46ecabed.eu-west-1.amazon.com (dev-dsk-farbere-1a-46ecabed.eu-west-1.amazon.com [172.19.116.181]) by email-imr-corp-prod-pdx-all-2b-22fa938e.us-west-2.amazon.com (Postfix) with ESMTP id ADDF8C01D2; Thu, 28 Nov 2024 20:10:27 +0000 (UTC) Received: by dev-dsk-farbere-1a-46ecabed.eu-west-1.amazon.com (Postfix, from userid 14301484) id 46D0F78EA; Thu, 28 Nov 2024 20:10:27 +0000 (UTC) From: Eliav Farber To: , , , , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v3 2/2] kexec: Prevent redundant IRQ masking by checking state before shutdown Date: Thu, 28 Nov 2024 20:10:27 +0000 Message-ID: <20241128201027.10396-3-farbere@amazon.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20241128201027.10396-1-farbere@amazon.com> References: <20241128201027.10396-1-farbere@amazon.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" During machine kexec, the function machine_kexec_mask_interrupts() is responsible for disabling or masking all interrupts. While the irq_disable hook ensures that an already-disabled IRQ is not disabled again, the current implementation unconditionally invokes the irq_mask() function for every interrupt descriptor, even when the interrupt is already masked. A specific issue was observed in the crash kernel flow after unbinding a device (prior to kexec) that used a GPIO as an IRQ source. The warning was triggered by the gpiochip_disable_irq() function, which attempted to clear the FLAG_IRQ_IS_ENABLED flag when FLAG_USED_AS_IRQ was not set: ``` void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset) { struct gpio_desc *desc =3D gpiochip_get_desc(gc, offset); if (!IS_ERR(desc) && !WARN_ON(!test_bit(FLAG_USED_AS_IRQ, &desc->flags))) clear_bit(FLAG_IRQ_IS_ENABLED, &desc->flags); } ``` This issue surfaced after commit a8173820f441 ("gpio: gpiolib: Allow GPIO IRQs to lazy disable") introduced lazy disablement for GPIO IRQs. It replaced disable/enable hooks with mask/unmask hooks. Unlike the disable hook, the mask hook doesn't handle already-masked IRQs. When a GPIO-IRQ driver is unbound, the IRQ is released, triggering __irq_disable() and irq_state_set_masked(). A subsequent call to machine_kexec_mask_interrupts() re-invokes chip->irq_mask(). This results in a call chain, including gpiochip_irq_mask() and gpiochip_disable_irq(). Since FLAG_USED_AS_IRQ was cleared earlier, a warning occurs. This patch addresses the issue by: - Replacing the calls to irq_mask() and irq_disable() hooks with a simplified call to irq_shutdown(). - Checking if the interrupt is started (irqd_is_started) before calling the shutdown. As part of this change, the irq_shutdown() declaration was moved from kernel/irq/internals.h to include/linux/irq.h to make it accessible outside the kernel/irq/ directory, as the former can only be included within that directory. Signed-off-by: Eliav Farber --- V2 -> V3: - Check if IRQ is started using irqd_is_started(). - Use irq_shutdown() instead of irq_disable(). include/linux/irq.h | 3 +++ kernel/irq/internals.h | 1 - kernel/kexec_core.c | 8 ++------ 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/include/linux/irq.h b/include/linux/irq.h index fa711f80957b..48a3df728c47 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -694,6 +694,9 @@ extern int irq_chip_request_resources_parent(struct irq= _data *data); extern void irq_chip_release_resources_parent(struct irq_data *data); #endif =20 +/* Shut down the interrupt */ +extern void irq_shutdown(struct irq_desc *desc); + /* Handling of unhandled and spurious interrupts: */ extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); =20 diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index fe0272cd84a5..1f9287b1ccb7 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -88,7 +88,6 @@ extern int irq_activate(struct irq_desc *desc); extern int irq_activate_and_startup(struct irq_desc *desc, bool resend); extern int irq_startup(struct irq_desc *desc, bool resend, bool force); =20 -extern void irq_shutdown(struct irq_desc *desc); extern void irq_shutdown_and_deactivate(struct irq_desc *desc); extern void irq_enable(struct irq_desc *desc); extern void irq_disable(struct irq_desc *desc); diff --git a/kernel/kexec_core.c b/kernel/kexec_core.c index 6e1e420946e0..928b4387502b 100644 --- a/kernel/kexec_core.c +++ b/kernel/kexec_core.c @@ -1083,7 +1083,7 @@ void machine_kexec_mask_interrupts(void) int check_eoi =3D 1; =20 chip =3D irq_desc_get_chip(desc); - if (!chip) + if (!chip || !irqd_is_started(&desc->irq_data)) continue; =20 if (IS_ENABLED(CONFIG_ARM64)) { @@ -1097,10 +1097,6 @@ void machine_kexec_mask_interrupts(void) if (check_eoi && chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data)) chip->irq_eoi(&desc->irq_data); =20 - if (chip->irq_mask) - chip->irq_mask(&desc->irq_data); - - if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data)) - chip->irq_disable(&desc->irq_data); + irq_shutdown(desc); } } --=20 2.40.1