From nobody Fri Nov 29 13:22:29 2024 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47F801B85F8 for ; Thu, 28 Nov 2024 15:16:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732807014; cv=none; b=sWJVSTYJhuI5HGZFjO8VydCoHL8FlVvdQAYfD4Sni83PBHzBwKKcs9Js7K3/1ku+QPmj3gU6IHZZfqN9u3zlL6cK+vb3J/bj5pTmggvm5cYRIaCPTsgVuaUtGTKVSdzQ+T7ogsh8UPteY1zN09QUCQkNpcbGdN7S1sVEVY/YEQQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732807014; c=relaxed/simple; bh=9Cp4EaFYwrm1DNXgnlUgE7sxl1OSRdzWSsgnFAohqcw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kdIkBVXt/oMJ8oE0Qg2n/lk+XkFdlBw4P9ndSh9pI3YTk4XPjGdFBHsN3CpxyvCyiDe7LFksPf1PUs1iXI8zFLwS7uEfbKyawECwtFsfU4hErbUXJLQjg3p3pyp5UlrLWFHXViBS8Mnh1ej9HulG8h3i5TPc1w21IKVwuS7o5UE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=lqEJi1NZ; arc=none smtp.client-ip=209.85.167.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="lqEJi1NZ" Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-53de5ec22adso1083771e87.3 for ; Thu, 28 Nov 2024 07:16:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732807009; x=1733411809; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RfeSJBhQWP8l7KTP5vZE2iSz9LkwdawgxtvBfvQp1xo=; b=lqEJi1NZErudmzZ4fzsIOwAEuftS5/4rh9b1VT3XBIqd4zK/zj9YrSFynI2+XoSoya j/Ee9H0m1hdmJFvrpFVgqMz8HYtS3CCgA8XpXd26ETwaSjVGqI+ijjlj8UuzHILz4XGg g8Bta0pG7O9yiOUFsgRBxNezgYfOp869dYZUcQRtgrXM5ePd0uRAZGSf6Psd/sX1WL2k lHdb3vUmmjTOOM8DRY8gFbib8qjjro+/xcdOsKOCd1hIVNq4+oZuS0Ta171kIRBHv8bl CvscR+JYUH0sXxfRbaWQkZoukyaA6lFBd74Wq1kEGIlZcxyba9QBcLtiRowORl05FNWO PxuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732807009; x=1733411809; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RfeSJBhQWP8l7KTP5vZE2iSz9LkwdawgxtvBfvQp1xo=; b=cFvRnaEqJcZR9FKSt3UdalVyvO36x5Ra48K4bfN067Apz9vxTZ4r3qGhOf1uYC7xWE 5qjtWmUiARQIcfXj8EYTvpsbY6RVRn6iAYzpLbVHPfPIeU6Eo8fKlJ5qMcSPBdMHv+2d iEVpR+4VgdCiDdF1d8d+SxONyvdG6soboC0LIYqMHHv0InRbvY5pzxV/Kt0hH3GWuQoB LVY2X7spA7ilnJ/4cXdic+Z9Qf0oNuzMLtkb0rmaZzHXt+pQoKaQLURw1wpMO4Bfhrq0 J1DVTpMdjfCuan3a9602uR485Paug/glMMJPchS489a/mZWXZU6sfNfJqOdpMKQMJjIy bjQQ== X-Forwarded-Encrypted: i=1; AJvYcCWRckKLyNQBOc4LOlzXb6UF7h4Kz0OOCLPa8RwXyXUQRS7sDQn7gtbGsJyTj/4vr8yd/R/YOcZbUPs9M/E=@vger.kernel.org X-Gm-Message-State: AOJu0YzuvU9LOWD3CsAG0PaveZxXqAXmex4TFo7QTu2c0eqVMyzbI3rA SJQIEgujaqd/OXWvCUHZvaR7Dle7MG+Z/fptX5SNTjmcNpsLQNF1pnMnK/Q7l+5S5nUkdhIZREJ PDJI= X-Gm-Gg: ASbGncs3AjFV2jf5wEMv79bn4reU/PhurVI1vyPIscKaHx+HW1V+Xf+xayj1otKozj9 U1biSQn9V8tvW7ijASnIa2MMR8SHnZ1mc2t2xc2E3+FYdse5b3eUrAITjLz/ZHWNVtmaCQwLC6v YQFOo3rYhtxCDto96bImg1ngvpRN56Xkzyk7KbZ4rJUD31Pv2B30Pk9+rcc1OgULEw2NZjrlQ6j 8ZuJtrIE1l8cELTI8BvnX91w4rM2BI8ObQ/gnQGPY3toHi69rmkmYzQwAaQImer5wIUtcE= X-Google-Smtp-Source: AGHT+IHn/lhzJjmymdgS/6JhVUH3swS4RU7HodKmDhCdl7gS1+/+6IDbGFSb0wYctmuAw5hTQlb8vw== X-Received: by 2002:a05:6512:32c9:b0:53d:e3a6:ae82 with SMTP id 2adb3069b0e04-53df00ccf7dmr4177851e87.14.1732807009070; Thu, 28 Nov 2024 07:16:49 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434aa7e4fe1sm55867025e9.38.2024.11.28.07.16.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 07:16:48 -0800 (PST) From: Neil Armstrong Date: Thu, 28 Nov 2024 16:16:42 +0100 Subject: [PATCH v4 2/5] dt-bindings: mmc: controller: move properties common with slot out to mmc-controller-common Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241128-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v4-2-11d9f9200a59@linaro.org> References: <20241128-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v4-0-11d9f9200a59@linaro.org> In-Reply-To: <20241128-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v4-0-11d9f9200a59@linaro.org> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Maxime Ripard Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=24571; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=9Cp4EaFYwrm1DNXgnlUgE7sxl1OSRdzWSsgnFAohqcw=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnSIlbc7yqMnrqGxFvNnxzkXxqTwiFJNf7uK9DLlp/ atWTuM2JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ0iJWwAKCRB33NvayMhJ0VZ2D/ 9o6CQHuiULqr2VYsXeaOojYUEMMgeykk+S2v+vcq8ldZAGIdkv1r/VUN/pRDz/c+886U6uYcSMtYa7 MNcKs2x9F2WhsD7aB3t9Cu8vIXVljwwShf/0DAn1v+OzTMjdjkB6meA4tVWahbChihI5UzTAZQr/zV NMCsTX9ZJM8mElhV/ctlZT6g5gPzKxYvdpN3yEUvhMsSP3qvwn1s/Ds9JF+AjGYw75dBnEHiMI4YIn exdhM2yNCAC/f4tGHEjhXw+HyP5oJ0bnVdc4C117SMlu4la/fceBZxiQr4eHuZrkotHcd1N/fJFeUA gbXlw1NGYYkw3DHz+UCPE3v9vIytAWJ1xMCoz/4PZgXj3ClViWv4+KyaMZ0fTi4r/W20ovC3W47Wkb Va5gLIoWZ099siEwAh0JPIG8Sla9LKDIx9iU8VgEwwXFNTQqPmjskTMFwuN+RJHjnnmQ5FA6IjZ9PP 1B5oXeyAVd/MUtTOLC9GkrENE3I3mtrhSiFaCs07nMDKCJFsgbdEU+x6zONj8WIWlUAlc2ex+uXV4L bJk+idzIVMpyg4xGAgQeZ+l4+QmsVPJE9x0jhyJVLn/6wt37mTVHajlsMeOs2EImaZPReRpJAEHY7u p+/O/M9g3fvHPEwVwG2RA1S93s6bF9LwPcy7K9b3zRup2jCSB05B0ba8CNaA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Move the common MMC "slot" properties because they are shared by the single-slot or multi-slot controllers, and will help defining a simple mmc-slot bindings document with proper slot properties and nodename. Reviewed-by: Rob Herring (Arm) Signed-off-by: Neil Armstrong --- .../bindings/mmc/mmc-controller-common.yaml | 357 +++++++++++++++++= ++++ .../devicetree/bindings/mmc/mmc-controller.yaml | 344 +----------------= --- 2 files changed, 360 insertions(+), 341 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.ya= ml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml new file mode 100644 index 0000000000000000000000000000000000000000..d8297af578049b2bf71cf6e06f4= 5aac1e42bde56 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml @@ -0,0 +1,357 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MMC Controller & Slots Common Properties + +maintainers: + - Ulf Hansson + +description: | + These properties are common to multiple MMC host controllers and the + possible slots or ports for multi-slot controllers. + +properties: + "#address-cells": + const: 1 + description: | + The cell is the SDIO function number if a function subnode is used. + + "#size-cells": + const: 0 + + # Card Detection. + # If none of these properties are supplied, the host native card + # detect will be used. Only one of them should be provided. + + broken-cd: + $ref: /schemas/types.yaml#/definitions/flag + description: + There is no card detection available; polling must be used. + + cd-gpios: + maxItems: 1 + description: + The card detection will be done using the GPIO provided. + + non-removable: + $ref: /schemas/types.yaml#/definitions/flag + description: + Non-removable slot (like eMMC); assume always present. + + # *NOTE* on CD and WP polarity. To use common for all SD/MMC host + # controllers line polarity properties, we have to fix the meaning + # of the "normal" and "inverted" line levels. We choose to follow + # the SDHCI standard, which specifies both those lines as "active + # low." Therefore, using the "cd-inverted" property means, that the + # CD line is active high, i.e. it is high, when a card is + # inserted. Similar logic applies to the "wp-inverted" property. + # + # CD and WP lines can be implemented on the hardware in one of two + # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or + # as dedicated pins. Polarity of dedicated pins can be specified, + # using *-inverted properties. GPIO polarity can also be specified + # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the + # latter case. We choose to use the XOR logic for GPIO CD and WP + # lines. This means, the two properties are "superimposed," for + # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the + # respective *-inverted property property results in a + # double-inversion and actually means the "normal" line polarity is + # in effect. + wp-inverted: + $ref: /schemas/types.yaml#/definitions/flag + description: + The Write Protect line polarity is inverted. + + cd-inverted: + $ref: /schemas/types.yaml#/definitions/flag + description: + The CD line polarity is inverted. + + # Other properties + + bus-width: + description: + Number of data lines. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 4, 8] + default: 1 + + max-frequency: + description: | + Maximum operating frequency of the bus: + - for eMMC, the maximum supported frequency is 200MHz, + - for SD/SDIO cards the SDR104 mode has a max supported + frequency of 208MHz, + - some mmc host controllers do support a max frequency upto + 384MHz. + So, lets keep the maximum supported value here. + + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 400000 + maximum: 384000000 + + disable-wp: + $ref: /schemas/types.yaml#/definitions/flag + description: + When set, no physical write-protect line is present. This + property should only be specified when the controller has a + dedicated write-protect detection logic. If a GPIO is always used + for the write-protect detection logic, it is sufficient to not + specify the wp-gpios property in the absence of a write-protect + line. Not used in combination with eMMC or SDIO. + + wp-gpios: + maxItems: 1 + description: + GPIO to use for the write-protect detection. + + cd-debounce-delay-ms: + description: + Set delay time before detecting card after card insert + interrupt. + + no-1-8-v: + $ref: /schemas/types.yaml#/definitions/flag + description: + When specified, denotes that 1.8V card voltage is not supported + on this system, even if the controller claims it. + + cap-sd-highspeed: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD high-speed timing is supported. + + cap-mmc-highspeed: + $ref: /schemas/types.yaml#/definitions/flag + description: + MMC high-speed timing is supported. + + sd-uhs-sdr12: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS SDR12 speed is supported. + + sd-uhs-sdr25: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS SDR25 speed is supported. + + sd-uhs-sdr50: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS SDR50 speed is supported. + + sd-uhs-sdr104: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS SDR104 speed is supported. + + sd-uhs-ddr50: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS DDR50 speed is supported. + + cap-power-off-card: + $ref: /schemas/types.yaml#/definitions/flag + description: + Powering off the card is safe. + + cap-mmc-hw-reset: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC hardware reset is supported + + cap-sdio-irq: + $ref: /schemas/types.yaml#/definitions/flag + description: + enable SDIO IRQ signalling on this interface + + full-pwr-cycle: + $ref: /schemas/types.yaml#/definitions/flag + description: + Full power cycle of the card is supported. + + full-pwr-cycle-in-suspend: + $ref: /schemas/types.yaml#/definitions/flag + description: + Full power cycle of the card in suspend is supported. + + mmc-ddr-1_2v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC high-speed DDR mode (1.2V I/O) is supported. + + mmc-ddr-1_8v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC high-speed DDR mode (1.8V I/O) is supported. + + mmc-ddr-3_3v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC high-speed DDR mode (3.3V I/O) is supported. + + mmc-hs200-1_2v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS200 mode (1.2V I/O) is supported. + + mmc-hs200-1_8v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS200 mode (1.8V I/O) is supported. + + mmc-hs400-1_2v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS400 mode (1.2V I/O) is supported. + + mmc-hs400-1_8v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS400 mode (1.8V I/O) is supported. + + mmc-hs400-enhanced-strobe: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS400 enhanced strobe mode is supported + + no-mmc-hs400: + $ref: /schemas/types.yaml#/definitions/flag + description: + All eMMC HS400 modes are not supported. + + dsr: + description: + Value the card Driver Stage Register (DSR) should be programmed + with. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 0xffff + + no-sdio: + $ref: /schemas/types.yaml#/definitions/flag + description: + Controller is limited to send SDIO commands during + initialization. + + no-sd: + $ref: /schemas/types.yaml#/definitions/flag + description: + Controller is limited to send SD commands during initialization. + + no-mmc: + $ref: /schemas/types.yaml#/definitions/flag + description: + Controller is limited to send MMC commands during + initialization. + + fixed-emmc-driver-type: + description: + For non-removable eMMC, enforce this driver type. The value is + the driver type as specified in the eMMC specification (table + 206 in spec version 5.1) + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 4 + + post-power-on-delay-ms: + description: + It was invented for MMC pwrseq-simple which could be referred to + mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay + waiting for I/O signalling and card power supply to be stable, + regardless of whether pwrseq-simple is used. Default to 10ms if + no available. + default: 10 + + supports-cqe: + $ref: /schemas/types.yaml#/definitions/flag + description: + The presence of this property indicates that the corresponding + MMC host controller supports HW command queue feature. + + disable-cqe-dcmd: + $ref: /schemas/types.yaml#/definitions/flag + description: + The presence of this property indicates that the MMC + controller\'s command queue engine (CQE) does not support direct + commands (DCMDs). + + keep-power-in-suspend: + $ref: /schemas/types.yaml#/definitions/flag + description: + SDIO only. Preserves card power during a suspend/resume cycle. + + wakeup-source: + $ref: /schemas/types.yaml#/definitions/flag + description: + SDIO only. Enables wake up of host system on SDIO IRQ assertion. + + vmmc-supply: + description: + Supply for the card power + + vqmmc-supply: + description: + Supply for the bus IO line power, such as a level shifter. + If the level shifter is controlled by a GPIO line, this shall + be modeled as a "regulator-fixed" with a GPIO line for + switching the level shifter on/off. + + mmc-pwrseq: + $ref: /schemas/types.yaml#/definitions/phandle + description: + System-on-Chip designs may specify a specific MMC power + sequence. To successfully detect an (e)MMC/SD/SDIO card, that + power sequence must be maintained while initializing the card. + +patternProperties: + "^.*@[0-9]+$": + type: object + description: | + On embedded systems the cards connected to a host may need + additional properties. These can be specified in subnodes to the + host controller node. The subnodes are identified by the + standard \'reg\' property. Which information exactly can be + specified depends on the bindings for the SDIO function driver + for the subnode, as specified by the compatible string. + + properties: + compatible: + description: | + Name of SDIO function following generic names recommended + practice + + reg: + items: + - minimum: 0 + maximum: 7 + description: + Must contain the SDIO function number of the function this + subnode describes. A value of 0 denotes the memory SD + function, values from 1 to 7 denote the SDIO functions. + + required: + - reg + + "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)= |ddr50))$": + $ref: /schemas/types.yaml#/definitions/uint32-array + + minItems: 2 + maxItems: 2 + items: + minimum: 0 + maximum: 359 + description: + Set the clock (phase) delays which are to be configured in the + controller while switching to particular speed mode. These values + are in pair of degrees. + +dependencies: + cd-debounce-delay-ms: [ cd-gpios ] + fixed-emmc-driver-type: [ non-removable ] + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Do= cumentation/devicetree/bindings/mmc/mmc-controller.yaml index 23884b8184a9df2da3bda5f86916f2e0a5d502bf..99c01ce318d3e5aa914ed9b1b71= e620538eef29b 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml @@ -18,351 +18,13 @@ description: | (and the corresponding mmcblkN devices) by defining an alias in the /aliases device tree node. =20 +$ref: mmc-controller-common.yaml# + properties: $nodename: pattern: "^mmc(@.*)?$" =20 - "#address-cells": - const: 1 - description: | - The cell is the SDIO function number if a function subnode is used. - - "#size-cells": - const: 0 - - # Card Detection. - # If none of these properties are supplied, the host native card - # detect will be used. Only one of them should be provided. - - broken-cd: - $ref: /schemas/types.yaml#/definitions/flag - description: - There is no card detection available; polling must be used. - - cd-gpios: - maxItems: 1 - description: - The card detection will be done using the GPIO provided. - - non-removable: - $ref: /schemas/types.yaml#/definitions/flag - description: - Non-removable slot (like eMMC); assume always present. - - # *NOTE* on CD and WP polarity. To use common for all SD/MMC host - # controllers line polarity properties, we have to fix the meaning - # of the "normal" and "inverted" line levels. We choose to follow - # the SDHCI standard, which specifies both those lines as "active - # low." Therefore, using the "cd-inverted" property means, that the - # CD line is active high, i.e. it is high, when a card is - # inserted. Similar logic applies to the "wp-inverted" property. - # - # CD and WP lines can be implemented on the hardware in one of two - # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or - # as dedicated pins. Polarity of dedicated pins can be specified, - # using *-inverted properties. GPIO polarity can also be specified - # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the - # latter case. We choose to use the XOR logic for GPIO CD and WP - # lines. This means, the two properties are "superimposed," for - # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the - # respective *-inverted property property results in a - # double-inversion and actually means the "normal" line polarity is - # in effect. - wp-inverted: - $ref: /schemas/types.yaml#/definitions/flag - description: - The Write Protect line polarity is inverted. - - cd-inverted: - $ref: /schemas/types.yaml#/definitions/flag - description: - The CD line polarity is inverted. - - # Other properties - - bus-width: - description: - Number of data lines. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 4, 8] - default: 1 - - max-frequency: - description: | - Maximum operating frequency of the bus: - - for eMMC, the maximum supported frequency is 200MHz, - - for SD/SDIO cards the SDR104 mode has a max supported - frequency of 208MHz, - - some mmc host controllers do support a max frequency upto - 384MHz. - So, lets keep the maximum supported value here. - - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 400000 - maximum: 384000000 - - disable-wp: - $ref: /schemas/types.yaml#/definitions/flag - description: - When set, no physical write-protect line is present. This - property should only be specified when the controller has a - dedicated write-protect detection logic. If a GPIO is always used - for the write-protect detection logic, it is sufficient to not - specify the wp-gpios property in the absence of a write-protect - line. Not used in combination with eMMC or SDIO. - - wp-gpios: - maxItems: 1 - description: - GPIO to use for the write-protect detection. - - cd-debounce-delay-ms: - description: - Set delay time before detecting card after card insert - interrupt. - - no-1-8-v: - $ref: /schemas/types.yaml#/definitions/flag - description: - When specified, denotes that 1.8V card voltage is not supported - on this system, even if the controller claims it. - - cap-sd-highspeed: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD high-speed timing is supported. - - cap-mmc-highspeed: - $ref: /schemas/types.yaml#/definitions/flag - description: - MMC high-speed timing is supported. - - sd-uhs-sdr12: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS SDR12 speed is supported. - - sd-uhs-sdr25: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS SDR25 speed is supported. - - sd-uhs-sdr50: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS SDR50 speed is supported. - - sd-uhs-sdr104: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS SDR104 speed is supported. - - sd-uhs-ddr50: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS DDR50 speed is supported. - - cap-power-off-card: - $ref: /schemas/types.yaml#/definitions/flag - description: - Powering off the card is safe. - - cap-mmc-hw-reset: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC hardware reset is supported - - cap-sdio-irq: - $ref: /schemas/types.yaml#/definitions/flag - description: - enable SDIO IRQ signalling on this interface - - full-pwr-cycle: - $ref: /schemas/types.yaml#/definitions/flag - description: - Full power cycle of the card is supported. - - full-pwr-cycle-in-suspend: - $ref: /schemas/types.yaml#/definitions/flag - description: - Full power cycle of the card in suspend is supported. - - mmc-ddr-1_2v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC high-speed DDR mode (1.2V I/O) is supported. - - mmc-ddr-1_8v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC high-speed DDR mode (1.8V I/O) is supported. - - mmc-ddr-3_3v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC high-speed DDR mode (3.3V I/O) is supported. - - mmc-hs200-1_2v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS200 mode (1.2V I/O) is supported. - - mmc-hs200-1_8v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS200 mode (1.8V I/O) is supported. - - mmc-hs400-1_2v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS400 mode (1.2V I/O) is supported. - - mmc-hs400-1_8v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS400 mode (1.8V I/O) is supported. - - mmc-hs400-enhanced-strobe: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS400 enhanced strobe mode is supported - - no-mmc-hs400: - $ref: /schemas/types.yaml#/definitions/flag - description: - All eMMC HS400 modes are not supported. - - dsr: - description: - Value the card Driver Stage Register (DSR) should be programmed - with. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 0xffff - - no-sdio: - $ref: /schemas/types.yaml#/definitions/flag - description: - Controller is limited to send SDIO commands during - initialization. - - no-sd: - $ref: /schemas/types.yaml#/definitions/flag - description: - Controller is limited to send SD commands during initialization. - - no-mmc: - $ref: /schemas/types.yaml#/definitions/flag - description: - Controller is limited to send MMC commands during - initialization. - - fixed-emmc-driver-type: - description: - For non-removable eMMC, enforce this driver type. The value is - the driver type as specified in the eMMC specification (table - 206 in spec version 5.1) - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 4 - - post-power-on-delay-ms: - description: - It was invented for MMC pwrseq-simple which could be referred to - mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay - waiting for I/O signalling and card power supply to be stable, - regardless of whether pwrseq-simple is used. Default to 10ms if - no available. - default: 10 - - supports-cqe: - $ref: /schemas/types.yaml#/definitions/flag - description: - The presence of this property indicates that the corresponding - MMC host controller supports HW command queue feature. - - disable-cqe-dcmd: - $ref: /schemas/types.yaml#/definitions/flag - description: - The presence of this property indicates that the MMC - controller\'s command queue engine (CQE) does not support direct - commands (DCMDs). - - keep-power-in-suspend: - $ref: /schemas/types.yaml#/definitions/flag - description: - SDIO only. Preserves card power during a suspend/resume cycle. - - wakeup-source: - $ref: /schemas/types.yaml#/definitions/flag - description: - SDIO only. Enables wake up of host system on SDIO IRQ assertion. - - vmmc-supply: - description: - Supply for the card power - - vqmmc-supply: - description: - Supply for the bus IO line power, such as a level shifter. - If the level shifter is controlled by a GPIO line, this shall - be modeled as a "regulator-fixed" with a GPIO line for - switching the level shifter on/off. - - mmc-pwrseq: - $ref: /schemas/types.yaml#/definitions/phandle - description: - System-on-Chip designs may specify a specific MMC power - sequence. To successfully detect an (e)MMC/SD/SDIO card, that - power sequence must be maintained while initializing the card. - -patternProperties: - "^.*@[0-9]+$": - type: object - description: | - On embedded systems the cards connected to a host may need - additional properties. These can be specified in subnodes to the - host controller node. The subnodes are identified by the - standard \'reg\' property. Which information exactly can be - specified depends on the bindings for the SDIO function driver - for the subnode, as specified by the compatible string. - - properties: - compatible: - description: | - Name of SDIO function following generic names recommended - practice - - reg: - items: - - minimum: 0 - maximum: 7 - description: - Must contain the SDIO function number of the function this - subnode describes. A value of 0 denotes the memory SD - function, values from 1 to 7 denote the SDIO functions. - - required: - - reg - - "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)= |ddr50))$": - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 2 - maxItems: 2 - items: - minimum: 0 - maximum: 359 - description: - Set the clock (phase) delays which are to be configured in the - controller while switching to particular speed mode. These values - are in pair of degrees. - -dependencies: - cd-debounce-delay-ms: [ cd-gpios ] - fixed-emmc-driver-type: [ non-removable ] - -additionalProperties: true +unevaluatedProperties: true =20 examples: - | --=20 2.34.1