From nobody Mon Feb 9 14:14:08 2026 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A3BE19539F for ; Wed, 27 Nov 2024 10:02:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732701742; cv=none; b=PCtvjxGMC1MDmepfr5QOZ20QyFseDMO9aNKWkhNOAdFs/peqQUtkDLUIPMG06vTjWeGp4/dRoccTxBBNsiq0hVxGmH7JuvDPoaR8hwLtUJR5p9zsPLoGs4out1+lHUvh0VuZ5kkDqYSz4lRM2a9QmxVZEaN2shzDFmvBxEKzUiA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732701742; c=relaxed/simple; bh=t6i8BpWjvHYC+LyV191L2DoLLnAHyCYZJLzH4xlBclg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bYtPFa2xCE/gG0X8kpNdA6dlb+oA/MfMz4YQ6Oe80BDyS1MaLJhbwKU6swUKb4gBNv1GsU9yBWZS6Qao+lGNDeE4eefIm6wdPzZDemNsmSw6LalUHDh5DOFt7RuwSmaYyJv3Mjbp9TMpL85Hq2PVzHuubdysBi07n/ahPpt9F5U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=tiX0sOb+; arc=none smtp.client-ip=209.85.208.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="tiX0sOb+" Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-5ceb03aadb1so8690656a12.0 for ; Wed, 27 Nov 2024 02:02:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732701738; x=1733306538; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rUBQf8hA2fpU+kmR16EcISA5nfxhUZdSES5iWO7fp+4=; b=tiX0sOb+jXEFlFRMJ8yab/6h0JbugPFSi8HFODl8i+O1gnYL5BnxdOwxw9LM0GjG4I Bd3MO5m9C4c34CoXmbwFoUtlve6gm8WsycQ5T1J6PLD39V6OcNZdcab+kBJBbwMvL1Tw VfNGkOeX4bECbQ7Jq3qI7GbIOxVu9GUk/kss9X9MJGd+rmC7+eRl5H+nz02ZY5Uwu6sP LV4xt166f59ddHSnBeYsra18U7+8evE3my3T9z5sGwTb+t+Rtaz/TCdisdVi35jiMqos vBHkUg9FNRuTtMUVIPXMJnx9EiJ2s5b3cZwOcNUxrkR2sgSLiVAKiCRuvH1OWm+vGtR+ Odjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732701738; x=1733306538; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rUBQf8hA2fpU+kmR16EcISA5nfxhUZdSES5iWO7fp+4=; b=T/rcEfDplustIcLnTVQfvdprE+M82yxI181XPvbIr72VTDFsp110kqOcQzdjBvViXP xRJb57jSHSrxuxgikuwcFyWmAIF7oVOHh4YzTnvK7IdEArNDgO1FOJX0CFqN3r8U0Hlr bW6//WZxzp9GPVlP/kUt8vkd5/QKZ9wTzkGtUG7TRmNwoiHyRh+v5VUmykgnQif52VR3 a6UhVBiegn5+Q66VdKVslZC0/aLRuN5d4oE5jbgKJ5sF2UnVmmn2/RHh07Pl1lqgaNN5 uQqD5VHFh0+ogbqljdt454evzvOgi+pNgVMOJuXTybYOBwjIfopzyH7StQ+PprjZudAF znjg== X-Forwarded-Encrypted: i=1; AJvYcCXdmNbV5DVDZ/ip6/brpmdovoGckvq268Jc+NfeWmpfI2LNRZzwFtqorUhF+DrG+NvAjTXOj2Mh8yW2qpI=@vger.kernel.org X-Gm-Message-State: AOJu0YzlBgl0tGKvd5oc7faR/p/Bw3sB5DVWwhQCXElbcgzRaRNot3sV 7moJQbpgyIYf4ek1xg6x7N5n5m7+YBYRcdgYLXgJG9e49gLsb+9urnpsy9xQSdE= X-Gm-Gg: ASbGncsbe2CX0gw+Goz/uXSAXa4jOeI17+DMK5Bg/341GWNInLZh3qpf4Nr1yZEeX0b opUs1GAmeC/mbS5+lWIWyJW8o7x/Jjd4nlcjWEjEsl/W19JYrD+VxMcSA6jd0Dvm61yp2JKeZgl jDXtkD/DbTZm9pilqwLQl/uKW++GhXiILLd49OklBBN1VdnDhbIGCKOy28Sufv8rjQGSTCIpD+g lthRmpJa+zbFL/3Jehhu5WmY7rCsslYOz2Bx5elfMMdTVvReQ== X-Google-Smtp-Source: AGHT+IECaX60QuAonYO0bJYi2tY+HH+x36ibKnOK0IapIsrV15QT17FWq7bCGXEU4iCd0ieDFErr3A== X-Received: by 2002:a17:906:23ea:b0:a9a:10c9:f4b8 with SMTP id a640c23a62f3a-aa58109dc28mr150069966b.61.1732701737692; Wed, 27 Nov 2024 02:02:17 -0800 (PST) Received: from pop-os.. ([145.224.90.200]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa547ffb152sm421887466b.62.2024.11.27.02.02.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Nov 2024 02:02:17 -0800 (PST) From: James Clark To: maz@kernel.org, kvmarm@lists.linux.dev, oliver.upton@linux.dev, suzuki.poulose@arm.com, coresight@lists.linaro.org Cc: James Clark , Mark Brown , James Clark , Joey Gouly , Zenghui Yu , Catalin Marinas , Will Deacon , Mike Leach , Alexander Shishkin , Anshuman Khandual , Fuad Tabba , Shiqi Liu , James Morse , Raghavendra Rao Ananta , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 5/8] arm64/sysreg/tools: Move TRFCR definitions to sysreg Date: Wed, 27 Nov 2024 10:01:22 +0000 Message-Id: <20241127100130.1162639-6-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241127100130.1162639-1-james.clark@linaro.org> References: <20241127100130.1162639-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: James Clark Convert TRFCR to automatic generation. Add separate definitions for ELx and EL2 as TRFCR_EL1 doesn't have CX. This also mirrors the previous definition so no code change is required. Also add TRFCR_EL12 which will start to be used in a later commit. Unfortunately, to avoid breaking the Perf build with duplicate definition errors, the tools copy of the sysreg.h header needs to be updated at the same time rather than the usual second commit. This is because the generated version of sysreg (arch/arm64/include/generated/asm/sysreg-defs.h), is currently shared and tools/ does not have its own copy. Reviewed-by: Mark Brown Signed-off-by: James Clark Signed-off-by: James Clark --- arch/arm64/include/asm/sysreg.h | 12 --------- arch/arm64/tools/sysreg | 36 +++++++++++++++++++++++++++ tools/arch/arm64/include/asm/sysreg.h | 12 --------- 3 files changed, 36 insertions(+), 24 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 345e81e0d2b3..150416682e2c 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -283,8 +283,6 @@ #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) =20 -#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) - #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) =20 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) @@ -519,7 +517,6 @@ #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) =20 -#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) @@ -983,15 +980,6 @@ /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) =20 -#define TRFCR_ELx_TS_SHIFT 5 -#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_EL2_CX BIT(3) -#define TRFCR_ELx_ExTRE BIT(1) -#define TRFCR_ELx_E0TRE BIT(0) - /* GIC Hypervisor interface registers */ /* ICH_MISR_EL2 bit definitions */ #define ICH_MISR_EOI (1 << 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a26c0da0c42d..27a7afd5329a 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1994,6 +1994,22 @@ Sysreg CPACR_EL1 3 0 1 0 2 Fields CPACR_ELx EndSysreg =20 +SysregFields TRFCR_ELx +Res0 63:7 +UnsignedEnum 6:5 TS + 0b0001 VIRTUAL + 0b0010 GUEST_PHYSICAL + 0b0011 PHYSICAL +EndEnum +Res0 4:2 +Field 1 ExTRE +Field 0 E0TRE +EndSysregFields + +Sysreg TRFCR_EL1 3 0 1 2 1 +Fields TRFCR_ELx +EndSysreg + Sysreg SMPRI_EL1 3 0 1 2 4 Res0 63:4 Field 3:0 PRIORITY @@ -2536,6 +2552,22 @@ Field 1 ICIALLU Field 0 ICIALLUIS EndSysreg =20 +Sysreg TRFCR_EL2 3 4 1 2 1 +Res0 63:7 +UnsignedEnum 6:5 TS + 0b0000 USE_TRFCR_EL1_TS + 0b0001 VIRTUAL + 0b0010 GUEST_PHYSICAL + 0b0011 PHYSICAL +EndEnum +Res0 4 +Field 3 CX +Res0 2 +Field 1 E2TRE +Field 0 E0HTRE +EndSysreg + + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 @@ -2946,6 +2978,10 @@ Sysreg ZCR_EL12 3 5 1 2 0 Fields ZCR_ELx EndSysreg =20 +Sysreg TRFCR_EL12 3 5 1 2 1 +Fields TRFCR_ELx +EndSysreg + Sysreg SMCR_EL12 3 5 1 2 6 Fields SMCR_ELx EndSysreg diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/inclu= de/asm/sysreg.h index 345e81e0d2b3..150416682e2c 100644 --- a/tools/arch/arm64/include/asm/sysreg.h +++ b/tools/arch/arm64/include/asm/sysreg.h @@ -283,8 +283,6 @@ #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) =20 -#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) - #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) =20 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) @@ -519,7 +517,6 @@ #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) =20 -#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) @@ -983,15 +980,6 @@ /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) =20 -#define TRFCR_ELx_TS_SHIFT 5 -#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_EL2_CX BIT(3) -#define TRFCR_ELx_ExTRE BIT(1) -#define TRFCR_ELx_E0TRE BIT(0) - /* GIC Hypervisor interface registers */ /* ICH_MISR_EL2 bit definitions */ #define ICH_MISR_EOI (1 << 0) --=20 2.34.1