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([178.197.219.21]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc38afsm15729035f8f.67.2024.11.27.01.36.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Nov 2024 01:36:29 -0800 (PST) From: Krzysztof Kozlowski To: Bjorn Andersson , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH] clk: qcom: clk-alpha-pll: Do not use random stack value for recalc rate Date: Wed, 27 Nov 2024 10:36:23 +0100 Message-ID: <20241127093623.80735-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If regmap_read() fails, random stack value was used in calculating new frequency in recalc_rate() callbacks. Such failure is really not expected as these are all MMIO reads, however code should be here correct and bail out. This also avoids possible warning on uninitialized value. Signed-off-by: Krzysztof Kozlowski --- drivers/clk/qcom/clk-alpha-pll.c | 41 ++++++++++++++++++++++---------- 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index 5e9217ea3760..0cd937ab47d0 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -682,9 +682,12 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned = long parent_rate) struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); u32 alpha_width =3D pll_alpha_width(pll); =20 - regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); + if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) + return 0; + + if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) + return 0; =20 - regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); if (ctl & PLL_ALPHA_EN) { regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); if (alpha_width > 32) { @@ -915,8 +918,11 @@ alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsign= ed long parent_rate) struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); u32 l, alpha =3D 0, ctl, alpha_m, alpha_n; =20 - regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); - regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); + if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) + return 0; + + if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) + return 0; =20 if (ctl & PLL_ALPHA_EN) { regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); @@ -1110,8 +1116,11 @@ clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigne= d long parent_rate) struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); u32 l, frac, alpha_width =3D pll_alpha_width(pll); =20 - regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); - regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); + if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) + return 0; + + if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac)) + return 0; =20 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); } @@ -1169,7 +1178,8 @@ clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, = unsigned long parent_rate) struct clk_alpha_pll_postdiv *pll =3D to_clk_alpha_pll_postdiv(hw); u32 ctl; =20 - regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); + if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) + return 0; =20 ctl >>=3D PLL_POST_DIV_SHIFT; ctl &=3D PLL_POST_DIV_MASK(pll); @@ -1385,8 +1395,11 @@ static unsigned long alpha_pll_fabia_recalc_rate(str= uct clk_hw *hw, struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); u32 l, frac, alpha_width =3D pll_alpha_width(pll); =20 - regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); - regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); + if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) + return 0; + + if (regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac)) + return 0; =20 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); } @@ -2457,9 +2470,12 @@ static unsigned long alpha_pll_lucid_evo_recalc_rate= (struct clk_hw *hw, struct regmap *regmap =3D pll->clkr.regmap; u32 l, frac; =20 - regmap_read(regmap, PLL_L_VAL(pll), &l); + if (regmap_read(regmap, PLL_L_VAL(pll), &l)) + return 0; l &=3D LUCID_EVO_PLL_L_VAL_MASK; - regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); + + if (regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac)) + return 0; =20 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); } @@ -2534,7 +2550,8 @@ static unsigned long clk_rivian_evo_pll_recalc_rate(s= truct clk_hw *hw, struct clk_alpha_pll *pll =3D to_clk_alpha_pll(hw); u32 l; =20 - regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); + if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) + return 0; =20 return parent_rate * l; } --=20 2.43.0