From nobody Tue Feb 10 09:59:20 2026 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A6631E0DE3 for ; Wed, 27 Nov 2024 10:58:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732705100; cv=none; b=LzhdkJjzwtU83m3cOinIAft1/jWMwFz/tYGWsiJGQ0IEQbFJsIkqFKWKOqq4q7gIxacgRwz3X0aSXGPSXpKlq1eyPvf5uicIcIgh56cZIJ7vmN7xw3pRQggdxziWONLrrTWW3RWm/wd5cyR8XuNd9ORg82GTJZie7Qk1QzQsCfU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732705100; c=relaxed/simple; bh=3z+3OrrHs0XCZfDLz7XD+u9amGrH0EuaZhr9cul7jPI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lJH0fbQP93ODqIZyhOqrjugAIVpivcGjXNeCo1AoGulnPK/VtkhNIyPbd8eKKyjrstcbIJaQpSArTDgUPD5fMvQjaifBkG3ONEEnG7oeYMzX8UrFomTs8Wpo3k+LPq4HMVwoJuqYCB3mtkRabARkcpi5F6ycOeUGj/GnlCExF2A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=dkTjMth6; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dkTjMth6" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-aa51d32fa69so702537366b.2 for ; Wed, 27 Nov 2024 02:58:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732705096; x=1733309896; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=AASoBGvbx8nrRldBio8kzQShrHQPCejymiRL3Jm8QQw=; b=dkTjMth6t2njsoqbCIA4Sn69SIcdE3UcAAQmN4hjZmgWks7qcZqqkvK+UtI9n3OQLT H56G/eiEY2k2nPV7pSW9+j7fBh4+FDb7BUEVviVR3/w9mLzXNSbLEs7TQEIQ3dxV0L6y ZngkvNDlhtpH2aZnZgfPgCenoJ+uKwbPQfFw+Ov+YF4SSnh7C9mziU5lDoWu+8ghEfym ejCnqM1VsX9aWAf6GLkj49ykpuFpy6HC+cqm/OySzywwabhw0LfcMMNe3l44rRGrhbu+ rKqsYxfhNntxYBIUGiK/KURz3zaTObewhbaV+Js9CtBB87ts+a+bEzNyNGwfpiUX3Ztc A0Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732705096; x=1733309896; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AASoBGvbx8nrRldBio8kzQShrHQPCejymiRL3Jm8QQw=; b=tqGUUgTNBfb1VbZin7se9eGZMatBgNiNMTY6pDLu+us3GnaDA7x1UWdWlM3oQg4Yt4 MjJhJnCtFjKC2zqJ6hPfWEDKiMARuqR4qQiergyFhPeh4qda/Hd4RY4aXmSaf1tMZGaK 8VGJPyFDCrpFqUm3RwFvav897BrVxOpmpqOHke6nic9vUm3j1IkZasLcIersdupVeQLF vV0q6QwFeOdFlMFKGET3HSvp3zOKay9O8EodIUM+65gO1/BA5PPW+4lkyO9iGsdyC65c PYwz4aLD6yxVzYGZ4YF1p2VVmTqF0UJXuv+nRSfJ32/eFhB+y52n0WLRPCCqyOP7OGkZ rWSw== X-Forwarded-Encrypted: i=1; AJvYcCXoTH5FzQ6IGfn3qXPCV54t0ZKmdP3WWARbD+i8hOQ2TjtdESxOvH8lRi+717hW81TER35rmCqHIOiYG9o=@vger.kernel.org X-Gm-Message-State: AOJu0YytWap6zlxzVyb3CwH+4nRXPJIUFD43Fkw+bYVJ2j4i3UpBbilf 0J5PgJXe+s3wkKOFNJD7X0lSpeTqZquyLwn/dDS9iN5cZiXOmFEvpqqc6Dh8ItU= X-Gm-Gg: ASbGnctSjv06DgSJwATzWIecFbpM1XGTvn+A96LplzVS4yigeuZ39HWcGhuVe/L6y6n RjHcyZB501Le5OKdgKzrjvr8XSW7aDxDNw4HP8Wes5cBYi1/KFoHCwWTLck0VsgqfRS0anYZn+I tnAcHguUbZxwywuuMUmq/O93e/OOcCZptRxtk8z5bhwthtH62OSUqqCj7JBmlz5DdWDdOVPrAi4 hgMLoIDQXgFwkZTnvAwnnbmHlfsHfG2H7CpONF6HjSHqwEJHmVT0FtYnxdyP4nisq4+t/OY4PEp sNXg8+34n1EAp+ZuNZpPA4gRECflAhcwbQ== X-Google-Smtp-Source: AGHT+IF3uxkslq060bQu5IOXE2CVt35TZdsY8S2FoowTgID7ALlXsIj3b2YpVReHJiVUCHWHrA1DAQ== X-Received: by 2002:a17:907:7819:b0:aa5:b2b:f236 with SMTP id a640c23a62f3a-aa580f353f3mr179583566b.28.1732705095696; Wed, 27 Nov 2024 02:58:15 -0800 (PST) Received: from puffmais.c.googlers.com (64.227.90.34.bc.googleusercontent.com. [34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa54a6db906sm412183566b.41.2024.11.27.02.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Nov 2024 02:58:15 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 27 Nov 2024 10:58:17 +0000 Subject: [PATCH 7/9] phy: exynos5-usbdrd: gs101: configure SS lanes based on orientation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241127-gs101-phy-lanes-orientation-phy-v1-7-1b7fce24960b@linaro.org> References: <20241127-gs101-phy-lanes-orientation-phy-v1-0-1b7fce24960b@linaro.org> In-Reply-To: <20241127-gs101-phy-lanes-orientation-phy-v1-0-1b7fce24960b@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar Cc: Peter Griffin , Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 USB SS lanes need to be configured based the connector orientation - at most two lanes will be in use for USB (and the remaining two for alternate modes like DP). For the USB link to come up in SS, the lane configuration registers have to be programmed accordingly. While we still need a way to be notified of the actual connector orientation and then reprogram the registers accordingly (at the moment the configuration happens just once during phy_init() and never again), we can prepare the code doing the configuration to take the orientation into account. Do so. Note: the mutex is needed to synchronize this with the upcoming connector orientation callback. Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Peter Griffin Tested-by: Peter Griffin --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 72 ++++++++++++++++++++++------= ---- 1 file changed, 51 insertions(+), 21 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index c1ce6fdeef31..1a34e9b4618a 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -23,6 +23,7 @@ #include #include #include +#include =20 /* Exynos USB PHY registers */ #define EXYNOS5_FSEL_9MHZ6 0x0 @@ -209,6 +210,10 @@ =20 #define EXYNOS9_PMA_USBDP_CMN_REG00B8 0x02e0 #define CMN_REG00B8_LANE_MUX_SEL_DP GENMASK(3, 0) +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE3 BIT(3) +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE2 BIT(2) +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE1 BIT(1) +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE0 BIT(0) =20 #define EXYNOS9_PMA_USBDP_CMN_REG01C0 0x0700 #define CMN_REG01C0_ANA_LCPLL_LOCK_DONE BIT(7) @@ -383,11 +388,13 @@ struct exynos5_usbdrd_phy_drvdata { * @clks: clocks for register access * @core_clks: core clocks for phy (ref, pipe3, utmi+, ITP, etc. as requir= ed) * @drv_data: pointer to SoC level driver data structure + * @phy_mutex: mutex protecting phy_init/exit & TCPC callbacks * @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY * instances each with its 'phy' and 'phy_cfg'. * @extrefclk: frequency select settings when using 'separate * reference clocks' for SS and HS operations * @regulators: regulators for phy + * @orientation: TypeC connector orientation - normal or flipped */ struct exynos5_usbdrd_phy { struct device *dev; @@ -397,6 +404,7 @@ struct exynos5_usbdrd_phy { struct clk_bulk_data *clks; struct clk_bulk_data *core_clks; const struct exynos5_usbdrd_phy_drvdata *drv_data; + struct mutex phy_mutex; struct phy_usb_instance { struct phy *phy; u32 index; @@ -406,6 +414,8 @@ struct exynos5_usbdrd_phy { } phys[EXYNOS5_DRDPHYS_NUM]; u32 extrefclk; struct regulator_bulk_data *regulators; + + enum typec_orientation orientation; }; =20 static inline @@ -647,22 +657,38 @@ exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel(struct ex= ynos5_usbdrd_phy *phy_drd) /* lane configuration: USB on all lanes */ reg =3D readl(regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8); reg &=3D ~CMN_REG00B8_LANE_MUX_SEL_DP; - writel(reg, regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8); - /* - * FIXME: below code supports one connector orientation only. It needs - * updating once we can receive connector events. + * USB on lanes 0 & 1 in normal mode, or 2 & 3 if reversed, DP on the + * other ones. */ + reg |=3D FIELD_PREP(CMN_REG00B8_LANE_MUX_SEL_DP, + ((phy_drd->orientation =3D=3D TYPEC_ORIENTATION_NORMAL) + ? (CMN_REG00B8_LANE_MUX_SEL_DP_LANE3 + | CMN_REG00B8_LANE_MUX_SEL_DP_LANE2) + : (CMN_REG00B8_LANE_MUX_SEL_DP_LANE1 + | CMN_REG00B8_LANE_MUX_SEL_DP_LANE0))); + writel(reg, regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8); + /* override of TX receiver detector and comparator: lane 1 */ reg =3D readl(regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0413); - reg &=3D ~TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN; - reg &=3D ~TRSV_REG0413_OVRD_LN1_TX_RXD_EN; + if (phy_drd->orientation =3D=3D TYPEC_ORIENTATION_NORMAL) { + reg &=3D ~TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN; + reg &=3D ~TRSV_REG0413_OVRD_LN1_TX_RXD_EN; + } else { + reg |=3D TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN; + reg |=3D TRSV_REG0413_OVRD_LN1_TX_RXD_EN; + } writel(reg, regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0413); =20 /* lane 3 */ reg =3D readl(regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0813); - reg |=3D TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN; - reg |=3D TRSV_REG0813_OVRD_LN3_TX_RXD_EN; + if (phy_drd->orientation =3D=3D TYPEC_ORIENTATION_NORMAL) { + reg |=3D TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN; + reg |=3D TRSV_REG0813_OVRD_LN3_TX_RXD_EN; + } else { + reg &=3D ~TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN; + reg &=3D ~TRSV_REG0813_OVRD_LN3_TX_RXD_EN; + } writel(reg, regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0813); } =20 @@ -700,21 +726,18 @@ exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock(struct = exynos5_usbdrd_phy *phy_drd int err; =20 err =3D readl_poll_timeout( - phy_drd->reg_pma + EXYNOS9_PMA_USBDP_TRSV_REG03C3, - reg, (reg & locked) =3D=3D locked, sleep_us, timeout_us); - if (!err) - return; - - dev_err(phy_drd->dev, - "timed out waiting for CDR lock (l0): %#.8x, retrying\n", reg); - - /* based on cable orientation, this might be on the other phy port */ - err =3D readl_poll_timeout( - phy_drd->reg_pma + EXYNOS9_PMA_USBDP_TRSV_REG07C3, + /* lane depends on cable orientation */ + (phy_drd->reg_pma + + ((phy_drd->orientation =3D=3D TYPEC_ORIENTATION_NORMAL) + ? EXYNOS9_PMA_USBDP_TRSV_REG03C3 + : EXYNOS9_PMA_USBDP_TRSV_REG07C3)), reg, (reg & locked) =3D=3D locked, sleep_us, timeout_us); if (err) dev_err(phy_drd->dev, - "timed out waiting for CDR lock (l2): %#.8x\n", reg); + "timed out waiting for CDR(l%d) lock: %#.8x\n", + ((phy_drd->orientation =3D=3D TYPEC_ORIENTATION_NORMAL) + ? 0 + : 2), reg); } =20 static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) @@ -1184,7 +1207,8 @@ static int exynos850_usbdrd_phy_init(struct phy *phy) return ret; =20 /* UTMI or PIPE3 specific init */ - inst->phy_cfg->phy_init(phy_drd); + scoped_guard(mutex, &phy_drd->phy_mutex) + inst->phy_cfg->phy_init(phy_drd); =20 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); =20 @@ -1203,6 +1227,8 @@ static int exynos850_usbdrd_phy_exit(struct phy *phy) if (ret) return ret; =20 + guard(mutex)(&phy_drd->phy_mutex); + /* Set PHY clock and control HS PHY */ reg =3D readl(regs_base + EXYNOS850_DRD_UTMI); reg &=3D ~(UTMI_DP_PULLDOWN | UTMI_DM_PULLDOWN); @@ -1701,6 +1727,10 @@ static int exynos5_usbdrd_phy_probe(struct platform_= device *pdev) return -EINVAL; phy_drd->drv_data =3D drv_data; =20 + ret =3D devm_mutex_init(dev, &phy_drd->phy_mutex); + if (ret) + return ret; + if (of_property_present(dev->of_node, "reg-names")) { void __iomem *reg; =20 --=20 2.47.0.338.g60cca15819-goog