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Wed, 27 Nov 2024 09:52:55 +0000 (UTC) From: Janne Grunau via B4 Relay Date: Wed, 27 Nov 2024 10:52:28 +0100 Subject: [PATCH RESEND 1/5] arm64: dts: apple: t8103: Fix spi4 power domain sort order Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241127-asahi-spi-dt-v1-1-907c9447f623@jannau.net> References: <20241127-asahi-spi-dt-v1-0-907c9447f623@jannau.net> In-Reply-To: <20241127-asahi-spi-dt-v1-0-907c9447f623@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1456; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=dM/GrGK9N/5tAToyLPPTWx70HidhWtGG6XOo893Pexw=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnS311/32JbP5bsq58ui+/r2j9WvAx7t70h6m/D3h2PmR VuH+oK0jlIWBjEuBlkxRZYk7ZcdDKtrFGNqH4TBzGFlAhnCwMUpABPZPp3hr/hp1+8/arcbTFp/ 4argg5kL7Fgvv93rdbijhvPHpdnzTxgzMtwQfK5+QCftNNcO8/Ue4mtZH3FndTJeEwgW83u7f/H jTBYA X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Hector Martin Signed-off-by: Hector Martin Reviewed-by: Neal Gompa --- arch/arm64/boot/dts/apple/t8103-pmgr.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/t8103-pmgr.dtsi index 9645861a858c1a7c46c25a614c2cc4b03083bf46..c41c57d63997a59a9fe3c88de31= fddb31781398e 100644 --- a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi @@ -387,6 +387,15 @@ ps_spi3: power-controller@258 { power-domains =3D <&ps_sio>, <&ps_spi_p>; }; =20 + ps_spi4: power-controller@260 { + compatible =3D "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi4"; + power-domains =3D <&ps_sio>, <&ps_spi_p>; + }; + ps_uart_n: power-controller@268 { compatible =3D "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; reg =3D <0x268 4>; @@ -558,15 +567,6 @@ ps_mcc: power-controller@2f8 { apple,always-on; /* Memory controller */ }; =20 - ps_spi4: power-controller@260 { - compatible =3D "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg =3D <0x260 4>; - #power-domain-cells =3D <0>; - #reset-cells =3D <0>; - label =3D "spi4"; - power-domains =3D <&ps_sio>, <&ps_spi_p>; - }; - ps_dcs0: power-controller@300 { compatible =3D "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; reg =3D <0x300 4>; --=20 2.47.0 From nobody Mon Feb 9 14:09:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 885BE193439; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241127-asahi-spi-dt-v1-2-907c9447f623@jannau.net> References: <20241127-asahi-spi-dt-v1-0-907c9447f623@jannau.net> In-Reply-To: <20241127-asahi-spi-dt-v1-0-907c9447f623@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3356; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=b1UDB+1sljglElFujEd7C6cEIDOAyC8En801j5/oUGU=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnS3119tX+Uacs/mOXwpqKM5bHcqw6rs+B/hWQcmpql+L nxcbbGoo5SFQYyLQVZMkSVJ+2UHw+oaxZjaB2Ewc1iZQIYwcHEKwETmSTL8z1//ftWNnQxygtu7 f29ROvrRaHPpCjbrna3b5CfondAq3sDwz+BMr3HB8aiG38rtLiw8nvH9F+XW7lD4lNGWLr3mfHQ BLwA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Janne Grunau Apple silicon devices have one or more SPI devices. Add device tree nodes for all known controllers. The missing ones could be guessed and tested with a little effort but since the devices expose no pins and no new devices are expected there is no point in spending the effort. SPI is used for spi-nor and input devices like keyboard, trackpad, touchscreen and fingerprint reader. Only the spi-nor flash has upstream drivers. Support for it will be added in a following commit. Signed-off-by: Janne Grunau Reviewed-by: Neal Gompa --- arch/arm64/boot/dts/apple/t8103.dtsi | 68 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/app= le/t8103.dtsi index 9b0dad6b618444ac6b1c9735c50cccfc3965f947..9b2d32059c3542f12fedd7f4dca= 309baa66c1bd4 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -326,6 +326,20 @@ clkref: clock-ref { clock-output-names =3D "clkref"; }; =20 + clk_120m: clock-120m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <120000000>; + clock-output-names =3D "clk_120m"; + }; + + clk_200m: clock-200m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + clock-output-names =3D "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. @@ -441,6 +455,46 @@ fpwm1: pwm@235044000 { status =3D "disabled"; }; =20 + spi0: spi@235100000 { + compatible =3D "apple,t8103-spi", "apple,spi"; + reg =3D <0x2 0x35100000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clk_200m>; + power-domains =3D <&ps_spi0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi1: spi@235104000 { + compatible =3D "apple,t8103-spi", "apple,spi"; + reg =3D <0x2 0x35104000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clk_200m>; + pinctrl-0 =3D <&spi1_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi3: spi@23510c000 { + compatible =3D "apple,t8103-spi", "apple,spi"; + reg =3D <0x2 0x3510c000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clk_120m>; + pinctrl-0 =3D <&spi3_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + serial0: serial@235200000 { compatible =3D "apple,s5l-uart"; reg =3D <0x2 0x35200000 0x0 0x1000>; @@ -597,6 +651,20 @@ i2c4_pins: i2c4-pins { ; }; =20 + spi1_pins: spi1-pins { + pinmux =3D , + , + , + ; + }; + + spi3_pins: spi3-pins { + pinmux =3D , + , + , + ; + }; + pcie_pins: pcie-pins { pinmux =3D , , --=20 2.47.0 From nobody Mon Feb 9 14:09:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8855F191F7C; Wed, 27 Nov 2024 09:52:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732701176; cv=none; b=mMBhZqSbRnU2IDn5CTQP4L2uOneEg+SjGcFRg5C+YvM+NlUro1Js89jFGeYxQqU5SFOwaMFBQeZj+tdCcNFPQiavzkpC+nZm3F58e6KOkvziHlz+BdTR0ChT6lAl/nBig3OTRNzRVaCV4uWYO8+3Y9UGbjg1yhPu6YVmCfTHw40= ARC-Message-Signature: i=1; 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b=o9f+zsvYC09+kZeR1wKs0hTR1xuo2kMQx8dNVa+kbQhG0StCap70herRilGL1gQM6 y0aJKW2G6j9rWDH/JTfQA1hDymWJFR7gZUR2n3L17acAf8NO1h3C2ASGifCgeCxrkV om4ZETumO9JZa3uQ/wJ56plUJmYOOGKNokeA4qRggt8K1vX80DEahZMMlW9a5zx4Sr xW4qhTbmgBjmGITbmO6iXuUw27Fz5D8u8OopAFCcQmLCGibZQ6PKDOP6kyg38zJ1BW 62uaEg2Fdv5GbLdGOV8c32lTJFFTWYmebfb9U964v18nBUoxLydGYnomh5VLOu+LTa 46wQkrTqJLc3A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30E80D609C7; Wed, 27 Nov 2024 09:52:56 +0000 (UTC) From: Janne Grunau via B4 Relay Date: Wed, 27 Nov 2024 10:52:30 +0100 Subject: [PATCH RESEND 3/5] arm64: dts: apple: t8112: Add spi controller nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241127-asahi-spi-dt-v1-3-907c9447f623@jannau.net> References: <20241127-asahi-spi-dt-v1-0-907c9447f623@jannau.net> In-Reply-To: <20241127-asahi-spi-dt-v1-0-907c9447f623@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2887; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=qBexsIdH/GqhHy7brZ1sYsseqom1YJB59+/UbwP2L/Y=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnS3199kAmQMk2+x5WvrHfMw5Uo4lqjkNf2z8uwpv4oFR SR+zH7QUcrCIMbFICumyJKk/bKDYXWNYkztgzCYOaxMIEMYuDgFYCLvQxn+aTnqPhVYlLAo+aBo cJ3LG/eF4bsv/E8oe1I3deYaE5lCdUaGPQ3nF77cwKvEGcNsMbVAVDTmm0HD8VdH1WMPscZUvj/ PAwA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Janne Grunau Apple silicon devices have one or more SPI devices. Add device tree nodes for all known controllers. The missing ones could be guessed and tested with a little effort but since the devices expose no pins and no new devices are expected there is no point in spending the effort. SPI is used for spi-nor and input devices like keyboard, trackpad, touchscreen and fingerprint reader. Only the spi-nor flash has upstream drivers. Support for it will be added in a following commit. Signed-off-by: Janne Grunau Reviewed-by: Neal Gompa --- arch/arm64/boot/dts/apple/t8112.dtsi | 44 ++++++++++++++++++++++++++++++++= +++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/app= le/t8112.dtsi index 1666e6ab250bc0be9b8318e3c8fc903ccd3f3760..58d88f1ef92a32061765bd3b569= fdae0255dcd7e 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -349,6 +349,13 @@ clkref: clock-ref { clock-output-names =3D "clkref"; }; =20 + clk_200m: clock-200m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + clock-output-names =3D "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. @@ -467,6 +474,34 @@ fpwm1: pwm@235044000 { status =3D "disabled"; }; =20 + spi1: spi@235104000 { + compatible =3D "apple,t8112-spi", "apple,spi"; + reg =3D <0x2 0x35104000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clk_200m>; + pinctrl-0 =3D <&spi1_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi3: spi@23510c000 { + compatible =3D "apple,t8112-spi", "apple,spi"; + reg =3D <0x2 0x3510c000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clkref>; + pinctrl-0 =3D <&spi3_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + serial0: serial@235200000 { compatible =3D "apple,s5l-uart"; reg =3D <0x2 0x35200000 0x0 0x1000>; @@ -626,13 +661,20 @@ i2c4_pins: i2c4-pins { ; }; =20 - spi3_pins: spi3-pins { + spi1_pins: spi1-pins { pinmux =3D , , , ; }; =20 + spi3_pins: spi3-pins { + pinmux =3D , + , + , + ; + }; + pcie_pins: pcie-pins { pinmux =3D , , --=20 2.47.0 From nobody Mon Feb 9 14:09:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADC7B1946A8; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241127-asahi-spi-dt-v1-4-907c9447f623@jannau.net> References: <20241127-asahi-spi-dt-v1-0-907c9447f623@jannau.net> In-Reply-To: <20241127-asahi-spi-dt-v1-0-907c9447f623@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3545; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=+9ZFqpJ8nwSbJAAJz7hiOfMfbrOzc9lBaAhTOBlh010=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnS3199Sg2//E4+fn39gr8z9iw1ZC4Jid5v77g+cdvFKy KucK12bO0pZGMS4GGTFFFmStF92MKyuUYypfRAGM4eVCWQIAxenAExkyQuGf6bVaaJWXWxFL6cs 7D9faSL91MUl4IFpUJ6Qk2llmHu2BsP/evaFlfb16mfeP72zwN9ypVlO7uSpM5dcfNMsFrB8tc5 TTgA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Janne Grunau Apple silicon devices have one or more SPI devices. Add device tree nodes for all known controllers. The missing ones could be guessed and tested with a little effort but since the devices expose no pins and no new devices are expected there is no point in spending the effort. SPI is used for spi-nor and input devices like keyboard, trackpad, touchscreen and fingerprint reader. Only the spi-nor flash has upstream drivers. Support for it will be added in a following commit. Signed-off-by: Janne Grunau Reviewed-by: Neal Gompa --- arch/arm64/boot/dts/apple/t600x-common.dtsi | 7 +++++++ arch/arm64/boot/dts/apple/t600x-die0.dtsi | 28 ++++++++++++++++++++++= ++++ arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi | 14 +++++++++++++ 3 files changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t600x-common.dtsi b/arch/arm64/boot/= dts/apple/t600x-common.dtsi index fa8ead69936366999786cdd4910266ee08b5ca7a..87dfc13d74171f62bf308740191= 8d9d41eaac560 100644 --- a/arch/arm64/boot/dts/apple/t600x-common.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-common.dtsi @@ -362,6 +362,13 @@ clkref: clock-ref { clock-output-names =3D "clkref"; }; =20 + clk_200m: clock-200m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + clock-output-names =3D "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dt= s/apple/t600x-die0.dtsi index b1c875e692c8fb9c0af46a23568a7b0cd720141b..e9b3140ba1a996eeb91b3f60470= 833060b632bd2 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -163,6 +163,34 @@ i2c5: i2c@39b054000 { status =3D "disabled"; }; =20 + spi1: spi@39b104000 { + compatible =3D "apple,t6000-spi", "apple,spi"; + reg =3D <0x3 0x9b104000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk_200m>; + pinctrl-0 =3D <&spi1_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi1>; + status =3D "disabled"; + }; + + spi3: spi@39b10c000 { + compatible =3D "apple,t6000-spi", "apple,spi"; + reg =3D <0x3 0x9b10c000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkref>; + pinctrl-0 =3D <&spi3_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi3>; + status =3D "disabled"; + }; + serial0: serial@39b200000 { compatible =3D "apple,s5l-uart"; reg =3D <0x3 0x9b200000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi b/arch/arm64/bo= ot/dts/apple/t600x-gpio-pins.dtsi index b31f1a7a2b3fc36e7dfa480d27012d6d0fd56f97..1a994c3c1b79f088d685e13d1dc= 16e7d1e6546f4 100644 --- a/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi @@ -36,6 +36,20 @@ i2c5_pins: i2c5-pins { ; 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Wed, 27 Nov 2024 09:52:56 +0000 (UTC) From: Janne Grunau via B4 Relay Date: Wed, 27 Nov 2024 10:52:32 +0100 Subject: [PATCH RESEND 5/5] arm64: dts: apple: Add SPI NOR nvram partition to all devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241127-asahi-spi-dt-v1-5-907c9447f623@jannau.net> References: <20241127-asahi-spi-dt-v1-0-907c9447f623@jannau.net> In-Reply-To: <20241127-asahi-spi-dt-v1-0-907c9447f623@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3506; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=4sH2FvtVOU7J6ZD/GsHPG804yvHnrTdh0gHvxrTVtvc=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnS3199yz65NmvRLy/PKvT2HH3orSzo3i20U+PxT+eJJz uZfG5fEdJSyMIhxMciKKbIkab/sYFhdoxhT+yAMZg4rE8gQBi5OAZhIfA3D/6Dd01wWcimWFCQK BD1dH/ZFfEeit7bZrT/GSQxSxe1HJjH84fweaFBQPCFc80/cl5kVc4qTd1yYsytiTXStSmXG9k/ qzAA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Janne Grunau All known M1* and M2* devices use an identical SPI NOR flash configuration with a partition containing a non-volatile key:value storage. Use a .dtsi and include it for every device. The nvram partition parameters itself depend on the version of the installed Apple iboot boot loader. m1n1 will fill in the current values provided by Apple's iboot. Signed-off-by: Janne Grunau Reviewed-by: Neal Gompa --- arch/arm64/boot/dts/apple/spi1-nvram.dtsi | 39 ++++++++++++++++++++++= ++++ arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi | 2 ++ arch/arm64/boot/dts/apple/t600x-j375.dtsi | 2 ++ arch/arm64/boot/dts/apple/t8103-jxxx.dtsi | 2 ++ arch/arm64/boot/dts/apple/t8112-jxxx.dtsi | 2 ++ 5 files changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/apple/spi1-nvram.dtsi b/arch/arm64/boot/dt= s/apple/spi1-nvram.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..3df2fd3993b52884d7c00b65099= c88d830a7a4c3 --- /dev/null +++ b/arch/arm64/boot/dts/apple/spi1-nvram.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Devicetree include for common spi-nor nvram flash. +// +// Apple uses a consistent configiguration for the nvram on all known M1* = and +// M2* devices. +// +// Copyright The Asahi Linux Contributors + +/ { + aliases { + nvram =3D &nvram; + }; +}; + +&spi1 { + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-max-frequency =3D <25000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + nvram: partition@700000 { + label =3D "nvram"; + /* To be filled by the loader */ + reg =3D <0x0 0x0>; + status =3D "disabled"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/bo= ot/dts/apple/t600x-j314-j316.dtsi index 2e471dfe43cf885c1234d36bf0e0acfdc4904621..22ebc78e120bf8f0f71fd532e9d= ce4dcd117bbc6 100644 --- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -119,3 +119,5 @@ sdhci0: mmc@0,0 { &fpwm0 { status =3D "okay"; }; + +#include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dt= s/apple/t600x-j375.dtsi index 1e5a19e49b089d4b3c5e12828b682d1993e35e75..d5b985ad567936111ee5cccc9ca= 9fc23d01d9edf 100644 --- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -126,3 +126,5 @@ &pcie0_dart_2 { &pcie0_dart_3 { status =3D "okay"; }; + +#include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dt= s/apple/t8103-jxxx.dtsi index 5988a4eb6efaa008c290b1842e0da2aae8052ba4..8e82231acab59ca0bffdcecfb66= 81f59661fcd96 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -90,3 +90,5 @@ bluetooth0: bluetooth@0,1 { &nco_clkref { clock-frequency =3D <900000000>; }; + +#include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi b/arch/arm64/boot/dt= s/apple/t8112-jxxx.dtsi index f5edf61113e7aa869613d672b281f7b7e84efb79..6da35496a4c88dbaba125ebbe8c= 5a4a428c647c3 100644 --- a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi @@ -79,3 +79,5 @@ &i2c3 { &nco_clkref { clock-frequency =3D <900000000>; }; + +#include "spi1-nvram.dtsi" --=20 2.47.0