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Tue, 26 Nov 2024 10:58:44 -0800 From: Vishwaroop A To: , , , , , , , , , , , CC: Vishwaroop A Subject: [PATCH 1/3] mtd: spi-nor: Add post-get-map-id fixup for S25FS512S/S1 Date: Tue, 26 Nov 2024 18:58:32 +0000 Message-ID: <20241126185834.1130949-2-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241126185834.1130949-1-va@nvidia.com> References: <20241126185834.1130949-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004683:EE_|CYYPR12MB8963:EE_ X-MS-Office365-Filtering-Correlation-Id: 277c496d-0ee8-4695-11a2-08dd0e4c6846 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?McsfNMhr//XjluxzW03tq1NRl58qkqM0xhQ1mSAz50oxzv2aDjcMkrYMhHMT?= =?us-ascii?Q?C2NOJKKMpvJ9L0qizUGIZlsC6nr2OoyAuBx/NwN2ZPxhSDvKArR9NqgSpWoI?= =?us-ascii?Q?jhoCY4nsPCi3CIjsHwuC9DFlePhTam4pP8cEO5HU8bvdqauPr/uVdb/yIZn5?= =?us-ascii?Q?w1DC4jdeR5qljBnL3CmMn9zyXp33pl4aZhlrCOJzPwv7hm01b/+QliTfDyQr?= =?us-ascii?Q?gZa93r/LYVCn/novD0gOJokeQNBfoxZkqrxLD/eWX/qHU5fmycCefkLEonSB?= =?us-ascii?Q?Meycp7Acdl0L8b1+hijZLmrMziZxb63rp0OVa40CA4UFTDiAn8ahDHzWp00D?= =?us-ascii?Q?eu22eHbxNorhfurHK7j74sR17zTKeyk+zvTRJfXNzLWooI+oAa1L9s+0hmS4?= =?us-ascii?Q?2AfzGo9VbZmm56gOD1K7pnqIN/ga4oByVuldlNJNtggUfOubB5n7HcwQLOv5?= =?us-ascii?Q?94PvOfxvOziI9X8NrKDIhnDJGGSMsqbBpLeGq21cmpA7Vqj5fHceVhgcC/fk?= =?us-ascii?Q?KPKhgqYRYky5W71l2uL/RWtPAjmvGfr4MIY+5Iy9mHIJCllDtrCrT68gkn0e?= =?us-ascii?Q?jgDfmiHR4PYPkACvfE28BI9wuq4UWAqE/rvyWMvJfzZQ3zHdAQMmIs4HDs5l?= =?us-ascii?Q?hVltMvkuDo8twCKCl0APZVi97sXkZfkgIkTS5QPMPxOxS/54nyc44PezJjBn?= =?us-ascii?Q?nFUzmY2xSmJ03eVrmJ6a8DibyOWLMXV4+/+EsLlhHM4+8EPwmvsQfgoBEHQr?= =?us-ascii?Q?pI1OxgUj+xkget4Fk2V18yXIrLc4n1IM9mHmyUAcqCKLcQ4RRj8MsQMChlCc?= =?us-ascii?Q?2aHrz7XeoxK8Yf0lR2ueFGA9mI3NJb8xg6UPwqYB2Vu0S0XpyqI8sC1tb7zw?= =?us-ascii?Q?5EEDrty77pxjzYKot1T1r2peRI07FyN6kcm+wlEelRuRoDV7EG7oHzPFunM3?= =?us-ascii?Q?7T3y1R9G2kq+8QjPqX7dogcC1UFqCc5MyoYDoXpZsWXdpXWbdZbS80EVIlPt?= =?us-ascii?Q?YzmMWG3VPo+04nf3nbINdMS2aAWQWU9lV48GenHzQaERykibHRhfQUFni2Z+?= =?us-ascii?Q?aHeahBCOa+zt6RPXjtxqWI0fRAsxOyJN4lFy7J8Msj1ayareAets3uJw4mr5?= =?us-ascii?Q?adhzkbHqjT8f7XJ64lg6K3ZCof6RmwDEEVRTVUJ2NfAa368oY3EJp1TbjUGc?= =?us-ascii?Q?vyzAKM6Snds5BKJAzLRcJ5bFKU2ffW6ICchpko/Ia3VeHE/rHbXYaTqQ9RBq?= =?us-ascii?Q?CBEwcMdF6wCXSJjt7kk27CiatWdlijjSCKgabM5NAWxb9CbTPplmg9j4y+wD?= =?us-ascii?Q?83n4NfXBN3GWEBrSoULkpSbdjxMQRevK1LHLkwDqJ8144ybrebLWgJiiZfef?= =?us-ascii?Q?hBYF7ZRskbeCD8n1EgvUj6y6opjWj6VypezOr/NPSnfEwRRxXy75IGvco9ri?= =?us-ascii?Q?kbGtsPY4rBdRPxC5iUK33Z73xmUqDWbu1rxjbFuF2zH5NpkVGAJ0CA=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2024 18:59:08.4173 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 277c496d-0ee8-4695-11a2-08dd0e4c6846 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004683.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8963 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SFDP Address Map for S25FS512S / S25FS512S1 devices incorrectly reports that the map ID is 0 when it should be 1. This issue can cause problems when trying to erase sectors on the flash device. Add a post-get-map-id fixup for S25FS512S / S1 flash devices. The fixup reads the values of the CR3V and CR1V registers and determines the map ID based on those values. The fixup also checks for invalid combinations of CR3V and CR1V values.This fixup is necessary to workaround an issue with the SFDP Address Map for S25FS512S flash. Change-Id: Ide18bb4ee076cd36c57b0b52b5d49b63c3caf322 Signed-off-by: Vishwaroop A --- drivers/mtd/spi-nor/core.c | 25 +++++++++++++++++++++ drivers/mtd/spi-nor/core.h | 4 ++++ drivers/mtd/spi-nor/sfdp.c | 7 ++++++ drivers/mtd/spi-nor/spansion.c | 41 ++++++++++++++++++++++++++++++++++ 4 files changed, 77 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 66949d9f0cc5..a76202c6d252 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2408,6 +2408,31 @@ int spi_nor_post_bfpt_fixups(struct spi_nor *nor, return 0; } =20 +/** + * spi_nor_post_get_map_id_fixups - Apply post-processing fixups for map ID + * @nor: Pointer to the spi_nor structure + * @smpt: Pointer to the sector map parameter table + * @smpt_len: Length of the sector map parameter table + * @map_id: Pointer to store the updated map ID + * + * Return: 0 on success (including when no fixup is applied), + * positive value if a new map_id is set, + * negative value on error + */ +int spi_nor_post_get_map_id_fixups(struct spi_nor *nor, const u32 *smpt, + u8 smpt_len, u8 *map_id) +{ + int ret; + + if (nor->info->fixups && nor->info->fixups->post_get_map_id) { + ret =3D nor->info->fixups->post_get_map_id(nor, smpt, smpt_len); + if (ret < 0) + return ret; + *map_id =3D ret; + } + return 0; +} + static int spi_nor_select_read(struct spi_nor *nor, u32 shared_hwcaps) { diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 5c33740ed7f5..37a9f43e1bf9 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -428,6 +428,7 @@ struct spi_nor_fixups { const struct sfdp_bfpt *bfpt); int (*post_sfdp)(struct spi_nor *nor); int (*late_init)(struct spi_nor *nor); + int (*post_get_map_id)(struct spi_nor *nor, const u32 *smpt, u8 smpt_len); }; =20 /** @@ -661,6 +662,9 @@ int spi_nor_post_bfpt_fixups(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, const struct sfdp_bfpt *bfpt); =20 +int spi_nor_post_get_map_id_fixups(struct spi_nor *nor, const u32 *smpt, + u8 smpt_len, u8 *map_id); + void spi_nor_init_default_locking_ops(struct spi_nor *nor); void spi_nor_try_unlock_all(struct spi_nor *nor); void spi_nor_set_mtd_locking_ops(struct spi_nor *nor); diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 21727f9a4ac6..87af29d2c28b 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -769,6 +769,13 @@ static const u32 *spi_nor_get_map_in_use(struct spi_no= r *nor, const u32 *smpt, map_id =3D map_id << 1 | !!(*buf & read_data_mask); } =20 + err =3D spi_nor_post_get_map_id_fixups(nor, smpt, smpt_len, &map_id); + + if (err < 0) { + dev_err(nor->dev, "Error in post_get_map_id fixup: %d\n", err); + return ERR_PTR(err); + } + /* * If command descriptors are provided, they always precede map * descriptors in the table. There is no need to start the iteration diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 5a88a6096ca8..2e1dd023a1aa 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -25,6 +25,7 @@ #define SPINOR_REG_CYPRESS_STR1V \ (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_STR1) #define SPINOR_REG_CYPRESS_CFR1 0x2 +#define SPINOR_REG_CYPRESS_CFR1V 0x00800002 #define SPINOR_REG_CYPRESS_CFR1_QUAD_EN BIT(1) /* Quad Enable */ #define SPINOR_REG_CYPRESS_CFR2 0x3 #define SPINOR_REG_CYPRESS_CFR2V \ @@ -33,6 +34,7 @@ #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb #define SPINOR_REG_CYPRESS_CFR2_ADRBYT BIT(7) #define SPINOR_REG_CYPRESS_CFR3 0x4 +#define SPINOR_REG_CYPRESS_CFR3V 0x00800004 #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ #define SPINOR_REG_CYPRESS_CFR5 0x6 #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) @@ -754,8 +756,47 @@ s25fs_s_nor_post_bfpt_fixups(struct spi_nor *nor, return 0; } =20 +static int s25fs_s_nor_post_get_map_id(struct spi_nor *nor, const u32 *smp= t, u8 smpt_len) +{ + struct spi_mem_op op =3D + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1), + SPI_MEM_OP_ADDR(3, 0, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1)); + + u8 reg_cr3v_val, reg_cr1v_val; + int ret; + + /* Read CR3V value from Configuration Register 3 Volatile */ + op.addr.val =3D SPINOR_REG_CYPRESS_CFR3V; + ret =3D spi_mem_exec_op(nor->spimem, &op); + if (ret) + return ret; + reg_cr3v_val =3D nor->bouncebuf[0]; + + /* Read CR1V value from Configuration Register 1 Volatile */ + op.addr.val =3D SPINOR_REG_CYPRESS_CFR1V; + ret =3D spi_mem_exec_op(nor->spimem, &op); + if (ret) + return ret; + reg_cr1v_val =3D nor->bouncebuf[0]; + + /* Determine the map ID based on CR3V[3] and CR1V[2] values */ + if (!(reg_cr3v_val & BIT(3)) && !(reg_cr1v_val & BIT(2))) + return 1; /* CR3V[3] =3D 0, CR1V[2] =3D 0, map id =3D 1 */ + + if (!(reg_cr3v_val & BIT(3)) && (reg_cr1v_val & BIT(2))) + return 3; /* CR3V[3] =3D 0, CR1V[2] =3D 1, map id =3D 3 */ + + if ((reg_cr3v_val & BIT(3)) && !(reg_cr1v_val & BIT(2))) + return 5; /* CR3V[3] =3D 1, CR1V[2] =3D 0, map id =3D 5 */ + + return 0; +} + static const struct spi_nor_fixups s25fs_s_nor_fixups =3D { .post_bfpt =3D s25fs_s_nor_post_bfpt_fixups, + .post_get_map_id =3D s25fs_s_nor_post_get_map_id, }; =20 static const struct flash_info spansion_nor_parts[] =3D { --=20 2.17.1