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charset="utf-8" Previous reference clock of i.MX95 PCIe RC is on when system boot to kernel. But boot firmware change the behavor, it is off when boot. So it needs be turn on when it is used. Also it needs be turn off/on when suspend and resume. Add one ref clock for i.MX95 PCIe RC. Increase clocks' maxItems to 5 and keep the same restriction with other compatible string. Signed-off-by: Richard Zhu Reviewed-by: Krzysztof Kozlowski --- .../bindings/pci/fsl,imx6q-pcie-common.yaml | 4 +-- .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 1 + .../bindings/pci/fsl,imx6q-pcie.yaml | 25 ++++++++++++++++--- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.ya= ml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml index a8b34f58f8f4..cddbe21f99f2 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml @@ -17,11 +17,11 @@ description: properties: clocks: minItems: 3 - maxItems: 4 + maxItems: 5 =20 clock-names: minItems: 3 - maxItems: 4 + maxItems: 5 =20 num-lanes: const: 1 diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b= /Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml index 7bd00faa1f2c..0b3526de1d62 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -118,6 +118,7 @@ allOf: properties: clocks: minItems: 4 + maxItems: 4 clock-names: items: - const: pcie diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Do= cumentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 1e05c560d797..4c76cd3f98a9 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -40,10 +40,11 @@ properties: - description: PCIe PHY clock. - description: Additional required clock entry for imx6sx-pcie, imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep. + - description: PCIe reference clock. =20 clock-names: minItems: 3 - maxItems: 4 + maxItems: 5 =20 interrupts: items: @@ -127,7 +128,7 @@ allOf: then: properties: clocks: - minItems: 4 + maxItems: 4 clock-names: items: - const: pcie @@ -140,11 +141,10 @@ allOf: compatible: enum: - fsl,imx8mq-pcie - - fsl,imx95-pcie then: properties: clocks: - minItems: 4 + maxItems: 4 clock-names: items: - const: pcie @@ -200,6 +200,23 @@ allOf: - const: mstr - const: slv =20 + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie + then: + properties: + clocks: + maxItems: 5 + clock-names: + items: + - const: pcie + - const: pcie_bus + - const: pcie_phy + - const: pcie_aux + - const: ref + unevaluatedProperties: false =20 examples: --=20 2.37.1 From nobody Wed Nov 27 00:25:58 2024 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2080.outbound.protection.outlook.com [40.107.21.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0515D19DF95; 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Received: from AS8PR04MB8676.eurprd04.prod.outlook.com (2603:10a6:20b:42b::10) by DB9PR04MB9401.eurprd04.prod.outlook.com (2603:10a6:10:36b::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8182.18; Tue, 26 Nov 2024 07:57:46 +0000 Received: from AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93]) by AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93%4]) with mapi id 15.20.8182.019; Tue, 26 Nov 2024 07:57:46 +0000 From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, frank.li@nxp.com, s.hauer@pengutronix.de, festevam@gmail.com Cc: imx@lists.linux.dev, kernel@pengutronix.de, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Richard Zhu , Frank Li Subject: [PATCH v7 02/10] PCI: imx6: Add ref clock for i.MX95 PCIe Date: Tue, 26 Nov 2024 15:56:54 +0800 Message-Id: <20241126075702.4099164-3-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241126075702.4099164-1-hongxing.zhu@nxp.com> References: <20241126075702.4099164-1-hongxing.zhu@nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SI1PR02CA0060.apcprd02.prod.outlook.com (2603:1096:4:1f5::17) To AS8PR04MB8676.eurprd04.prod.outlook.com (2603:10a6:20b:42b::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS8PR04MB8676:EE_|DB9PR04MB9401:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b5f351c-bd11-4320-e658-08dd0df003e2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|52116014|7416014|921020|38350700014; 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charset="utf-8" Add "ref" clock to enable reference clock. To avoid breaking DT backwards compatibility, i.MX95 REF clock might be optional. Use devm_clk_get_optional() to fetch i.MX95 PCIe optional clocks in driver. If use external clock, ref clock should point to external reference. If use internal clock, CREF_EN in LAST_TO_REG controls reference output, which implement in drivers/clk/imx/clk-imx95-blk-ctl.c. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 385f6323e3ca..f7e928e0a018 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -103,6 +103,7 @@ struct imx_pcie_drvdata { const char *gpr; const char * const *clk_names; const u32 clks_cnt; + const u32 clks_optional_cnt; const u32 ltssm_off; const u32 ltssm_mask; const u32 mode_off[IMX_PCIE_MAX_INSTANCES]; @@ -1306,9 +1307,8 @@ static int imx_pcie_probe(struct platform_device *pde= v) struct device_node *np; struct resource *dbi_base; struct device_node *node =3D dev->of_node; - int ret; + int i, ret, req_cnt; u16 val; - int i; =20 imx_pcie =3D devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL); if (!imx_pcie) @@ -1358,9 +1358,13 @@ static int imx_pcie_probe(struct platform_device *pd= ev) imx_pcie->clks[i].id =3D imx_pcie->drvdata->clk_names[i]; =20 /* Fetch clocks */ - ret =3D devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt, imx_pcie->clk= s); + req_cnt =3D imx_pcie->drvdata->clks_cnt - imx_pcie->drvdata->clks_optiona= l_cnt; + ret =3D devm_clk_bulk_get(dev, req_cnt, imx_pcie->clks); if (ret) return ret; + imx_pcie->clks[req_cnt].clk =3D devm_clk_get_optional(dev, "ref"); + if (IS_ERR(imx_pcie->clks[req_cnt].clk)) + return PTR_ERR(imx_pcie->clks[req_cnt].clk); =20 if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) { imx_pcie->phy =3D devm_phy_get(dev, "pcie-phy"); @@ -1509,6 +1513,7 @@ static const char * const imx8mm_clks[] =3D {"pcie_bu= s", "pcie", "pcie_aux"}; static const char * const imx8mq_clks[] =3D {"pcie_bus", "pcie", "pcie_phy= ", "pcie_aux"}; static const char * const imx6sx_clks[] =3D {"pcie_bus", "pcie", "pcie_phy= ", "pcie_inbound_axi"}; static const char * const imx8q_clks[] =3D {"mstr", "slv", "dbi"}; +static const char * const imx95_clks[] =3D {"pcie_bus", "pcie", "pcie_phy"= , "pcie_aux", "ref"}; =20 static const struct imx_pcie_drvdata drvdata[] =3D { [IMX6Q] =3D { @@ -1623,8 +1628,9 @@ static const struct imx_pcie_drvdata drvdata[] =3D { [IMX95] =3D { .variant =3D IMX95, .flags =3D IMX_PCIE_FLAG_HAS_SERDES, - .clk_names =3D imx8mq_clks, - .clks_cnt =3D ARRAY_SIZE(imx8mq_clks), + .clk_names =3D imx95_clks, + .clks_cnt =3D ARRAY_SIZE(imx95_clks), + .clks_optional_cnt =3D 1, .ltssm_off =3D IMX95_PE0_GEN_CTRL_3, .ltssm_mask =3D IMX95_PCIE_LTSSM_EN, .mode_off[0] =3D IMX95_PE0_GEN_CTRL_1, --=20 2.37.1 From nobody Wed Nov 27 00:25:58 2024 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2048.outbound.protection.outlook.com [40.107.22.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E9F7199EA2; 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charset="utf-8" Since dw_pcie_get_resources() gets the dbi2 and iATU base addresses from DT, remove the code from imx6 driver that does the same. Upsteam dts's have not enabled EP function. So no function broken for old upsteam's dtb. Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pci-imx6.c | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index f7e928e0a018..81f1f68ccc14 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1114,7 +1114,6 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, struct platform_device *pdev) { int ret; - unsigned int pcie_dbi2_offset; struct dw_pcie_ep *ep; struct dw_pcie *pci =3D imx_pcie->pci; struct dw_pcie_rp *pp =3D &pci->pp; @@ -1124,28 +1123,6 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, ep =3D &pci->ep; ep->ops =3D &pcie_ep_ops; =20 - switch (imx_pcie->drvdata->variant) { - case IMX8MQ_EP: - case IMX8MM_EP: - case IMX8MP_EP: - pcie_dbi2_offset =3D SZ_1M; - break; - default: - pcie_dbi2_offset =3D SZ_4K; - break; - } - - pci->dbi_base2 =3D pci->dbi_base + pcie_dbi2_offset; - - /* - * FIXME: Ideally, dbi2 base address should come from DT. But since only = IMX95 is defining - * "dbi2" in DT, "dbi_base2" is set to NULL here for that platform alone = so that the DWC - * core code can fetch that from DT. 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charset="utf-8" i.MX7D only has one PCIe controller, so controller_id should always be 0. The previous code is incorrect although yielding the correct result. Fix by removing IMX7D from the switch case branch. Fixes: 2d8ed461dbc9 ("PCI: imx6: Add support for i.MX8MQ") Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 81f1f68ccc14..3538440601a7 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1367,7 +1367,6 @@ static int imx_pcie_probe(struct platform_device *pde= v) switch (imx_pcie->drvdata->variant) { case IMX8MQ: case IMX8MQ_EP: - case IMX7D: if (dbi_base->start =3D=3D IMX8MQ_PCIE2_BASE_ADDR) imx_pcie->controller_id =3D 1; break; --=20 2.37.1 From nobody Wed Nov 27 00:25:58 2024 Received: from PA4PR04CU001.outbound.protection.outlook.com (mail-francecentralazon11013041.outbound.protection.outlook.com [40.107.162.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAF131AF4EE; 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charset="utf-8" Since the apps_reset is asserted in imx_pcie_assert_core_reset(), it should be deasserted in imx_pcie_deassert_core_reset(). Fixes: 9b3fe6796d7c ("PCI: imx6: Add code to support i.MX7D") Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 3538440601a7..413db182ce9f 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -776,6 +776,7 @@ static void imx_pcie_assert_core_reset(struct imx_pcie = *imx_pcie) static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) { reset_control_deassert(imx_pcie->pciephy_reset); + reset_control_deassert(imx_pcie->apps_reset); =20 if (imx_pcie->drvdata->core_reset) imx_pcie->drvdata->core_reset(imx_pcie, false); --=20 2.37.1 From nobody Wed Nov 27 00:25:58 2024 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11011060.outbound.protection.outlook.com [52.101.70.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 989441B2192; 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charset="utf-8" Ensure the *_enable_ref_clk() function is symmetric by addressing missing disable parts on some platforms. Fixes: d0a75c791f98 ("PCI: imx6: Factor out ref clock disable to match enab= le") Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 413db182ce9f..ab2c97a8c327 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -599,10 +599,9 @@ static int imx_pcie_attach_pd(struct device *dev) =20 static int imx6sx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enab= le) { - if (enable) - regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN); - + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6SX_GPR12_PCIE_TEST_POWERDOWN, + enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN); return 0; } =20 @@ -631,19 +630,20 @@ static int imx8mm_pcie_enable_ref_clk(struct imx_pcie= *imx_pcie, bool enable) { int offset =3D imx_pcie_grp_offset(imx_pcie); =20 - if (enable) { - regmap_clear_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_= OVERRIDE); - regmap_set_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OV= ERRIDE_EN); - } - + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, + IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, + enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE); + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, + IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, + enable ? 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charset="utf-8" This function essentially duplicates imx7d_pcie_enable_ref_clk(). So remove it. Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index ab2c97a8c327..743a71789d17 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -394,13 +394,6 @@ static int imx8mq_pcie_init_phy(struct imx_pcie *imx_p= cie) return 0; } =20 -static int imx7d_pcie_init_phy(struct imx_pcie *imx_pcie) -{ - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_P= HY_REFCLK_SEL, 0); - - return 0; -} - static int imx_pcie_init_phy(struct imx_pcie *imx_pcie) { regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, @@ -1554,7 +1547,6 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .clks_cnt =3D ARRAY_SIZE(imx6q_clks), .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, - .init_phy =3D imx7d_pcie_init_phy, .enable_ref_clk =3D imx7d_pcie_enable_ref_clk, .core_reset =3D imx7d_pcie_core_reset, }, --=20 2.37.1 From nobody Wed Nov 27 00:25:58 2024 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11011004.outbound.protection.outlook.com [52.101.70.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C44E11B532F; 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charset="utf-8" From: Frank Li Call common dwc suspend/resume function. Use dwc common iATU method to send out PME_TURN_OFF message. In Old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD bit in iATU Ctrl2 register is reserved. So the generic DWC implementation of sending the PME_Turn_Off message using a dummy MMIO write cannot be used. Use previouse method to kick off PME_TURN_OFF MSG for these platforms. SRC(System Reset Control) interface is used to toggle 'turnoff_reset' to send PME_TURN_OFF and since the DWC implementation is used, it is not needed now. Replace the imx_pcie_stop_link() and imx_pcie_host_exit() by dw_pcie_suspend_noirq() in imx_pcie_suspend_noirq(). Since dw_pcie_suspend_noirq() already does these, see below call stack: dw_pcie_suspend_noirq() dw_pcie_stop_link(); imx_pcie_stop_link(); pci->pp.ops->deinit(); imx_pcie_host_exit(); Replace the imx_pcie_host_init(), dw_pcie_setup_rc() and imx_pcie_start_link() by dw_pcie_resume_noirq() in imx_pcie_resume_noirq(). Since dw_pcie_resume_noirq() already does these, see below call stack: dw_pcie_resume_noirq() pci->pp.ops->init(); imx_pcie_host_init(); dw_pcie_setup_rc(); dw_pcie_start_link(); imx_pcie_start_link(); Signed-off-by: Frank Li Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 96 ++++++++++----------------- 1 file changed, 35 insertions(+), 61 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 743a71789d17..87dac4ac9d10 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -33,6 +33,7 @@ #include #include =20 +#include "../../pci.h" #include "pcie-designware.h" =20 #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) @@ -112,19 +113,18 @@ struct imx_pcie_drvdata { int (*init_phy)(struct imx_pcie *pcie); int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable); int (*core_reset)(struct imx_pcie *pcie, bool assert); + const struct dw_pcie_host_ops *ops; }; =20 struct imx_pcie { struct dw_pcie *pci; struct gpio_desc *reset_gpiod; - bool link_is_up; struct clk_bulk_data clks[IMX_PCIE_MAX_CLKS]; struct regmap *iomuxc_gpr; u16 msi_ctrl; u32 controller_id; struct reset_control *pciephy_reset; struct reset_control *apps_reset; - struct reset_control *turnoff_reset; u32 tx_deemph_gen1; u32 tx_deemph_gen2_3p5db; u32 tx_deemph_gen2_6db; @@ -903,13 +903,11 @@ static int imx_pcie_start_link(struct dw_pcie *pci) dev_info(dev, "Link: Only Gen1 is enabled\n"); } =20 - imx_pcie->link_is_up =3D true; tmp =3D dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); return 0; =20 err_reset_phy: - imx_pcie->link_is_up =3D false; dev_dbg(dev, "PHY DEBUG_R0=3D0x%08x DEBUG_R1=3D0x%08x\n", dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); @@ -1014,9 +1012,31 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) regulator_disable(imx_pcie->vpcie); } =20 +/* + * In Old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD bit in iATU Ctrl2 + * register is reserved. So the generic DWC implementation of sending the + * PME_Turn_Off message using a dummy MMIO write cannot be used. + */ +static void imx_pcie_pme_turn_off(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct imx_pcie *imx_pcie =3D to_imx_pcie(pci); + + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_= TURN_OFF); + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_P= M_TURN_OFF); + + usleep_range(PCIE_PME_TO_L2_TIMEOUT_US/10, PCIE_PME_TO_L2_TIMEOUT_US); +} + static const struct dw_pcie_host_ops imx_pcie_host_ops =3D { .init =3D imx_pcie_host_init, .deinit =3D imx_pcie_host_exit, + .pme_turn_off =3D imx_pcie_pme_turn_off, +}; + +static const struct dw_pcie_host_ops imx_pcie_host_dw_pme_ops =3D { + .init =3D imx_pcie_host_init, + .deinit =3D imx_pcie_host_exit, }; =20 static const struct dw_pcie_ops dw_pcie_ops =3D { @@ -1143,43 +1163,6 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, return 0; } =20 -static void imx_pcie_pm_turnoff(struct imx_pcie *imx_pcie) -{ - struct device *dev =3D imx_pcie->pci->dev; - - /* Some variants have a turnoff reset in DT */ - if (imx_pcie->turnoff_reset) { - reset_control_assert(imx_pcie->turnoff_reset); - reset_control_deassert(imx_pcie->turnoff_reset); - goto pm_turnoff_sleep; - } - - /* Others poke directly at IOMUXC registers */ - switch (imx_pcie->drvdata->variant) { - case IMX6SX: - case IMX6QP: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_PM_TURN_OFF, - IMX6SX_GPR12_PCIE_PM_TURN_OFF); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); - break; - default: - dev_err(dev, "PME_Turn_Off not implemented\n"); - return; - } - - /* - * Components with an upstream port must respond to - * PME_Turn_Off with PME_TO_Ack but we can't check. - * - * The standard recommends a 1-10ms timeout after which to - * proceed anyway as if acks were received. - */ -pm_turnoff_sleep: - usleep_range(1000, 10000); -} - static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save) { u8 offset; @@ -1203,7 +1186,6 @@ static void imx_pcie_msi_save_restore(struct imx_pcie= *imx_pcie, bool save) static int imx_pcie_suspend_noirq(struct device *dev) { struct imx_pcie *imx_pcie =3D dev_get_drvdata(dev); - struct dw_pcie_rp *pp =3D &imx_pcie->pci->pp; =20 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; @@ -1218,9 +1200,7 @@ static int imx_pcie_suspend_noirq(struct device *dev) imx_pcie_assert_core_reset(imx_pcie); imx_pcie->drvdata->enable_ref_clk(imx_pcie, false); } else { - imx_pcie_pm_turnoff(imx_pcie); - imx_pcie_stop_link(imx_pcie->pci); - imx_pcie_host_exit(pp); + return dw_pcie_suspend_noirq(imx_pcie->pci); } =20 return 0; @@ -1230,7 +1210,6 @@ static int imx_pcie_resume_noirq(struct device *dev) { int ret; struct imx_pcie *imx_pcie =3D dev_get_drvdata(dev); - struct dw_pcie_rp *pp =3D &imx_pcie->pci->pp; =20 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; @@ -1250,17 +1229,12 @@ static int imx_pcie_resume_noirq(struct device *dev) ret =3D dw_pcie_setup_rc(&imx_pcie->pci->pp); if (ret) return ret; - imx_pcie_msi_save_restore(imx_pcie, false); } else { - ret =3D imx_pcie_host_init(pp); + ret =3D dw_pcie_resume_noirq(imx_pcie->pci); if (ret) return ret; - imx_pcie_msi_save_restore(imx_pcie, false); - dw_pcie_setup_rc(pp); - - if (imx_pcie->link_is_up) - imx_pcie_start_link(imx_pcie->pci); } + imx_pcie_msi_save_restore(imx_pcie, false); =20 return 0; } @@ -1291,11 +1265,15 @@ static int imx_pcie_probe(struct platform_device *p= dev) =20 pci->dev =3D dev; pci->ops =3D &dw_pcie_ops; - pci->pp.ops =3D &imx_pcie_host_ops; =20 imx_pcie->pci =3D pci; imx_pcie->drvdata =3D of_device_get_match_data(dev); =20 + if (imx_pcie->drvdata->ops) + pci->pp.ops =3D imx_pcie->drvdata->ops; + else + pci->pp.ops =3D &imx_pcie_host_dw_pme_ops; + /* Find the PHY if one is defined, only imx7d uses it */ np =3D of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); if (np) { @@ -1368,13 +1346,6 @@ static int imx_pcie_probe(struct platform_device *pd= ev) break; } =20 - /* Grab turnoff reset */ - imx_pcie->turnoff_reset =3D devm_reset_control_get_optional_exclusive(dev= , "turnoff"); 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charset="utf-8" Add iMX8MQ i.MX8Q and i.MX95 PCIe suspend/resume support. Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 87dac4ac9d10..852b34572bb8 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1527,7 +1527,8 @@ static const struct imx_pcie_drvdata drvdata[] =3D { [IMX8MQ] =3D { .variant =3D IMX8MQ, .flags =3D IMX_PCIE_FLAG_HAS_APP_RESET | - IMX_PCIE_FLAG_HAS_PHY_RESET, + IMX_PCIE_FLAG_HAS_PHY_RESET | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr =3D "fsl,imx8mq-iomuxc-gpr", .clk_names =3D imx8mq_clks, .clks_cnt =3D ARRAY_SIZE(imx8mq_clks), @@ -1564,13 +1565,15 @@ static const struct imx_pcie_drvdata drvdata[] =3D { }, [IMX8Q] =3D { .variant =3D IMX8Q, - .flags =3D IMX_PCIE_FLAG_HAS_PHYDRV, + .flags =3D IMX_PCIE_FLAG_HAS_PHYDRV | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .clk_names =3D imx8q_clks, .clks_cnt =3D ARRAY_SIZE(imx8q_clks), }, [IMX95] =3D { .variant =3D IMX95, - .flags =3D IMX_PCIE_FLAG_HAS_SERDES, + .flags =3D IMX_PCIE_FLAG_HAS_SERDES | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .clk_names =3D imx95_clks, .clks_cnt =3D ARRAY_SIZE(imx95_clks), .clks_optional_cnt =3D 1, --=20 2.37.1 From nobody Wed Nov 27 00:25:58 2024 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11011012.outbound.protection.outlook.com [52.101.70.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F7071ABED8; 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charset="utf-8" Add ref clock for i.MX95 PCIe here, when the internal PLL is used as PCIe reference clock. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95.dtsi | 25 ++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts= /freescale/imx95.dtsi index 03661e76550f..9951d2c84799 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -236,6 +236,13 @@ clk_ext1: clock-ext1 { clock-output-names =3D "clk_ext1"; }; =20 + clk_sys100m: clock-sys100m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1000000>; + clock-output-names =3D "clk_sys100m"; + }; + sai1_mclk: clock-sai-mclk1 { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -1473,6 +1480,14 @@ smmu: iommu@490d0000 { }; }; =20 + hsio_blk_ctl: syscon@4c0100c0 { + compatible =3D "nxp,imx95-hsio-blk-ctl", "syscon"; + reg =3D <0x0 0x4c0100c0 0x0 0x4>; + #clock-cells =3D <1>; + clocks =3D <&clk_sys100m>; + power-domains =3D <&scmi_devpd IMX95_PD_HSIO_TOP>; + }; + pcie0: pcie@4c300000 { compatible =3D "fsl,imx95-pcie"; reg =3D <0 0x4c300000 0 0x10000>, @@ -1500,8 +1515,9 @@ pcie0: pcie@4c300000 { clocks =3D <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; assigned-clocks =3D<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; @@ -1567,8 +1583,9 @@ pcie1: pcie@4c380000 { clocks =3D <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names =3D "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; assigned-clocks =3D<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; --=20 2.37.1