From nobody Mon Nov 25 22:34:47 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AF7E1B85C2; Mon, 25 Nov 2024 17:59:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732557542; cv=none; b=VxnbsKI6EM3dFZPYx6JbjH+4bxxXrkMkMdXHHry4TB16RnpoouupsvQOMKfENbBtuL0IwXQTDdD8U4WN6uJJNWhG0dHka1BTB6QCIgF+4SZ3b/+2mZPm8QRg7YAwDu+bxvrfStO8aBjE1UN5l9b/F6MaRLU19Nfm1yh0o59INQ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732557542; c=relaxed/simple; bh=xWSs+CCHo2cnkHp+YQIYQ9pyFy661acsmyXS6RC2uDQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VqBIcwauQGUcXwV+Gvuy3B8eR9+4HRzW6P9OB5IJRBhk/T3BgWsJVZHaU2eW46YoeNPJ6VQvzKn6Xo/61ZPBG1Zwrfj6/NOxeSb6L1MYDmv/9qDPGxh7GE9d5B6LuCnMp2iGmDWkBBckBcg7r3vOOgolp831yxHExAh+z60kZi8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=mOS9iQVK; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="mOS9iQVK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1732557540; x=1764093540; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xWSs+CCHo2cnkHp+YQIYQ9pyFy661acsmyXS6RC2uDQ=; b=mOS9iQVKBr6x6XAAihtsG9J262ZY6qgazGKHRdzYfeTu8y7Gi0dPupUF 1RiCtfnGM9Nm6expTO9r93X8OWriIxwF7YJJ0CBUeAJaYp3AWBKfsRexi bsPCNjGwXtQZ+7TXBspRXjBgHkfxY6sdmq1v9iBgHVAILqweKuFoJ9VcS p7JnIKVo2hfKpyES8TNMsqmsiGQJELB5/UEc5yVEaC1YWdyXl3syOB9rR WziHZpQQm6R5EMWRGyCJRVmmlWwXbSc57HosoVj7QHZWXMUEGdnJATuRK TfGPL3OMKD4bCCd2BQyxPhtUClXmfStisvDTv/j14c88JB8/QRcQqKGEQ A==; X-CSE-ConnectionGUID: QcIy3zy5RLCJ7zVSqoxwVg== X-CSE-MsgGUID: dGxu753KRwqgAnyAephq7g== X-IronPort-AV: E=Sophos;i="6.12,183,1728975600"; d="scan'208";a="38361996" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 25 Nov 2024 10:58:51 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 25 Nov 2024 10:58:38 -0700 Received: from valentina.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 25 Nov 2024 10:58:35 -0700 From: Valentina Fernandez To: , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v4 1/4] riscv: sbi: vendorid_list: Add Microchip Technology to the vendor list Date: Mon, 25 Nov 2024 17:58:15 +0000 Message-ID: <20241125175818.213108-2-valentina.fernandezalanis@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241125175818.213108-1-valentina.fernandezalanis@microchip.com> References: <20241125175818.213108-1-valentina.fernandezalanis@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Microchip Technology to the RISC-V vendor list. Signed-off-by: Valentina Fernandez --- arch/riscv/include/asm/vendorid_list.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/as= m/vendorid_list.h index 2f2bb0c84f9a..a5150cdf34d8 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -6,6 +6,7 @@ #define ASM_VENDOR_LIST_H =20 #define ANDES_VENDOR_ID 0x31e +#define MICROCHIP_VENDOR_ID 0x029 #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 =20 --=20 2.34.1 From nobody Mon Nov 25 22:34:47 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 048561B87C1; Mon, 25 Nov 2024 17:59:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732557542; cv=none; b=DfDBcD4WwC0fMM4cj2QvLXWIYP77X8qTKm9T126493vc81l60f5kMW+ordy0HkZuRORc9vPOlaoAatJfRtQc1vj8TLSFoO+MuNYC9DT9Uj+UlH6aPmZ8PiSYkpfIpmpbDElDAhrgpaWyXBAeDhY8PXBPtQT9zE1eSJnEJiaT2gk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732557542; c=relaxed/simple; bh=z6u/32qG+4VOxWxyQMcxtikghEw3g/GuPpIgKl24hiQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=E/3+a2f8wRfWVs9BZipHO0y3DcU5Ox+xgwUbGl/oeyrGsJicNcHn1cmM6tm22UG1YxOiIuITumbRQCk6rbVE/zBKUxsvXHvwriRozYbR6yRYfzLGnnppIhcP7PhkLNo8xpfFSGdvBus3XJwX2OyHMbsGdeToFpGXKN1BPhDg4nk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=hqjpvfC0; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="hqjpvfC0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1732557541; x=1764093541; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=z6u/32qG+4VOxWxyQMcxtikghEw3g/GuPpIgKl24hiQ=; b=hqjpvfC0/HIsXftcQvowVlJ8wzR8JBoYHHfxB2KRKTT3Gz8xL7qY4op1 GrblNpdrNkXH7exxya7zEDAZnKZnkTXSFOrLDeE9tCLVcr6BCqaB4yZx7 t4sBw68Al9xDrHOMd9SqbxTpWCOGREvTH44NXpWSGcJDXQUPBo89GwcFf bywDZTmf0kjWz79eY1iEFr2+6wS4VDdBKwJO4vBCVURWcsZrNLul6eIh/ s+msubw14UtCxmtgkpzRPqzcEI3GDG6NM3CAHbx8bHWVoyNe2WKvfBEdN yZ5GwJK5VVvtWsRNz9EYgWrHw6H0gYSV4dIMNWn55L4ZfIEQdii+PhBsN Q==; X-CSE-ConnectionGUID: QcIy3zy5RLCJ7zVSqoxwVg== X-CSE-MsgGUID: 79PrQIPUQpyVSrn+vDhdig== X-IronPort-AV: E=Sophos;i="6.12,183,1728975600"; d="scan'208";a="38361997" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 25 Nov 2024 10:58:52 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 25 Nov 2024 10:58:42 -0700 Received: from valentina.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 25 Nov 2024 10:58:39 -0700 From: Valentina Fernandez To: , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v4 2/4] riscv: export __cpuid_to_hartid_map Date: Mon, 25 Nov 2024 17:58:16 +0000 Message-ID: <20241125175818.213108-3-valentina.fernandezalanis@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241125175818.213108-1-valentina.fernandezalanis@microchip.com> References: <20241125175818.213108-1-valentina.fernandezalanis@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" EXPORT_SYMBOL_GPL() is missing for __cpuid_to_hartid_map array. Export this symbol to allow drivers compiled as modules to use cpuid_to_hartid_map(). Signed-off-by: Valentina Fernandez --- arch/riscv/kernel/smp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index c180a647a30e..d58b5e751286 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -43,6 +43,7 @@ enum ipi_message_type { unsigned long __cpuid_to_hartid_map[NR_CPUS] __ro_after_init =3D { [0 ... NR_CPUS-1] =3D INVALID_HARTID }; +EXPORT_SYMBOL_GPL(__cpuid_to_hartid_map); =20 void __init smp_setup_processor_id(void) { --=20 2.34.1 From nobody Mon Nov 25 22:34:47 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32ACF1B87D9; Mon, 25 Nov 2024 17:59:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732557543; cv=none; b=GpiyNwZRC6We8wlHehpwSag2J1xQO9TndT/PzghdUMUebgTsBzCuuczxQ4kd6nRR+Tt3RcGaZL1/UwvQ8sRtP0lAHmRTne+Wt4pZTqfImyNZBK2CM4yt5oHtCQXUPQmexTA7BP3teOE2GU67YYc77uMXnuht+lZdMX3OOgPoI18= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732557543; c=relaxed/simple; bh=U+npF1NvJtoJ4T6hVxDwsCJ5YF+JSUTcWrivx8R4two=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fZp9ZaGOnHwF3Lsr5uLl+SbXFxjX2gvrG1Y0Frtr4UjT+sR/E6qLuMRMMCC562xL+QiCT0CvjzwBk80CRiMSvXMumDqqHhuitKI18wUcULZ0l1AxYzhqu7XTqUDRNQU8Ayfiu7zi/BxayregIHQC38kMVz8R28+eeF8zoL+DhAY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=wdHSEicu; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="wdHSEicu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1732557542; x=1764093542; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=U+npF1NvJtoJ4T6hVxDwsCJ5YF+JSUTcWrivx8R4two=; b=wdHSEicumcfKJZ3gbdqO8p0n4FrpvE42HklrLI/p3U0df2EoEmaPFkxc pfSzvGern68pz062BQbwLz2MTZ3fj6NxraUzA8w/PT+7AahZQuQYyZPpT v4SYDgqZoL88XTf8HTPK+bIFBvaYE0xNHRT7tUKfyKbKDbtSk/FYAVAsJ 27plA2OSbMXqmZ/ms2AMejrJXJ3W3rSNt3QBTEXrVwQ8LFU1SDAAyiVoY q7/AgAxG5TLmPQVtFYDDiEfJryEpCpbX39b2OAxIBzsi7DRAads9BY/P+ 4aayxdTDjZ2Lf8okQR3tg96hb1O0j2zTz9Ma1uSDg5ivdGNR3FqeO/0XW w==; X-CSE-ConnectionGUID: QcIy3zy5RLCJ7zVSqoxwVg== X-CSE-MsgGUID: rlNRxlbmRjCAsP7JRKUTyw== X-IronPort-AV: E=Sophos;i="6.12,183,1728975600"; d="scan'208";a="38361999" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 25 Nov 2024 10:58:52 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 25 Nov 2024 10:58:45 -0700 Received: from valentina.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 25 Nov 2024 10:58:42 -0700 From: Valentina Fernandez To: , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v4 3/4] dt-bindings: mailbox: add binding for Microchip IPC mailbox controller Date: Mon, 25 Nov 2024 17:58:17 +0000 Message-ID: <20241125175818.213108-4-valentina.fernandezalanis@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241125175818.213108-1-valentina.fernandezalanis@microchip.com> References: <20241125175818.213108-1-valentina.fernandezalanis@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add a dt-binding for the Microchip Inter-Processor Communication (IPC) mailbox controller. Signed-off-by: Valentina Fernandez --- .../bindings/mailbox/microchip,sbi-ipc.yaml | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,sbi= -ipc.yaml diff --git a/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.ya= ml b/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml new file mode 100644 index 000000000000..b69af85ec608 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Inter-processor communication (IPC) mailbox controller + +maintainers: + - Valentina Fernandez + +description: + The Microchip Inter-processor Communication (IPC) facilitates + message passing between processors using an interrupt signaling + mechanism. + +properties: + compatible: + oneOf: + - description: + Intended for use by software running in supervisor privileged + mode (s-mode). This SBI interface is compatible with the Mi-V + Inter-hart Communication (IHC) IP. + const: microchip,sbi-ipc + + - description: + Intended for use by the SBI implementation in machine mode + (m-mode), this compatible string is for the MIV_IHC Soft-IP. + const: microchip,miv-ihc-rtl-v2 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 5 + + interrupt-names: + minItems: 1 + maxItems: 5 + items: + pattern: "^hart-[0-5]+$" + + "#mbox-cells": + description: > + For "microchip,sbi-ipc", the cell represents the global "logical" + channel IDs. The meaning of channel IDs are platform firmware depend= ent. + + For "microchip,miv-ihc-rtl-v2", the cell represents the physical + channel and does not vary based on the platform firmware. + const: 1 + + microchip,ihc-chan-disabled-mask: + description: > + Represents the enable/disable state of the bi-directional IHC + channels within the MIV-IHC IP configuration. + + A bit set to '1' indicates that the corresponding channel is disable= d, + and any read or write operations to that channel will return zero. + + A bit set to '0' indicates that the corresponding channel is enabled + and will be accessible through its dedicated address range registers. + + The actual enable/disable state of each channel is determined by the + IP block=E2=80=99s configuration. + $ref: /schemas/types.yaml#/definitions/uint16 + maximum: 0x7fff + default: 0 + +required: + - compatible + - interrupts + - interrupt-names + - "#mbox-cells" + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: microchip,sbi-ipc + then: + properties: + reg: false + microchip,ihc-chan-disabled-mask: false + else: + required: + - reg + - microchip,ihc-chan-disabled-mask + +examples: + - | + mailbox { + compatible =3D "microchip,sbi-ipc"; + interrupt-parent =3D <&plic>; + interrupts =3D <180>, <179>, <178>; + interrupt-names =3D "hart-1", "hart-2", "hart-3"; + #mbox-cells =3D <1>; + }; + - | + mailbox@50000000 { + compatible =3D "microchip,miv-ihc-rtl-v2"; + microchip,ihc-chan-disabled-mask =3D /bits/ 16 <0>; + reg =3D <0x50000000 0x1C000>; + interrupt-parent =3D <&plic>; + interrupts =3D <180>, <179>, <178>; + interrupt-names =3D "hart-1", "hart-2", "hart-3"; + #mbox-cells =3D <1>; + }; --=20 2.34.1 From nobody Mon Nov 25 22:34:47 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 950C11B87E5; Mon, 25 Nov 2024 17:59:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732557544; cv=none; b=F8QsnsE3+LIuD9sDR7VolvtIGAC7AYDUe3PPzKg/9a1/KOKaLhDcUr1BCs78p/G3qSdjYlHujKCC6QRcoaUWDXK8rLrz8g/b14d6VaAsIfafzFbJ25BkJkA+P61/E2m2PW6PMDOVl6wdzaXIx2X3G7ujrVWXzkZuY9nEKE6KOw0= ARC-Message-Signature: i=1; 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Mon, 25 Nov 2024 10:58:48 -0700 Received: from valentina.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 25 Nov 2024 10:58:45 -0700 From: Valentina Fernandez To: , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v4 4/4] mailbox: add Microchip IPC support Date: Mon, 25 Nov 2024 17:58:18 +0000 Message-ID: <20241125175818.213108-5-valentina.fernandezalanis@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241125175818.213108-1-valentina.fernandezalanis@microchip.com> References: <20241125175818.213108-1-valentina.fernandezalanis@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a mailbox controller driver for the Microchip Inter-processor Communication (IPC), which is used to send and receive data between processors. The driver uses the RISC-V Supervisor Binary Interface (SBI) to communicate with software running in machine mode (M-mode) to access the IPC hardware block. Additional details on the Microchip vendor extension and the IPC function IDs described in the driver can be found in the following documentation: https://github.com/linux4microchip/microchip-sbi-ecall-extension This SBI interface in this driver is compatible with the Mi-V Inter-hart Communication (IHC) IP. Transmitting and receiving data through the mailbox framework is done through struct mchp_ipc_msg. Signed-off-by: Valentina Fernandez --- drivers/mailbox/Kconfig | 13 + drivers/mailbox/Makefile | 2 + drivers/mailbox/mailbox-mchp-ipc-sbi.c | 504 +++++++++++++++++++++++++ include/linux/mailbox/mchp-ipc.h | 33 ++ 4 files changed, 552 insertions(+) create mode 100644 drivers/mailbox/mailbox-mchp-ipc-sbi.c create mode 100644 include/linux/mailbox/mchp-ipc.h diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 6fb995778636..a61b3b0c5da3 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -177,6 +177,19 @@ config POLARFIRE_SOC_MAILBOX =20 If unsure, say N. =20 +config MCHP_SBI_IPC_MBOX + tristate "Microchip Inter-processor Communication (IPC) SBI driver" + depends on RISCV_SBI || COMPILE_TEST + depends on ARCH_MICROCHIP + help + Mailbox implementation for Microchip devices with an + Inter-process communication (IPC) controller. + + To compile this driver as a module, choose M here. the + module will be called mailbox-mchp-ipc-sbi. + + If unsure, say N. + config QCOM_APCS_IPC tristate "Qualcomm APCS IPC driver" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 3c3c27d54c13..a78d1948e331 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -45,6 +45,8 @@ obj-$(CONFIG_BCM_FLEXRM_MBOX) +=3D bcm-flexrm-mailbox.o =20 obj-$(CONFIG_POLARFIRE_SOC_MAILBOX) +=3D mailbox-mpfs.o =20 +obj-$(CONFIG_MCHP_SBI_IPC_MBOX) +=3D mailbox-mchp-ipc-sbi.o + obj-$(CONFIG_QCOM_APCS_IPC) +=3D qcom-apcs-ipc-mailbox.o =20 obj-$(CONFIG_TEGRA_HSP_MBOX) +=3D tegra-hsp.o diff --git a/drivers/mailbox/mailbox-mchp-ipc-sbi.c b/drivers/mailbox/mailb= ox-mchp-ipc-sbi.c new file mode 100644 index 000000000000..a6e52009a424 --- /dev/null +++ b/drivers/mailbox/mailbox-mchp-ipc-sbi.c @@ -0,0 +1,504 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip Inter-Processor communication (IPC) driver + * + * Copyright (c) 2021 - 2024 Microchip Technology Inc. All rights reserved. + * + * Author: Valentina Fernandez + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IRQ_STATUS_BITS 12 +#define NUM_CHANS_PER_CLUSTER 5 +#define IPC_DMA_BIT_MASK 32 +#define SBI_EXT_MICROCHIP_TECHNOLOGY (SBI_EXT_VENDOR_START | \ + MICROCHIP_VENDOR_ID) + +enum { + SBI_EXT_IPC_PROBE =3D 0x100, + SBI_EXT_IPC_CH_INIT, + SBI_EXT_IPC_SEND, + SBI_EXT_IPC_RECEIVE, + SBI_EXT_IPC_STATUS, +}; + +enum ipc_hw { + MIV_IHC, +}; + +/** + * struct mchp_ipc_mbox_info - IPC probe message format + * + * @hw_type: IPC implementation available in the hardware + * @num_channels: number of IPC channels available in the hardware + * + * Used to retrieve information on the IPC implementation + * using the SBI_EXT_IPC_PROBE SBI function id. + */ +struct mchp_ipc_mbox_info { + enum ipc_hw hw_type; + u8 num_channels; +}; + +/** + * struct mchp_ipc_init - IPC channel init message format + * + * @max_msg_size: maxmimum message size in bytes of a given channel + * + * struct used by the SBI_EXT_IPC_CH_INIT SBI function id to get + * the max message size in bytes of the initialized channel. + */ +struct mchp_ipc_init { + u16 max_msg_size; +}; + +/** + * struct mchp_ipc_status - IPC status message format + * + * @status: interrupt status for all channels associated to a cluster + * @cluster: specifies the cluster instance that originated an irq + * + * struct used by the SBI_EXT_IPC_STATUS SBI function id to get + * the message present and message clear interrupt status for all the + * channels associated to a cluster. + */ +struct mchp_ipc_status { + u32 status; + u8 cluster; +}; + +/** + * struct mchp_ipc_sbi_msg - IPC SBI payload message + * + * @buf_addr: physical address where the received data should be copied to + * @size: maximum size(in bytes) that can be stored in the buffer pointed = to by `buf` + * @irq_type: mask representing the irq types that triggered an irq + * + * struct used by the SBI_EXT_IPC_SEND/SBI_EXT_IPC_RECEIVE SBI function + * ids to send/receive a message from an associated processor using + * the IPC. + */ +struct mchp_ipc_sbi_msg { + u64 buf_addr; + u16 size; + u8 irq_type; +}; + +struct mchp_ipc_cluster_cfg { + void *buf_base; + phys_addr_t buf_base_addr; + int irq; +}; + +struct mchp_ipc_sbi_mbox { + struct device *dev; + struct mbox_chan *chans; + struct mchp_ipc_cluster_cfg *cluster_cfg; + void *buf_base; + unsigned long buf_base_addr; + struct mbox_controller controller; + enum ipc_hw hw_type; +}; + +static int mchp_ipc_sbi_chan_send(u32 command, u32 channel, unsigned long = address) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_MICROCHIP_TECHNOLOGY, command, channel, + address, 0, 0, 0, 0); + + if (ret.error) + return sbi_err_map_linux_errno(ret.error); + else + return ret.value; +} + +static int mchp_ipc_sbi_send(u32 command, unsigned long address) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_MICROCHIP_TECHNOLOGY, command, address, + 0, 0, 0, 0, 0); + + if (ret.error) + return sbi_err_map_linux_errno(ret.error); + else + return ret.value; +} + +static struct mchp_ipc_sbi_mbox *to_mchp_ipc_mbox(struct mbox_controller *= mbox) +{ + return container_of(mbox, struct mchp_ipc_sbi_mbox, controller); +} + +static inline void mchp_ipc_prepare_receive_req(struct mbox_chan *chan) +{ + struct mchp_ipc_sbi_chan *chan_info =3D (struct mchp_ipc_sbi_chan *)chan-= >con_priv; + struct mchp_ipc_sbi_msg request; + + request.buf_addr =3D chan_info->msg_buf_rx_addr; + request.size =3D chan_info->max_msg_size; + memcpy(chan_info->buf_base_rx, &request, sizeof(struct mchp_ipc_sbi_msg)); +} + +static inline void mchp_ipc_process_received_data(struct mbox_chan *chan, + struct mchp_ipc_msg *ipc_msg) +{ + struct mchp_ipc_sbi_chan *chan_info =3D (struct mchp_ipc_sbi_chan *)chan-= >con_priv; + struct mchp_ipc_sbi_msg sbi_msg; + + memcpy(&sbi_msg, chan_info->buf_base_rx, sizeof(struct mchp_ipc_sbi_msg)); + ipc_msg->buf =3D (u32 *)chan_info->msg_buf_rx; + ipc_msg->size =3D sbi_msg.size; +} + +static irqreturn_t mchp_ipc_cluster_aggr_isr(int irq, void *data) +{ + struct mbox_chan *chan; + struct mchp_ipc_sbi_chan *chan_info; + struct mchp_ipc_sbi_mbox *ipc =3D (struct mchp_ipc_sbi_mbox *)data; + struct mchp_ipc_msg ipc_msg; + struct mchp_ipc_status status_msg; + int ret; + unsigned long hartid; + u32 i, chan_index, chan_id; + + /* Find out the hart that originated the irq */ + for_each_online_cpu(i) { + hartid =3D cpuid_to_hartid_map(i); + if (irq =3D=3D ipc->cluster_cfg[hartid].irq) + break; + } + + status_msg.cluster =3D hartid; + memcpy(ipc->cluster_cfg[hartid].buf_base, &status_msg, sizeof(struct mchp= _ipc_status)); + + ret =3D mchp_ipc_sbi_send(SBI_EXT_IPC_STATUS, ipc->cluster_cfg[hartid].bu= f_base_addr); + if (ret < 0) { + dev_err_ratelimited(ipc->dev, "could not get IHC irq status ret=3D%d\n",= ret); + return IRQ_HANDLED; + } + + memcpy(&status_msg, ipc->cluster_cfg[hartid].buf_base, sizeof(struct mchp= _ipc_status)); + + /* + * Iterate over each bit set in the IHC interrupt status register (IRQ_ST= ATUS) to identify + * the channel(s) that have a message to be processed/acknowledged. + * The bits are organized in alternating format, where each pair of bits = represents + * the status of the message present and message clear interrupts for eac= h cluster/hart + * (from hart 0 to hart 5). Each cluster can have up to 5 fixed channels = associated. + */ + + for_each_set_bit(i, (unsigned long *)&status_msg.status, IRQ_STATUS_BITS)= { + /* Find out the destination hart that triggered the interrupt */ + chan_index =3D i / 2; + + /* + * The IP has no loopback channels, so we need to decrement the index wh= en + * the target hart has a greater index than our own + */ + if (chan_index >=3D status_msg.cluster) + chan_index--; + + /* + * Calculate the channel id given the hart and channel index. Channel IDs + * are unique across all clusters of an IPC, and iterate contiguously + * across all clusters. + */ + chan_id =3D status_msg.cluster * (NUM_CHANS_PER_CLUSTER + chan_index); + + chan =3D &ipc->chans[chan_id]; + chan_info =3D (struct mchp_ipc_sbi_chan *)chan->con_priv; + + if (i % 2 =3D=3D 0) { + mchp_ipc_prepare_receive_req(chan); + ret =3D mchp_ipc_sbi_chan_send(SBI_EXT_IPC_RECEIVE, chan_id, + chan_info->buf_base_rx_addr); + if (ret < 0) + continue; + + mchp_ipc_process_received_data(chan, &ipc_msg); + mbox_chan_received_data(&ipc->chans[chan_id], (void *)&ipc_msg); + + } else { + ret =3D mchp_ipc_sbi_chan_send(SBI_EXT_IPC_RECEIVE, chan_id, + chan_info->buf_base_rx_addr); + mbox_chan_txdone(&ipc->chans[chan_id], ret); + } + } + return IRQ_HANDLED; +} + +static int mchp_ipc_send_data(struct mbox_chan *chan, void *data) +{ + struct mchp_ipc_sbi_chan *chan_info =3D (struct mchp_ipc_sbi_chan *)chan-= >con_priv; + const struct mchp_ipc_msg *msg =3D data; + struct mchp_ipc_sbi_msg sbi_payload; + + memcpy(chan_info->msg_buf_tx, msg->buf, msg->size); + sbi_payload.buf_addr =3D chan_info->msg_buf_tx_addr; + sbi_payload.size =3D msg->size; + memcpy(chan_info->buf_base_tx, &sbi_payload, sizeof(sbi_payload)); + + return mchp_ipc_sbi_chan_send(SBI_EXT_IPC_SEND, chan_info->id, chan_info-= >buf_base_tx_addr); +} + +static int mchp_ipc_startup(struct mbox_chan *chan) +{ + struct mchp_ipc_sbi_chan *chan_info =3D (struct mchp_ipc_sbi_chan *)chan-= >con_priv; + struct mchp_ipc_sbi_mbox *ipc =3D to_mchp_ipc_mbox(chan->mbox); + struct mchp_ipc_init ch_init_msg; + int ret; + + /* + * The TX base buffer is used to transmit two types of messages: + * - struct mchp_ipc_init to initialize the channel + * - struct mchp_ipc_sbi_msg to transmit user data/payload + * Ensure the TX buffer size is large enough to accommodate either messag= e type. + */ + size_t max_size =3D max(sizeof(struct mchp_ipc_init), sizeof(struct mchp_= ipc_sbi_msg)); + + chan_info->buf_base_tx =3D kmalloc(max_size, GFP_KERNEL); + if (!chan_info->buf_base_tx) { + ret =3D -ENOMEM; + goto fail; + } + + chan_info->buf_base_tx_addr =3D __pa(chan_info->buf_base_tx); + + chan_info->buf_base_rx =3D kmalloc(max_size, GFP_KERNEL); + if (!chan_info->buf_base_rx) { + ret =3D -ENOMEM; + goto fail_free_buf_base_tx; + } + + chan_info->buf_base_rx_addr =3D __pa(chan_info->buf_base_rx); + + ret =3D mchp_ipc_sbi_chan_send(SBI_EXT_IPC_CH_INIT, chan_info->id, + chan_info->buf_base_tx_addr); + if (ret < 0) { + dev_err(ipc->dev, "channel %u init failed\n", chan_info->id); + goto fail_free_buf_base_rx; + } + + memcpy(&ch_init_msg, chan_info->buf_base_tx, sizeof(struct mchp_ipc_init)= ); + chan_info->max_msg_size =3D ch_init_msg.max_msg_size; + + chan_info->msg_buf_tx =3D kmalloc(chan_info->max_msg_size, GFP_KERNEL); + if (!chan_info->msg_buf_tx) { + ret =3D -ENOMEM; + goto fail_free_buf_base_rx; + } + + chan_info->msg_buf_tx_addr =3D __pa(chan_info->msg_buf_tx); + + chan_info->msg_buf_rx =3D kmalloc(chan_info->max_msg_size, GFP_KERNEL); + if (!chan_info->msg_buf_rx) { + ret =3D -ENOMEM; + goto fail_free_buf_msg_tx; + } + + chan_info->msg_buf_rx_addr =3D __pa(chan_info->msg_buf_rx); + + switch (ipc->hw_type) { + case MIV_IHC: + return 0; + default: + goto fail_free_buf_msg_rx; + } + + if (ret) { + dev_err(ipc->dev, "failed to register interrupt(s)\n"); + goto fail_free_buf_msg_rx; + } + + return ret; + +fail_free_buf_msg_rx: + kfree(chan_info->msg_buf_rx); +fail_free_buf_msg_tx: + kfree(chan_info->msg_buf_tx); +fail_free_buf_base_rx: + kfree(chan_info->buf_base_rx); +fail_free_buf_base_tx: + kfree(chan_info->buf_base_tx); +fail: + return ret; +} + +static void mchp_ipc_shutdown(struct mbox_chan *chan) +{ + struct mchp_ipc_sbi_chan *chan_info =3D (struct mchp_ipc_sbi_chan *)chan-= >con_priv; + + kfree(chan_info->buf_base_tx); + kfree(chan_info->buf_base_rx); + kfree(chan_info->msg_buf_tx); + kfree(chan_info->msg_buf_rx); +} + +static const struct mbox_chan_ops mchp_ipc_ops =3D { + .startup =3D mchp_ipc_startup, + .send_data =3D mchp_ipc_send_data, + .shutdown =3D mchp_ipc_shutdown, +}; + +static struct mbox_chan *mchp_ipc_mbox_xlate(struct mbox_controller *contr= oller, + const struct of_phandle_args *spec) +{ + struct mchp_ipc_sbi_mbox *ipc =3D to_mchp_ipc_mbox(controller); + unsigned int chan_id =3D spec->args[0]; + + if (chan_id >=3D ipc->controller.num_chans) { + dev_err(ipc->dev, "invalid channel id %d\n", chan_id); + return ERR_PTR(-EINVAL); + } + + return &ipc->chans[chan_id]; +} + +static int mchp_ipc_get_cluster_aggr_irq(struct mchp_ipc_sbi_mbox *ipc) +{ + struct platform_device *pdev =3D to_platform_device(ipc->dev); + char *irq_name; + int cpuid, ret; + unsigned long hartid; + bool irq_found =3D false; + + for_each_online_cpu(cpuid) { + hartid =3D cpuid_to_hartid_map(cpuid); + irq_name =3D devm_kasprintf(ipc->dev, GFP_KERNEL, "hart-%lu", hartid); + ret =3D platform_get_irq_byname_optional(pdev, irq_name); + if (ret <=3D 0) + continue; + + ipc->cluster_cfg[hartid].irq =3D ret; + ret =3D devm_request_irq(ipc->dev, ipc->cluster_cfg[hartid].irq, + mchp_ipc_cluster_aggr_isr, IRQF_SHARED, + "miv-ihc-irq", ipc); + if (ret) + return ret; + + ipc->cluster_cfg[hartid].buf_base =3D devm_kmalloc(ipc->dev, + sizeof(struct mchp_ipc_status), + GFP_KERNEL); + + if (!ipc->cluster_cfg[hartid].buf_base) + return -ENOMEM; + + ipc->cluster_cfg[hartid].buf_base_addr =3D __pa(ipc->cluster_cfg[hartid]= .buf_base); + + irq_found =3D true; + } + + return irq_found; +} + +static int mchp_ipc_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mchp_ipc_mbox_info ipc_info; + struct mchp_ipc_sbi_mbox *ipc; + struct mchp_ipc_sbi_chan *priv; + bool irq_avail =3D false; + int ret; + u32 chan_id; + + ret =3D sbi_probe_extension(SBI_EXT_MICROCHIP_TECHNOLOGY); + if (ret <=3D 0) + return dev_err_probe(dev, ret, "Microchip SBI extension not detected\n"); + + ipc =3D devm_kzalloc(dev, sizeof(*ipc), GFP_KERNEL); + if (!ipc) + return -ENOMEM; + + platform_set_drvdata(pdev, ipc); + + ipc->buf_base =3D devm_kmalloc(dev, sizeof(struct mchp_ipc_mbox_info), GF= P_KERNEL); + if (!ipc->buf_base) + return -ENOMEM; + + ipc->buf_base_addr =3D __pa(ipc->buf_base); + + ret =3D mchp_ipc_sbi_send(SBI_EXT_IPC_PROBE, ipc->buf_base_addr); + if (ret < 0) + return dev_err_probe(dev, ret, "could not probe IPC SBI service\n"); + + memcpy(&ipc_info, ipc->buf_base, sizeof(struct mchp_ipc_mbox_info)); + ipc->controller.num_chans =3D ipc_info.num_channels; + ipc->hw_type =3D ipc_info.hw_type; + + ipc->chans =3D devm_kcalloc(dev, ipc->controller.num_chans, sizeof(*ipc->= chans), GFP_KERNEL); + if (!ipc->chans) + return -ENOMEM; + + ipc->dev =3D dev; + ipc->controller.txdone_irq =3D true; + ipc->controller.dev =3D ipc->dev; + ipc->controller.ops =3D &mchp_ipc_ops; + ipc->controller.chans =3D ipc->chans; + ipc->controller.of_xlate =3D mchp_ipc_mbox_xlate; + + for (chan_id =3D 0; chan_id < ipc->controller.num_chans; chan_id++) { + priv =3D devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + ipc->chans[chan_id].con_priv =3D priv; + priv->id =3D chan_id; + } + + if (ipc->hw_type =3D=3D MIV_IHC) { + ipc->cluster_cfg =3D devm_kcalloc(dev, num_online_cpus(), + sizeof(struct mchp_ipc_cluster_cfg), + GFP_KERNEL); + if (!ipc->cluster_cfg) + return -ENOMEM; + + if (mchp_ipc_get_cluster_aggr_irq(ipc)) + irq_avail =3D true; + } + + if (!irq_avail) + return dev_err_probe(dev, -ENODEV, "missing interrupt property\n"); + + ret =3D devm_mbox_controller_register(dev, &ipc->controller); + if (ret) + return dev_err_probe(dev, ret, + "Inter-Processor communication (IPC) registration failed\n"); + + return 0; +} + +static const struct of_device_id mchp_ipc_of_match[] =3D { + {.compatible =3D "microchip,sbi-ipc", }, + {} +}; +MODULE_DEVICE_TABLE(of, mchp_ipc_of_match); + +static struct platform_driver mchp_ipc_driver =3D { + .driver =3D { + .name =3D "microchip_ipc", + .of_match_table =3D mchp_ipc_of_match, + }, + .probe =3D mchp_ipc_probe, +}; + +module_platform_driver(mchp_ipc_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Valentina Fernandez "); +MODULE_DESCRIPTION("Microchip Inter-Processor Communication (IPC) driver"); diff --git a/include/linux/mailbox/mchp-ipc.h b/include/linux/mailbox/mchp-= ipc.h new file mode 100644 index 000000000000..f084ac9e291b --- /dev/null +++ b/include/linux/mailbox/mchp-ipc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + *Copyright (c) 2024 Microchip Technology Inc. All rights reserved. + */ + +#ifndef _LINUX_MCHP_IPC_H_ +#define _LINUX_MCHP_IPC_H_ + +#include +#include + +struct mchp_ipc_msg { + u32 *buf; + u16 size; +}; + +struct mchp_ipc_sbi_chan { + void *buf_base_tx; + void *buf_base_rx; + void *msg_buf_tx; + void *msg_buf_rx; + phys_addr_t buf_base_tx_addr; + phys_addr_t buf_base_rx_addr; + phys_addr_t msg_buf_tx_addr; + phys_addr_t msg_buf_rx_addr; + int chan_aggregated_irq; + int mp_irq; + int mc_irq; + u32 id; + u32 max_msg_size; +}; + +#endif /* _LINUX_MCHP_IPC_H_ */ --=20 2.34.1