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charset="utf-8" Add display controller subsystem in i.MX8qxp SoC. Signed-off-by: Liu Ying acked-by from a DT maintainer for those aliases as well? --- v4: * No change. v3: * No change. v2: * New patch. (Krzysztof) .../arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | 408 ++++++++++++++++++ .../boot/dts/freescale/imx8qxp-ss-dc.dtsi | 236 ++++++++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 25 +- 3 files changed, 668 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi b/arch/arm64/bo= ot/dts/freescale/imx8-ss-dc0.dtsi new file mode 100644 index 000000000000..0db345204b89 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include +#include +#include + +dc0_axi_ext_clk: clock-dc0-axi-ext { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <800000000>; + clock-output-names =3D "dc0_axi_ext_clk"; +}; + +dc0_axi_int_clk: clock-dc0-axi-int { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <400000000>; + clock-output-names =3D "dc0_axi_int_clk"; +}; + +dc0_cfg_clk: clock-dc0-cfg { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100000000>; + clock-output-names =3D "dc0_cfg_clk"; +}; + +dc0_subsys: bus@56000000 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x56000000 0x0 0x56000000 0x1000000>; + + dc0_irqsteer: interrupt-controller@56000000 { + compatible =3D "fsl,imx-irqsteer"; + reg =3D <0x56000000 0x1000>; + interrupt-controller; + interrupt-parent =3D <&gic>; + #interrupt-cells =3D <1>; + interrupts =3D , + , + , + , + , + , + , + ; + clocks =3D <&dc0_lis_lpcg IMX_LPCG_CLK_4>; + clock-names =3D "ipg"; + fsl,channel =3D <0>; + fsl,num-irqs =3D <512>; + }; + + dc0_disp_lpcg: clock-controller@56010000 { + reg =3D <0x56010000 0x4>; + #clock-cells =3D <1>; + clocks =3D <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>; + clock-indices =3D , ; + clock-output-names =3D "dc0_disp0_lpcg_clk", "dc0_disp1_lpcg_clk"; + power-domains =3D <&pd IMX_SC_R_DC_0>; + }; + + dc0_lis_lpcg: clock-controller@56010004 { + reg =3D <0x56010004 0x4>; + #clock-cells =3D <1>; + clocks =3D <&dc0_cfg_clk>; + clock-indices =3D ; + clock-output-names =3D "dc0_lis_lpcg_ipg_clk"; + power-domains =3D <&pd IMX_SC_R_DC_0>; + }; + + dc0_disp_ctrl_link_mst0_lpcg: clock-controller@56010008 { + reg =3D <0x56010008 0x4>; + #clock-cells =3D <1>; + clocks =3D <&dc0_cfg_clk>; + clock-indices =3D ; + clock-output-names =3D "dc0_disp_ctrl_link_mst0_lpcg_msi_clk"; + power-domains =3D <&pd IMX_SC_R_DC_0>; + }; + + dc0_pixel_combiner_lpcg: clock-controller@56010010 { + reg =3D <0x56010010 0x4>; + #clock-cells =3D <1>; + clocks =3D <&dc0_cfg_clk>; + clock-indices =3D ; + clock-output-names =3D "dc0_pixel_combiner_lpcg_apb_clk"; + power-domains =3D <&pd IMX_SC_R_DC_0>; + }; + + dc0_lpcg: clock-controller@56010014 { + reg =3D <0x56010014 0x4>; + #clock-cells =3D <1>; + clocks =3D <&dc0_cfg_clk>, <&dc0_axi_int_clk>; + clock-indices =3D , ; + clock-output-names =3D "dc0_lpcg_cfg_clk", + "dc0_lpcg_axi_clk"; + power-domains =3D <&pd IMX_SC_R_DC_0>; + }; + + dc0_pc: pixel-combiner@56020000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x56020000 0x10000>; + clocks =3D <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>; + clock-names =3D "apb"; + power-domains =3D <&pd IMX_SC_R_DC_0>; + status =3D "disabled"; + + channel@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + status =3D "disabled"; + + port@0 { + reg =3D <0>; + + dc0_pixel_combiner_ch0_dc0_disp0: endpoint { + remote-endpoint =3D <&dc0_disp0_dc0_pixel_combiner_ch0>; + }; + }; + + port@1 { + reg =3D <1>; + + dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint { + remote-endpoint =3D <&dc0_pixel_link0_dc0_pixel_combiner_ch0>; + }; + }; + }; + + channel@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + status =3D "disabled"; + + port@0 { + reg =3D <0>; + + dc0_pixel_combiner_ch1_dc0_disp1: endpoint { + remote-endpoint =3D <&dc0_disp1_dc0_pixel_combiner_ch1>; + }; + }; + + port@1 { + reg =3D <1>; + + dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint { + remote-endpoint =3D <&dc0_pixel_link1_dc0_pixel_combiner_ch1>; + }; + }; + }; + }; + + dc0: display-controller@56180000 { + reg =3D <0x56180000 0x40000>; + clocks =3D <&dc0_lpcg IMX_LPCG_CLK_4>; + power-domains =3D <&pd IMX_SC_R_DC_0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + status =3D "disabled"; + + dc0_intc: interrupt-controller@56180040 { + reg =3D <0x56180040 0x60>; + clocks =3D <&dc0_lpcg IMX_LPCG_CLK_5>; + interrupt-controller; + interrupt-parent =3D <&dc0_irqsteer>; + #interrupt-cells =3D <1>; + interrupts =3D <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <5>, + <0>, <1>, <2>, <3>, + <4>, <82>, <83>, <84>, + <85>, <209>, <210>, <211>, + <212>; + interrupt-names =3D "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "reserved", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + }; + + dc0_pixel_engine: pixel-engine@56180800 { + reg =3D <0x56180800 0xac00>; + clocks =3D <&dc0_lpcg IMX_LPCG_CLK_5>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + dc0_constframe0: constframe@56180960 { + reg =3D <0x56180960 0xc>, <0x56184400 0x20>; + reg-names =3D "pec", "cfg"; + }; + + dc0_extdst0: extdst@56180980 { + reg =3D <0x56180980 0x1c>, <0x56184800 0x28>; + reg-names =3D "pec", "cfg"; + interrupt-parent =3D <&dc0_intc>; + interrupts =3D <3>, <4>, <5>; + interrupt-names =3D "shdload", "framecomplete", "seqcomplete"; + }; + + dc0_constframe4: constframe@561809a0 { + reg =3D <0x561809a0 0xc>, <0x56184c00 0x20>; + reg-names =3D "pec", "cfg"; + }; + + dc0_extdst4: extdst@561809c0 { + reg =3D <0x561809c0 0x1c>, <0x56185000 0x28>; + reg-names =3D "pec", "cfg"; + interrupt-parent =3D <&dc0_intc>; + interrupts =3D <6>, <7>, <8>; + interrupt-names =3D "shdload", "framecomplete", "seqcomplete"; + }; + + dc0_constframe1: constframe@561809e0 { + reg =3D <0x561809e0 0xc>, <0x56185400 0x20>; + reg-names =3D "pec", "cfg"; + }; + + dc0_extdst1: extdst@56180a00 { + reg =3D <0x56180a00 0x1c>, <0x56185800 0x28>; + reg-names =3D "pec", "cfg"; + interrupt-parent =3D <&dc0_intc>; + interrupts =3D <9>, <10>, <11>; + interrupt-names =3D "shdload", "framecomplete", "seqcomplete"; + }; + + dc0_constframe5: constframe@56180a20 { + reg =3D <0x56180a20 0xc>, <0x56185c00 0x20>; + reg-names =3D "pec", "cfg"; + }; + + dc0_extdst5: extdst@56180a40 { + reg =3D <0x56180a40 0x1c>, <0x56186000 0x28>; + reg-names =3D "pec", "cfg"; + interrupt-parent =3D <&dc0_intc>; + interrupts =3D <12>, <13>, <14>; + interrupt-names =3D "shdload", "framecomplete", "seqcomplete"; + }; + + dc0_fetchwarp2: fetchwarp@56180a60 { + reg =3D <0x56180a60 0x10>, <0x56186400 0x190>; + reg-names =3D "pec", "cfg"; + }; + + dc0_fetchlayer0: fetchlayer@56180ac0 { + reg =3D <0x56180ac0 0xc>, <0x56188400 0x404>; + reg-names =3D "pec", "cfg"; + }; + + dc0_layerblend0: layerblend@56180ba0 { + reg =3D <0x56180ba0 0x10>, <0x5618a400 0x20>; + reg-names =3D "pec", "cfg"; + }; + + dc0_layerblend1: layerblend@56180bc0 { + reg =3D <0x56180bc0 0x10>, <0x5618a800 0x20>; + reg-names =3D "pec", "cfg"; + }; + + dc0_layerblend2: layerblend@56180be0 { + reg =3D <0x56180be0 0x10>, <0x5618ac00 0x20>; + reg-names =3D "pec", "cfg"; + }; + + dc0_layerblend3: layerblend@56180c00 { + reg =3D <0x56180c00 0x10>, <0x5618b000 0x20>; + reg-names =3D "pec", "cfg"; + }; + }; + + dc0_display_engine0: display-engine@5618b400 { + reg =3D <0x5618b400 0x14>, <0x5618b800 0x1c00>; + reg-names =3D "top", "cfg"; + interrupt-parent =3D <&dc0_intc>; + interrupts =3D <15>, <16>, <17>; + interrupt-names =3D "shdload", "framecomplete", "seqcomplete"; + power-domains =3D <&pd IMX_SC_R_DC_0_PLL_0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + dc0_framegen0: framegen@5618b800 { + reg =3D <0x5618b800 0x98>; + clocks =3D <&dc0_disp_lpcg IMX_LPCG_CLK_0>; + interrupt-parent =3D <&dc0_intc>; + interrupts =3D <18>, <19>, <20>, <21>, + <41>, <42>, <43>, <44>; + interrupt-names =3D "int0", "int1", "int2", "int3", + "primsync_on", "primsync_off", + "secsync_on", "secsync_off"; + }; + + dc0_tcon0: tcon@5618c800 { + reg =3D <0x5618c800 0x588>; + + port { + dc0_disp0_dc0_pixel_combiner_ch0: endpoint { + remote-endpoint =3D <&dc0_pixel_combiner_ch0_dc0_disp0>; + }; + }; + }; + }; + + dc0_display_engine1: display-engine@5618b420 { + reg =3D <0x5618b420 0x14>, <0x5618d400 0x1c00>; + reg-names =3D "top", "cfg"; + interrupt-parent =3D <&dc0_intc>; + interrupts =3D <25>, <26>, <27>; + interrupt-names =3D "shdload", "framecomplete", "seqcomplete"; + power-domains =3D <&pd IMX_SC_R_DC_0_PLL_1>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + dc0_framegen1: framegen@5618d400 { + reg =3D <0x5618d400 0x98>; + clocks =3D <&dc0_disp_lpcg IMX_LPCG_CLK_1>; + interrupt-parent =3D <&dc0_intc>; + interrupts =3D <28>, <29>, <30>, <31>, + <45>, <46>, <47>, <48>; + interrupt-names =3D "int0", "int1", "int2", "int3", + "primsync_on", "primsync_off", + "secsync_on", "secsync_off"; + }; + + dc0_tcon1: tcon@5618e400 { + reg =3D <0x5618e400 0x588>; + + port { + dc0_disp1_dc0_pixel_combiner_ch1: endpoint { + remote-endpoint =3D <&dc0_pixel_combiner_ch1_dc0_disp1>; + }; + }; + }; + }; + }; + + dc0_pl_msi_bus: bus@56200000 { + reg =3D <0x56200000 0x100000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupt-parent =3D <&dc0_irqsteer>; + interrupts =3D <320>; + ranges; + clocks =3D <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>, + <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>; + clock-names =3D "msi", "ahb"; + power-domains =3D <&pd IMX_SC_R_DC_0>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi b/arch/arm64/= boot/dts/freescale/imx8qxp-ss-dc.dtsi new file mode 100644 index 000000000000..299720d8c99e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +&dc0 { + compatible =3D "fsl,imx8qxp-dc"; +}; + +&dc0_constframe0 { + compatible =3D "fsl,imx8qxp-dc-constframe"; +}; + +&dc0_constframe1 { + compatible =3D "fsl,imx8qxp-dc-constframe"; +}; + +&dc0_constframe4 { + compatible =3D "fsl,imx8qxp-dc-constframe"; +}; + +&dc0_constframe5 { + compatible =3D "fsl,imx8qxp-dc-constframe"; +}; + +&dc0_disp_ctrl_link_mst0_lpcg { + compatible =3D "fsl,imx8qxp-lpcg"; +}; + +&dc0_disp_lpcg { + compatible =3D "fsl,imx8qxp-lpcg"; +}; + +&dc0_display_engine0 { + compatible =3D "fsl,imx8qxp-dc-display-engine"; +}; + +&dc0_display_engine1 { + compatible =3D "fsl,imx8qxp-dc-display-engine"; +}; + +&dc0_extdst0 { + compatible =3D "fsl,imx8qxp-dc-extdst"; +}; + +&dc0_extdst1 { + compatible =3D "fsl,imx8qxp-dc-extdst"; +}; + +&dc0_extdst4 { + compatible =3D "fsl,imx8qxp-dc-extdst"; +}; + +&dc0_extdst5 { + compatible =3D "fsl,imx8qxp-dc-extdst"; +}; + +&dc0_fetchlayer0 { + compatible =3D "fsl,imx8qxp-dc-fetchlayer"; +}; + +&dc0_fetchwarp2 { + compatible =3D "fsl,imx8qxp-dc-fetchwarp"; +}; + +&dc0_framegen0 { + compatible =3D "fsl,imx8qxp-dc-framegen"; +}; + +&dc0_framegen1 { + compatible =3D "fsl,imx8qxp-dc-framegen"; +}; + +&dc0_intc { + compatible =3D "fsl,imx8qxp-dc-intc"; +}; + +&dc0_layerblend0 { + compatible =3D "fsl,imx8qxp-dc-layerblend"; +}; + +&dc0_layerblend1 { + compatible =3D "fsl,imx8qxp-dc-layerblend"; +}; + +&dc0_layerblend2 { + compatible =3D "fsl,imx8qxp-dc-layerblend"; +}; + +&dc0_layerblend3 { + compatible =3D "fsl,imx8qxp-dc-layerblend"; +}; + +&dc0_lis_lpcg { + compatible =3D "fsl,imx8qxp-lpcg"; +}; + +&dc0_lpcg { + compatible =3D "fsl,imx8qxp-lpcg"; +}; + +&dc0_pc { + compatible =3D "fsl,imx8qxp-pixel-combiner"; +}; + +&dc0_pixel_combiner_lpcg { + compatible =3D "fsl,imx8qxp-lpcg"; +}; + +&dc0_pixel_engine { + compatible =3D "fsl,imx8qxp-dc-pixel-engine"; +}; + +&dc0_pl_msi_bus { + compatible =3D "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus"; +}; + +&dc0_tcon0 { + compatible =3D "fsl,imx8qxp-dc-tcon"; +}; + +&dc0_tcon1 { + compatible =3D "fsl,imx8qxp-dc-tcon"; +}; + +&scu { + dc0_pixel_link0: dc0-pixel-link0 { + compatible =3D "fsl,imx8qxp-dc-pixel-link"; + fsl,dc-id =3D /bits/ 8 <0>; + fsl,dc-stream-id =3D /bits/ 8 <0>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* from dc0 pixel combiner channel0 */ + port@0 { + reg =3D <0>; + + dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint { + remote-endpoint =3D <&dc0_pixel_combiner_ch0_dc0_pixel_link0>; + }; + }; + + /* to PXL2DPIs in MIPI/LVDS combo subsystems */ + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + status =3D "disabled"; + + dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 { + reg =3D <0>; + }; + + dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 { + reg =3D <1>; + }; + }; + + /* unused */ + port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + /* unused */ + port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + /* to imaging subsystem */ + port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + + dc0_pixel_link1: dc0-pixel-link1 { + compatible =3D "fsl,imx8qxp-dc-pixel-link"; + fsl,dc-id =3D /bits/ 8 <0>; + fsl,dc-stream-id =3D /bits/ 8 <1>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* from dc0 pixel combiner channel1 */ + port@0 { + reg =3D <0>; + + dc0_pixel_link1_dc0_pixel_combiner_ch1: endpoint { + remote-endpoint =3D <&dc0_pixel_combiner_ch1_dc0_pixel_link1>; + }; + }; + + /* to PXL2DPIs in MIPI/LVDS combo subsystems */ + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + status =3D "disabled"; + + dc0_pixel_link1_mipi_lvds_1_pxl2dpi: endpoint@0 { + reg =3D <0>; + }; + + dc0_pixel_link1_mipi_lvds_0_pxl2dpi: endpoint@1 { + reg =3D <1>; + }; + }; + + /* to parallel display interface in ADMA subsystem */ + port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + /* unused */ + port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + /* unused */ + port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8qxp.dtsi index 05138326f0a5..35cc82cbbcd1 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -20,6 +20,27 @@ / { #size-cells =3D <2>; =20 aliases { + dc0 =3D &dc0; + dc0-constframe0 =3D &dc0_constframe0; + dc0-constframe1 =3D &dc0_constframe1; + dc0-constframe4 =3D &dc0_constframe4; + dc0-constframe5 =3D &dc0_constframe5; + dc0-display-engine0 =3D &dc0_display_engine0; + dc0-display-engine1 =3D &dc0_display_engine1; + dc0-extdst0 =3D &dc0_extdst0; + dc0-extdst1 =3D &dc0_extdst1; + dc0-extdst4 =3D &dc0_extdst4; + dc0-extdst5 =3D &dc0_extdst5; + dc0-fetchlayer0 =3D &dc0_fetchlayer0; + dc0-fetchwarp2 =3D &dc0_fetchwarp2; + dc0-framegen0 =3D &dc0_framegen0; + dc0-framegen1 =3D &dc0_framegen1; + dc0-layerblend0 =3D &dc0_layerblend0; + dc0-layerblend1 =3D &dc0_layerblend1; + dc0-layerblend2 =3D &dc0_layerblend2; + dc0-layerblend3 =3D &dc0_layerblend3; + dc0-tcon0 =3D &dc0_tcon0; + dc0-tcon1 =3D &dc0_tcon1; ethernet0 =3D &fec1; ethernet1 =3D &fec2; gpio0 =3D &lsio_gpio0; @@ -206,7 +227,7 @@ psci { method =3D "smc"; }; =20 - system-controller { + scu: system-controller { compatible =3D "fsl,imx-scu"; mbox-names =3D "tx0", "rx0", @@ -323,6 +344,7 @@ map0 { #include "imx8-ss-vpu.dtsi" #include "imx8-ss-cm40.dtsi" #include "imx8-ss-gpu0.dtsi" + #include "imx8-ss-dc0.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" @@ -332,6 +354,7 @@ map0 { =20 #include "imx8qxp-ss-img.dtsi" #include "imx8qxp-ss-vpu.dtsi" +#include "imx8qxp-ss-dc.dtsi" #include "imx8qxp-ss-adma.dtsi" #include "imx8qxp-ss-conn.dtsi" #include "imx8qxp-ss-lsio.dtsi" --=20 2.34.1